Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25980

1

T1

12

T2

20

T3

64

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22140

1

T1

12

T2

20

T3

40

auto[ADC_CTRL_FILTER_COND_OUT]

3840

1

T3

24

T7

6

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19505

1

T1

12

T2

20

T3

26

auto[1]

6475

1

T3

38

T4

2

T6

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21875

1

T1

12

T2

20

T3

32

auto[1]

4105

1

T3

32

T5

20

T6

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	624	1			T3	26		T7	2		T11	3
values[0]	8	1			T291	8		-	-		-	-
values[1]	886	1			T38	2		T187	9		T220	21
values[2]	3032	1			T4	2		T6	9		T10	15
values[3]	765	1			T5	23		T12	1		T13	3
values[4]	766	1			T7	2		T12	1		T128	1
values[5]	685	1			T9	1		T29	7		T131	13
values[6]	713	1			T136	14		T130	5		T138	6
values[7]	632	1			T29	19		T36	27		T136	11
values[8]	793	1			T3	14		T5	22		T7	4
values[9]	900	1			T3	24		T7	5		T9	1
minimum	16176	1			T1	12		T2	20		T7	102

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	964	1			T24	1		T28	37		T31	17
values[1]	2946	1			T4	2		T6	9		T10	15
values[2]	820	1			T5	23		T13	3		T128	1
values[3]	688	1			T7	2		T12	1		T29	7
values[4]	711	1			T9	1		T138	6		T131	13
values[5]	680	1			T136	14		T16	4		T130	5
values[6]	729	1			T29	19		T36	27		T136	11
values[7]	754	1			T3	14		T5	22		T7	4
values[8]	752	1			T3	24		T9	1		T131	15
values[9]	172	1			T3	26		T7	5		T37	2
minimum	16764	1			T1	12		T2	20		T7	104

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

4368

1

T3

29

T5

23

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T24	1		T31	10		T187	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T28	17		T16	1		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1570	1			T4	2		T6	1		T10	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	1		T139	4		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	14		T13	3		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T129	14		T137	2		T246	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T202	1		T39	1		T132	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T7	2		T12	1		T29	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T9	1		T138	6		T265	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T131	13		T220	12		T215	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T136	1		T189	5		T249	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T16	3		T130	1		T247	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T29	17		T169	1		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T36	13		T136	1		T139	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	6		T5	11		T138	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T7	2		T39	2		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T160	1		T161	1		T171	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T3	12		T9	1		T131	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T3	14		T7	3		T173	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T37	1		T131	20		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16453	1			T1	12		T2	20		T7	99
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T220	12		T161	1		T264	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T31	7		T187	6		T189	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T28	20		T42	1		T189	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T6	8		T71	11		T73	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T139	11		T140	14		T247	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T5	9		T137	3		T130	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T129	14		T137	15		T197	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T40	7		T148	11		T135	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T29	1		T132	6		T42	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T265	11		T160	2		T255	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T220	17		T215	11		T145	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T136	13		T189	1		T142	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T16	1		T130	4		T247	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T29	2		T169	12		T161	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T36	14		T136	10		T139	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	8		T5	11		T140	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	2		T247	11		T150	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T160	14		T171	12		T257	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T3	12		T248	12		T171	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T3	12		T7	2		T173	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T37	1		T142	7		T107	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	5		T31	1		T37	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T220	9		T161	11		T264	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	459	1			T3	14		T7	2		T11	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T37	1		T131	20		T204	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T291	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T187	3		T189	2		T253	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T38	2		T220	12		T42	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1554	1			T4	2		T6	1		T10	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T28	17		T16	1		T139	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	14		T13	3		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	1		T129	14		T197	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T130	1		T202	1		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T7	2		T12	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	1		T148	1		T265	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T29	6		T131	13		T132	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T136	1		T138	6		T189	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T130	1		T247	14		T257	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T29	17		T169	1		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T36	13		T136	1		T16	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	6		T5	11		T138	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T7	2		T39	2		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	3		T140	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T3	12		T9	1		T131	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16045	1			T1	12		T2	20		T7	97
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T3	12		T320	10		T173	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T37	1		T300	8		T107	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T187	6		T189	1		T253	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T220	9		T42	1		T189	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T6	8		T31	7		T71	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T28	20		T139	11		T140	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T5	9		T129	8		T137	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T129	14		T197	10		T160	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T130	9		T40	7		T135	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T137	15		T42	1		T214	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T148	11		T265	11		T160	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T29	1		T132	6		T220	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T136	13		T189	1		T255	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T130	4		T247	11		T257	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T29	2		T169	12		T161	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T36	14		T136	10		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	8		T5	11		T140	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	2		T135	12		T275	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	2		T140	9		T160	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	12		T247	11		T248	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T24	1		T31	11		T187	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T28	21		T16	1		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T4	2		T6	9		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	1		T139	12		T140	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	10		T13	2		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T129	15		T137	17		T246	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T202	1		T39	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	2		T12	1		T29	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	1		T138	1		T265	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T131	1		T220	18		T215	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T136	14		T189	4		T249	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T16	3		T130	5		T247	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T29	3		T169	13		T161	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T36	17		T136	11		T139	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	9		T5	12		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T7	4		T39	2		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T160	15		T161	1		T171	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	13		T9	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T3	13		T7	3		T173	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T37	2		T131	1		T142	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16592	1			T1	12		T2	20		T7	104
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T220	10		T161	12		T264	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T31	6		T187	2		T264	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T28	16		T42	1		T133	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T10	14		T25	18		T37	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T139	3		T247	14		T165	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T5	13		T13	1		T229	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T129	13		T197	11		T279	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T132	7		T40	4		T215	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T29	5		T132	2		T42	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T138	5		T265	11		T285	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T131	12		T220	11		T215	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T189	2		T142	15		T256	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T16	1		T247	13		T257	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T29	16		T263	9		T321	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T36	10		T139	12		T150	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T3	5		T5	10		T138	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T247	10		T150	12		T256	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T257	8		T270	11		T322	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	11		T131	14		T248	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T3	13		T7	2		T173	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T131	19		T287	13		T107	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T253	8		T282	6		T323	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T220	11		T264	8		T279	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	465	1			T3	13		T7	2		T11	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T37	2		T131	1		T204	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T291	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T187	7		T189	3		T253	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T38	2		T220	10		T42	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T4	2		T6	9		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T28	21		T16	1		T139	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	10		T13	2		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T12	1		T129	15		T197	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T130	10		T202	1		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T7	2		T12	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T9	1		T148	12		T265	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T29	2		T131	1		T132	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T136	14		T138	1		T189	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T130	5		T247	12		T257	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T29	3		T169	13		T161	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T36	17		T136	11		T16	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	9		T5	12		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T7	4		T39	2		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T7	3		T140	10		T160	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T3	13		T9	1		T131	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16176	1			T1	12		T2	20		T7	102
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T3	13		T322	9		T173	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T131	19		T300	2		T287	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T291	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T187	2		T253	8		T264	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T220	11		T42	1		T133	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1212	1			T10	14		T25	18		T31	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T28	16		T139	3		T134	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	13		T13	1		T129	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T129	13		T197	11		T144	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T132	7		T40	4		T229	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T42	2		T279	13		T143	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T265	11		T285	6		T180	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T29	5		T131	12		T132	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T138	5		T189	2		T142	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T247	13		T257	10		T213	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T29	16		T263	9		T301	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T36	10		T16	1		T139	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	5		T5	10		T138	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T275	13		T284	3		T256	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T7	2		T257	8		T270	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T3	11		T131	14		T247	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

auto[0]

4368

1

T3

29

T5

23

T7

2