Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25980

1

T1

12

T2

20

T3

64

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22312

1

T1

12

T2

20

T3

26

auto[ADC_CTRL_FILTER_COND_OUT]

3668

1

T3

38

T5

45

T9

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19872

1

T1

12

T2

20

T3

38

auto[1]

6108

1

T3

26

T4

2

T5

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21875

1

T1

12

T2

20

T3

32

auto[1]

4105

1

T3

32

T5

20

T6

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	10	1			T76	8		T324	2		-	-
values[0]	66	1			T220	21		T153	2		T306	6
values[1]	699	1			T131	13		T38	2		T247	25
values[2]	621	1			T7	2		T29	26		T16	1
values[3]	702	1			T7	5		T128	1		T138	18
values[4]	881	1			T3	14		T12	1		T31	17
values[5]	795	1			T3	50		T37	2		T220	29
values[6]	621	1			T36	27		T129	18		T137	4
values[7]	667	1			T9	1		T12	1		T24	1
values[8]	895	1			T5	22		T7	4		T37	2
values[9]	3465	1			T4	2		T5	23		T6	9
minimum	16558	1			T1	12		T2	20		T7	104

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	954	1			T7	2		T129	28		T131	13
values[1]	569	1			T7	5		T29	19		T16	1
values[2]	729	1			T3	14		T29	7		T137	13
values[3]	946	1			T3	24		T12	1		T128	1
values[4]	679	1			T3	26		T31	17		T37	2
values[5]	616	1			T9	1		T36	27		T128	1
values[6]	2954	1			T4	2		T6	9		T7	4
values[7]	874	1			T5	22		T37	2		T136	14
values[8]	890	1			T5	23		T9	1		T13	3
values[9]	178	1			T130	5		T39	2		T42	4
minimum	16591	1			T1	12		T2	20		T7	104

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

4368

1

T3

29

T5

23

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T7	2		T129	14		T220	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T131	13		T38	2		T247	29
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	3		T29	17		T285	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T16	1		T138	18		T187	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T29	6		T137	1		T40	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	6		T132	3		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T12	1		T128	1		T138	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T3	12		T42	2		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	14		T325	1		T266	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T31	10		T37	2		T220	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T36	13		T128	1		T129	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T9	1		T131	15		T246	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1583	1			T4	2		T6	1		T7	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T24	1		T28	17		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T37	1		T136	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	11		T139	13		T247	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T13	3		T161	1		T256	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T5	14		T9	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T130	1		T42	3		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T39	2		T321	16		T326	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16427	1			T1	12		T2	20		T7	99
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T142	16		T327	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T129	14		T220	9		T214	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T247	22		T248	12		T256	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T7	2		T29	2		T285	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T187	6		T148	11		T150	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T29	1		T137	12		T40	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	8		T132	6		T140	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T139	11		T265	11		T256	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	12		T42	1		T135	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T3	12		T17	1		T271	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T31	7		T220	17		T189	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T36	14		T129	8		T137	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T133	18		T263	6		T255	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1023	1			T6	8		T7	2		T71	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T28	20		T16	1		T137	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T37	1		T136	13		T252	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	11		T139	12		T247	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T161	11		T256	5		T262	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	9		T136	10		T169	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T130	4		T42	1		T135	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T321	13		T326	3		T20	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T142	16		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T76	4		T324	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T220	12		T153	1		T306	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T146	9		T328	8		T329	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T214	1		T161	1		T215	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T131	13		T38	2		T247	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	2		T29	23		T129	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T16	1		T187	3		T247	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	3		T128	1		T289	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T138	18		T132	3		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T12	1		T137	1		T138	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	6		T31	10		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	14		T265	12		T142	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T3	12		T37	2		T220	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T36	13		T129	10		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T131	15		T133	15		T215	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	1		T128	1		T272	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T9	1		T24	1		T28	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T7	2		T37	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T5	11		T16	3		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1689	1			T4	2		T6	1		T10	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	428	1			T5	14		T9	1		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16427	1			T1	12		T2	20		T7	99
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T76	4		T324	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T220	9		T153	1		T330	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T146	4		T329	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T214	15		T215	5		T153	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T247	11		T248	12		T150	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T29	3		T129	14		T40	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T187	6		T247	11		T256	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	2		T160	14		T284	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T132	6		T140	9		T148	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T137	12		T139	11		T134	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	8		T31	7		T135	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	12		T265	11		T271	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	12		T220	17		T42	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T36	14		T129	8		T137	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T133	18		T215	11		T255	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T272	1		T264	12		T292	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T28	20		T140	14		T253	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	2		T37	1		T136	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	11		T16	1		T137	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1072	1			T6	8		T71	11		T73	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T5	9		T136	10		T169	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T7	2		T129	15		T220	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T131	1		T38	2		T247	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	3		T29	3		T285	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T16	1		T138	1		T187	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T29	2		T137	13		T40	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	9		T132	7		T140	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T12	1		T128	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	13		T42	2		T135	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	13		T325	1		T266	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T31	11		T37	1		T220	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T36	17		T128	1		T129	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T9	1		T131	1		T246	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T4	2		T6	9		T7	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T24	1		T28	21		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T37	2		T136	14		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T5	12		T139	13		T247	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	2		T161	12		T256	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T5	10		T9	1		T136	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T130	5		T42	2		T135	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T39	2		T321	14		T326	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16558	1			T1	12		T2	20		T7	104
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T142	17		T327	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T129	13		T220	11		T215	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T131	12		T247	27		T248	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T7	2		T29	16		T285	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T138	17		T187	2		T150	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T29	5		T40	4		T134	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	5		T132	2		T279	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T138	5		T132	7		T139	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	11		T42	1		T229	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	13		T266	4		T270	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T31	6		T37	1		T220	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T36	10		T129	9		T150	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T131	14		T133	14		T263	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T10	14		T25	18		T223	32
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T28	16		T16	1		T253	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T252	6		T257	15		T270	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	10		T139	12		T247	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	1		T256	12		T262	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T5	13		T131	19		T189	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T42	2		T331	2		T332	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T321	15		T326	2		T20	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T142	15		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T76	6		T324	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T220	10		T153	2		T306	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T146	8		T328	1		T329	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T214	16		T161	1		T215	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T131	1		T38	2		T247	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	2		T29	5		T129	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T16	1		T187	7		T247	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	3		T128	1		T289	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T138	1		T132	7		T140	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T12	1		T137	13		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	9		T31	11		T135	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	13		T265	12		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T3	13		T37	1		T220	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T36	17		T129	9		T137	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T131	1		T133	19		T215	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	1		T128	1		T272	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	1		T24	1		T28	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	4		T37	2		T136	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T5	12		T16	3		T137	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1457	1			T4	2		T6	9		T10	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T5	10		T9	1		T136	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16558	1			T1	12		T2	20		T7	104
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T76	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T220	11		T306	5		T330	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T146	5		T328	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T215	9		T153	13		T293	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T131	12		T247	13		T248	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T29	21		T129	13		T40	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T187	2		T247	14		T256	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T284	3		T256	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T138	17		T132	2		T279	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T138	5		T132	7		T139	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	5		T31	6		T229	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	13		T265	11		T142	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	11		T37	1		T220	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T36	10		T129	9		T150	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T131	14		T133	14		T215	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T264	8		T180	9		T258	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T28	16		T253	8		T165	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T252	6		T261	2		T257	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	10		T16	1		T139	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T10	14		T13	1		T25	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T5	13		T131	19		T189	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

auto[0]

4368

1

T3

29

T5

23

T7

2