Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25980

1

T1

12

T2

20

T3

64

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22128

1

T1

12

T2

20

T3

26

auto[ADC_CTRL_FILTER_COND_OUT]

3852

1

T3

38

T5

45

T7

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19879

1

T1

12

T2

20

T3

38

auto[1]

6101

1

T3

26

T4

2

T5

45

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21875

1

T1

12

T2

20

T3

32

auto[1]

4105

1

T3

32

T5

20

T6

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	242	1			T130	5		T39	2		T189	6
values[0]	35	1			T220	21		T333	14		-	-
values[1]	713	1			T38	2		T247	25		T214	16
values[2]	643	1			T7	2		T29	19		T16	1
values[3]	644	1			T7	5		T29	7		T138	18
values[4]	922	1			T3	14		T12	1		T128	1
values[5]	808	1			T3	24		T31	17		T37	2
values[6]	617	1			T3	26		T36	27		T129	18
values[7]	671	1			T9	1		T12	1		T24	1
values[8]	925	1			T5	22		T7	4		T37	2
values[9]	3202	1			T4	2		T5	23		T6	9
minimum	16558	1			T1	12		T2	20		T7	104

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	828	1			T7	2		T129	28		T131	13
values[1]	586	1			T29	19		T16	1		T138	18
values[2]	671	1			T3	14		T7	5		T29	7
values[3]	974	1			T3	24		T12	1		T128	1
values[4]	664	1			T3	26		T31	17		T37	2
values[5]	624	1			T9	1		T36	27		T128	1
values[6]	2930	1			T4	2		T6	9		T7	4
values[7]	913	1			T5	22		T37	2		T136	14
values[8]	919	1			T5	23		T9	1		T13	3
values[9]	148	1			T130	5		T39	2		T42	4
minimum	16723	1			T1	12		T2	20		T7	104

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

4368

1

T3

29

T5

23

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T7	2		T129	14		T247	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T131	13		T38	2		T247	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T29	17		T40	7		T285	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T16	1		T138	18		T187	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T29	6		T137	1		T289	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	6		T7	3		T132	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T12	1		T128	1		T138	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T3	12		T42	2		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	14		T266	5		T270	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T31	10		T37	2		T220	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T36	13		T128	1		T129	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	1		T131	15		T133	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1561	1			T4	2		T6	1		T7	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T24	1		T28	17		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T37	1		T136	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	11		T139	13		T275	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	3		T169	1		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T5	14		T9	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T130	1		T42	3		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T39	2		T321	16		T205	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16475	1			T1	12		T2	20		T7	99
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T143	19		T146	9		T334	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T129	14		T247	11		T214	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T247	11		T248	12		T142	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T29	2		T40	7		T285	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T187	6		T148	11		T258	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T29	1		T137	12		T134	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T3	8		T7	2		T132	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T139	11		T265	11		T256	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	12		T42	1		T135	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T3	12		T17	1		T271	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T31	7		T220	17		T189	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T36	14		T129	8		T137	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T133	18		T263	6		T255	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T6	8		T7	2		T71	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T28	20		T16	1		T137	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T37	1		T136	13		T247	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	11		T139	12		T275	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T169	12		T161	11		T256	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	9		T136	10		T189	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T130	4		T42	1		T135	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T321	13		T205	12		T20	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	5		T31	1		T37	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T143	13		T146	4		T334	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T130	1		T256	13		T211	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T39	2		T189	5		T266	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T220	12		T333	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T214	1		T150	3		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T38	2		T247	14		T248	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	2		T29	17		T129	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T16	1		T131	13		T187	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T29	6		T289	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	3		T138	18		T132	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T12	1		T128	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	6		T135	1		T229	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T265	12		T142	15		T144	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T3	12		T31	10		T37	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	14		T36	13		T129	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T131	15		T133	15		T215	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	1		T128	1		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	1		T24	1		T28	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T7	2		T37	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T5	11		T139	13		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1617	1			T4	2		T6	1		T10	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T5	14		T9	1		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16427	1			T1	12		T2	20		T7	99
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T130	4		T256	5		T335	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T189	1		T296	14		T268	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T220	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T214	15		T150	11		T215	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T247	11		T248	12		T142	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T29	2		T129	14		T40	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T187	6		T212	6		T258	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T29	1		T160	14		T284	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T7	2		T132	6		T140	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T137	12		T139	11		T134	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	8		T135	9		T229	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T265	11		T271	22		T172	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	12		T31	7		T220	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T3	12		T36	14		T129	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T133	18		T215	11		T255	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T160	2		T272	1		T264	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T28	20		T16	1		T137	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	2		T37	1		T136	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T5	11		T139	12		T140	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T6	8		T71	11		T73	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	9		T136	10		T197	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	2		T129	15		T247	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T131	1		T38	2		T247	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T29	3		T40	10		T285	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T16	1		T138	1		T187	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T29	2		T137	13		T289	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	9		T7	3		T132	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T12	1		T128	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T3	13		T42	2		T135	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T3	13		T266	1		T270	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T31	11		T37	1		T220	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T36	17		T128	1		T129	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	1		T131	1		T133	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T4	2		T6	9		T7	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T24	1		T28	21		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T37	2		T136	14		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T5	12		T139	13		T275	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	2		T169	13		T161	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T5	10		T9	1		T136	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T130	5		T42	2		T135	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T39	2		T321	14		T205	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16594	1			T1	12		T2	20		T7	104
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T143	14		T146	8		T334	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T129	13		T247	14		T150	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T131	12		T247	13		T248	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T29	16		T40	4		T285	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T138	17		T187	2		T282	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T29	5		T134	9		T284	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T3	5		T7	2		T132	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T138	5		T132	7		T139	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T3	11		T42	1		T229	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	13		T266	4		T270	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T31	6		T37	1		T220	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T36	10		T129	9		T150	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T131	14		T133	14		T263	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T10	14		T25	18		T223	32
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T28	16		T16	1		T253	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T247	10		T252	6		T257	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	10		T139	12		T275	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	1		T256	12		T262	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T5	13		T131	19		T189	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T42	2		T332	11		T311	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T321	15		T205	14		T20	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T220	11		T293	1		T329	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T143	18		T146	5		T334	20

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T130	5		T256	6		T211	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T39	2		T189	4		T266	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T220	10		T333	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T214	16		T150	12		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T38	2		T247	12		T248	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	2		T29	3		T129	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T16	1		T131	1		T187	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T29	2		T289	1		T160	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T7	3		T138	1		T132	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T12	1		T128	1		T137	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T3	9		T135	10		T229	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T265	12		T142	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	13		T31	11		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	13		T36	17		T129	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T131	1		T133	19		T215	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	1		T128	1		T160	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	1		T24	1		T28	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	4		T37	2		T136	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T5	12		T139	13		T140	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1395	1			T4	2		T6	9		T10	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T5	10		T9	1		T136	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16558	1			T1	12		T2	20		T7	104
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T256	12		T335	2		T336	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T189	2		T266	9		T290	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T220	11		T333	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T150	2		T215	9		T306	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T247	13		T248	13		T142	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T29	16		T129	13		T40	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T131	12		T187	2		T212	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T29	5		T284	3		T283	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	2		T138	17		T132	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T138	5		T132	7		T139	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	5		T229	1		T254	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T265	11		T142	14		T144	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	11		T31	6		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	13		T36	10		T129	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T131	14		T133	14		T215	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T264	8		T258	8		T144	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T28	16		T16	1		T253	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T252	6		T261	2		T154	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	10		T139	12		T275	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T10	14		T13	1		T25	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T5	13		T131	19		T197	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

auto[0]

4368

1

T3

29

T5

23

T7

2