Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25980

1

T1

12

T2

20

T3

64

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21703

1

T1

12

T2

20

T3

24

auto[ADC_CTRL_FILTER_COND_OUT]

4277

1

T3

40

T5

23

T7

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19597

1

T1

12

T2

20

T5

23

auto[1]

6383

1

T3

64

T4

2

T5

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21875

1

T1

12

T2

20

T3

32

auto[1]

4105

1

T3

32

T5

20

T6

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	330	1			T28	37		T197	22		T255	13
values[0]	68	1			T337	13		T245	18		T307	12
values[1]	716	1			T3	14		T31	17		T37	2
values[2]	2951	1			T4	2		T6	9		T10	15
values[3]	758	1			T5	22		T7	4		T24	1
values[4]	838	1			T29	19		T16	4		T169	13
values[5]	703	1			T5	23		T136	14		T16	1
values[6]	682	1			T7	2		T9	1		T13	3
values[7]	745	1			T12	1		T136	11		T137	17
values[8]	760	1			T3	24		T9	1		T137	4
values[9]	871	1			T3	26		T7	5		T12	1
minimum	16558	1			T1	12		T2	20		T7	104

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	628	1			T3	14		T129	28		T130	10
values[1]	2938	1			T4	2		T5	22		T6	9
values[2]	846	1			T7	4		T24	1		T128	1
values[3]	736	1			T29	19		T136	14		T16	5
values[4]	708	1			T5	23		T9	1		T131	15
values[5]	738	1			T7	2		T12	1		T13	3
values[6]	700	1			T136	11		T137	8		T38	2
values[7]	780	1			T3	50		T9	1		T138	18
values[8]	967	1			T7	5		T12	1		T28	37
values[9]	64	1			T29	7		T32	2		T270	13
minimum	16875	1			T1	12		T2	20		T7	104

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

4368

1

T3

29

T5

23

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T129	14		T189	1		T133	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	6		T130	1		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1505	1			T4	2		T5	11		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T36	13		T37	1		T131	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T24	1		T130	1		T132	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T7	2		T128	1		T165	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T29	17		T136	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T16	1		T169	1		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	1		T131	15		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T5	14		T214	1		T150	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T12	1		T131	20		T220	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	2		T13	3		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T132	8		T189	5		T247	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T136	1		T137	2		T38	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	12		T42	2		T150	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T3	14		T9	1		T138	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T128	1		T197	12		T142	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	400	1			T7	3		T12	1		T28	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T32	1		T270	13		T329	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T29	6		T293	2		T221	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16496	1			T1	12		T2	20		T7	99
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T37	2		T338	1		T282	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T129	14		T189	1		T133	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	8		T130	9		T248	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	941	1			T5	11		T6	8		T71	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T36	14		T37	1		T220	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T130	4		T132	6		T187	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T7	2		T256	16		T257	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T29	2		T136	13		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T169	12		T140	14		T255	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T140	9		T204	9		T339	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T5	9		T214	10		T150	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T220	9		T135	9		T161	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T137	12		T189	1		T247	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T189	1		T247	11		T229	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T136	10		T137	6		T253	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	12		T42	1		T150	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	12		T42	1		T265	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T197	10		T292	15		T282	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T7	2		T28	20		T129	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T32	1		T329	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T29	1		T293	1		T221	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	5		T31	8		T37	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T338	15		T282	10		T173	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T197	12		T292	1		T181	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T28	17		T255	1		T171	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T337	1		T245	9		T307	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T31	10		T129	14		T39	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	6		T37	2		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1508	1			T4	2		T6	1		T10	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T37	1		T220	12		T134	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	11		T24	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T7	2		T36	13		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T29	17		T16	3		T138	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T169	1		T39	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T136	1		T131	15		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	14		T16	1		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T9	1		T131	20		T220	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	2		T13	3		T150	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	1		T132	8		T247	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T136	1		T137	2		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T3	12		T42	2		T189	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	1		T137	1		T138	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T128	1		T142	15		T32	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	389	1			T3	14		T7	3		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16427	1			T1	12		T2	20		T7	99
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T197	10		T292	15		T326	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T28	20		T255	12		T171	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T337	12		T245	9		T307	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T31	7		T129	14		T189	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	8		T130	9		T248	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	945	1			T6	8		T71	11		T73	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T37	1		T220	17		T134	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	11		T130	4		T135	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	2		T36	14		T256	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T29	2		T16	1		T132	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T169	12		T140	14		T255	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T136	13		T140	9		T293	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	9		T214	10		T252	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T220	9		T135	9		T161	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T150	11		T215	11		T272	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T247	11		T212	6		T279	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T136	10		T137	15		T189	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	12		T42	1		T189	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T137	3		T265	11		T214	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T32	1		T282	8		T145	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T3	12		T7	2		T29	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	5		T31	1		T37	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T129	15		T189	2		T133	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	9		T130	10		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T4	2		T5	12		T6	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T36	17		T37	2		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T24	1		T130	5		T132	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T7	4		T128	1		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T29	3		T136	14		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T16	1		T169	13		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T9	1		T131	1		T140	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T5	10		T214	11		T150	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	1		T131	1		T220	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	2		T13	2		T137	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T132	1		T189	4		T247	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T136	11		T137	8		T38	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	13		T42	2		T150	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	13		T9	1		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T128	1		T197	11		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T7	3		T12	1		T28	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T32	2		T270	1		T329	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T29	2		T293	2		T221	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16633	1			T1	12		T2	20		T7	104
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T37	1		T338	16		T282	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T129	13		T133	14		T340	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	5		T248	13		T275	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1177	1			T5	10		T10	14		T25	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T36	10		T131	12		T220	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T132	2		T187	2		T264	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T165	10		T256	17		T257	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T29	16		T16	1		T138	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T284	3		T142	15		T180	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T131	14		T266	4		T339	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	13		T150	2		T252	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T131	19		T220	11		T264	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	1		T247	10		T272	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T132	7		T189	2		T247	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T253	8		T256	12		T257	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	11		T42	1		T150	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T3	13		T138	17		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T197	11		T142	14		T181	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T7	2		T28	16		T129	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T270	12		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T29	5		T293	1		T341	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T31	6		T247	14		T296	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T37	1		T282	13		T173	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T197	11		T292	16		T181	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T28	21		T255	13		T171	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T337	13		T245	10		T307	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T31	11		T129	15		T39	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	9		T37	1		T130	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T4	2		T6	9		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T37	2		T220	18		T134	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	12		T24	1		T130	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	4		T36	17		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T29	3		T16	3		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T169	13		T39	1		T140	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T136	14		T131	1		T140	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	10		T16	1		T214	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	1		T131	1		T220	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	2		T13	2		T150	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	1		T132	1		T247	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T136	11		T137	17		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	13		T42	2		T189	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T9	1		T137	4		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T128	1		T142	1		T32	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T3	13		T7	3		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16558	1			T1	12		T2	20		T7	104
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T197	11		T181	13		T270	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T28	16		T283	2		T271	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T245	8		T342	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T31	6		T129	13		T133	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	5		T37	1		T248	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1171	1			T10	14		T25	18		T223	32
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T220	11		T134	9		T143	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	10		T213	15		T143	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T36	10		T131	12		T165	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T29	16		T16	1		T138	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T284	3		T256	11		T257	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T131	14		T266	4		T339	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	13		T252	6		T285	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T131	19		T220	11		T263	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	1		T150	2		T215	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T132	7		T247	13		T212	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T253	8		T247	10		T257	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	11		T42	1		T189	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T138	17		T265	11		T213	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T142	14		T282	10		T172	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T3	13		T7	2		T29	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21612

1

T1

12

T2

20

T3

35

auto[1]

auto[0]

4368

1

T3

29

T5

23

T7

2