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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.70 99.07 96.67 100.00 100.00 98.83 98.33 91.02


Total test records in report: 918
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T795 /workspace/coverage/default/37.adc_ctrl_lowpower_counter.201828252 May 19 01:36:20 PM PDT 24 May 19 01:37:28 PM PDT 24 29214531205 ps
T269 /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3805717608 May 19 01:33:37 PM PDT 24 May 19 01:46:03 PM PDT 24 522984376389 ps
T796 /workspace/coverage/default/6.adc_ctrl_stress_all.2618407913 May 19 01:33:54 PM PDT 24 May 19 01:35:03 PM PDT 24 28040977873 ps
T797 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3743910077 May 19 01:47:56 PM PDT 24 May 19 01:47:57 PM PDT 24 465233574 ps
T23 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3816813957 May 19 01:48:12 PM PDT 24 May 19 01:48:29 PM PDT 24 4201329513 ps
T48 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2459687064 May 19 01:48:11 PM PDT 24 May 19 01:48:19 PM PDT 24 4313560248 ps
T798 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2769188200 May 19 01:47:53 PM PDT 24 May 19 01:47:54 PM PDT 24 490028815 ps
T121 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2713529164 May 19 01:48:02 PM PDT 24 May 19 01:48:03 PM PDT 24 623361682 ps
T77 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2556805296 May 19 01:47:54 PM PDT 24 May 19 01:47:57 PM PDT 24 425338256 ps
T799 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.187228584 May 19 01:48:01 PM PDT 24 May 19 01:48:03 PM PDT 24 493710117 ps
T53 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3860039112 May 19 01:48:03 PM PDT 24 May 19 01:48:05 PM PDT 24 544370591 ps
T49 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3885386056 May 19 01:47:47 PM PDT 24 May 19 01:47:51 PM PDT 24 2912298829 ps
T122 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3233459137 May 19 01:48:11 PM PDT 24 May 19 01:48:13 PM PDT 24 428622090 ps
T800 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2983300990 May 19 01:48:23 PM PDT 24 May 19 01:48:26 PM PDT 24 499977222 ps
T50 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3442821450 May 19 01:47:44 PM PDT 24 May 19 01:47:55 PM PDT 24 4092420511 ps
T108 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.4020488951 May 19 01:47:44 PM PDT 24 May 19 01:47:47 PM PDT 24 680533018 ps
T801 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1854873985 May 19 01:48:11 PM PDT 24 May 19 01:48:13 PM PDT 24 405732968 ps
T802 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.376909038 May 19 01:48:14 PM PDT 24 May 19 01:48:17 PM PDT 24 513001928 ps
T123 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3686354702 May 19 01:48:01 PM PDT 24 May 19 01:48:09 PM PDT 24 2367605292 ps
T51 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3557418494 May 19 01:48:01 PM PDT 24 May 19 01:48:06 PM PDT 24 9779067598 ps
T803 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.277917552 May 19 01:48:08 PM PDT 24 May 19 01:48:10 PM PDT 24 532011878 ps
T59 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3813501292 May 19 01:47:55 PM PDT 24 May 19 01:47:57 PM PDT 24 640650997 ps
T124 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1511125509 May 19 01:47:54 PM PDT 24 May 19 01:48:04 PM PDT 24 2817656174 ps
T109 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.424224431 May 19 01:48:02 PM PDT 24 May 19 01:48:03 PM PDT 24 515427701 ps
T804 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1228600300 May 19 01:48:14 PM PDT 24 May 19 01:48:16 PM PDT 24 354191175 ps
T805 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1553665357 May 19 01:48:15 PM PDT 24 May 19 01:48:17 PM PDT 24 307030713 ps
T806 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3543137571 May 19 01:47:53 PM PDT 24 May 19 01:47:55 PM PDT 24 334742922 ps
T807 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1461224772 May 19 01:48:10 PM PDT 24 May 19 01:48:11 PM PDT 24 479833494 ps
T808 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1513566341 May 19 01:47:55 PM PDT 24 May 19 01:47:57 PM PDT 24 466826299 ps
T809 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1038168027 May 19 01:48:09 PM PDT 24 May 19 01:48:11 PM PDT 24 430898815 ps
T810 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2811221988 May 19 01:48:15 PM PDT 24 May 19 01:48:16 PM PDT 24 325212172 ps
T127 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3031094614 May 19 01:47:40 PM PDT 24 May 19 01:47:41 PM PDT 24 803797263 ps
T125 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.103218000 May 19 01:47:53 PM PDT 24 May 19 01:47:58 PM PDT 24 4999488938 ps
T126 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2045903276 May 19 01:47:41 PM PDT 24 May 19 01:47:43 PM PDT 24 338897851 ps
T811 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2143064768 May 19 01:48:04 PM PDT 24 May 19 01:48:07 PM PDT 24 2677583701 ps
T812 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.322592094 May 19 01:47:55 PM PDT 24 May 19 01:47:57 PM PDT 24 365854771 ps
T813 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3262641215 May 19 01:48:28 PM PDT 24 May 19 01:48:30 PM PDT 24 465099215 ps
T110 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3531977994 May 19 01:47:50 PM PDT 24 May 19 01:47:52 PM PDT 24 442090161 ps
T67 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1251248734 May 19 01:47:49 PM PDT 24 May 19 01:47:52 PM PDT 24 461877892 ps
T814 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2533562258 May 19 01:48:10 PM PDT 24 May 19 01:48:12 PM PDT 24 316274537 ps
T52 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.99215371 May 19 01:47:51 PM PDT 24 May 19 01:48:05 PM PDT 24 4672580277 ps
T815 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2170487926 May 19 01:47:41 PM PDT 24 May 19 01:47:42 PM PDT 24 487235678 ps
T60 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1235353057 May 19 01:47:58 PM PDT 24 May 19 01:48:01 PM PDT 24 1139295467 ps
T78 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3541423626 May 19 01:48:10 PM PDT 24 May 19 01:48:12 PM PDT 24 519168225 ps
T816 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3128397451 May 19 01:48:19 PM PDT 24 May 19 01:48:21 PM PDT 24 429992675 ps
T79 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3877511688 May 19 01:48:02 PM PDT 24 May 19 01:48:04 PM PDT 24 418169582 ps
T111 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1779533708 May 19 01:47:49 PM PDT 24 May 19 01:50:28 PM PDT 24 49486710758 ps
T61 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1972394222 May 19 01:47:51 PM PDT 24 May 19 01:47:53 PM PDT 24 562815103 ps
T817 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1116246743 May 19 01:47:46 PM PDT 24 May 19 01:47:54 PM PDT 24 2660106614 ps
T62 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1032171971 May 19 01:47:58 PM PDT 24 May 19 01:48:01 PM PDT 24 519408054 ps
T818 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.974444843 May 19 01:48:10 PM PDT 24 May 19 01:48:15 PM PDT 24 4497206672 ps
T65 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1758836875 May 19 01:47:48 PM PDT 24 May 19 01:47:51 PM PDT 24 1590337150 ps
T819 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2123614487 May 19 01:48:13 PM PDT 24 May 19 01:48:15 PM PDT 24 1206284578 ps
T820 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.18381583 May 19 01:48:23 PM PDT 24 May 19 01:48:25 PM PDT 24 385079493 ps
T821 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.585580049 May 19 01:48:15 PM PDT 24 May 19 01:48:17 PM PDT 24 489829951 ps
T822 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3243965047 May 19 01:48:05 PM PDT 24 May 19 01:48:14 PM PDT 24 4857373582 ps
T823 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1062908768 May 19 01:48:14 PM PDT 24 May 19 01:48:15 PM PDT 24 341906017 ps
T54 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3184271179 May 19 01:47:37 PM PDT 24 May 19 01:47:59 PM PDT 24 8077247382 ps
T112 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.394558232 May 19 01:47:50 PM PDT 24 May 19 01:47:53 PM PDT 24 1010826507 ps
T824 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1956654894 May 19 01:47:50 PM PDT 24 May 19 01:47:54 PM PDT 24 2372762837 ps
T825 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2762706654 May 19 01:48:10 PM PDT 24 May 19 01:48:13 PM PDT 24 441311209 ps
T826 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.650888898 May 19 01:47:54 PM PDT 24 May 19 01:47:57 PM PDT 24 2854067161 ps
T113 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1965253549 May 19 01:47:42 PM PDT 24 May 19 01:47:45 PM PDT 24 1200752114 ps
T64 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1171052946 May 19 01:48:09 PM PDT 24 May 19 01:48:22 PM PDT 24 8736933057 ps
T66 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1984901580 May 19 01:47:48 PM PDT 24 May 19 01:47:52 PM PDT 24 2955326392 ps
T827 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3481787338 May 19 01:47:49 PM PDT 24 May 19 01:47:50 PM PDT 24 560174721 ps
T828 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.590508703 May 19 01:47:42 PM PDT 24 May 19 01:47:47 PM PDT 24 2812377727 ps
T829 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3140579874 May 19 01:48:10 PM PDT 24 May 19 01:48:13 PM PDT 24 356446292 ps
T830 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2216937855 May 19 01:47:56 PM PDT 24 May 19 01:47:57 PM PDT 24 542401531 ps
T831 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1908445787 May 19 01:47:42 PM PDT 24 May 19 01:48:20 PM PDT 24 26352202562 ps
T832 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.992999809 May 19 01:48:10 PM PDT 24 May 19 01:48:13 PM PDT 24 513585239 ps
T833 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3641288586 May 19 01:47:53 PM PDT 24 May 19 01:47:57 PM PDT 24 480386718 ps
T834 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.447533441 May 19 01:47:55 PM PDT 24 May 19 01:48:00 PM PDT 24 613187869 ps
T835 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2553762881 May 19 01:47:55 PM PDT 24 May 19 01:47:58 PM PDT 24 2931211266 ps
T836 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3632381167 May 19 01:48:07 PM PDT 24 May 19 01:48:12 PM PDT 24 4339505044 ps
T837 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1813871734 May 19 01:47:51 PM PDT 24 May 19 01:47:53 PM PDT 24 473032002 ps
T838 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1136571985 May 19 01:47:43 PM PDT 24 May 19 01:49:26 PM PDT 24 26776493090 ps
T839 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1993207163 May 19 01:48:11 PM PDT 24 May 19 01:48:15 PM PDT 24 2488193270 ps
T840 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.307254017 May 19 01:47:54 PM PDT 24 May 19 01:47:57 PM PDT 24 405473448 ps
T841 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3669445184 May 19 01:48:06 PM PDT 24 May 19 01:48:18 PM PDT 24 4183587862 ps
T114 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3262265377 May 19 01:47:38 PM PDT 24 May 19 01:47:47 PM PDT 24 19414705027 ps
T842 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2441084206 May 19 01:48:02 PM PDT 24 May 19 01:48:06 PM PDT 24 467894719 ps
T843 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3715849593 May 19 01:48:09 PM PDT 24 May 19 01:48:11 PM PDT 24 487366587 ps
T844 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1626133982 May 19 01:48:05 PM PDT 24 May 19 01:48:07 PM PDT 24 515731672 ps
T845 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.4110377620 May 19 01:48:03 PM PDT 24 May 19 01:48:21 PM PDT 24 8757208227 ps
T846 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1176849385 May 19 01:47:38 PM PDT 24 May 19 01:47:40 PM PDT 24 499619226 ps
T847 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2875413230 May 19 01:48:14 PM PDT 24 May 19 01:48:17 PM PDT 24 309789673 ps
T848 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4194511596 May 19 01:47:56 PM PDT 24 May 19 01:47:58 PM PDT 24 443531742 ps
T849 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.173509805 May 19 01:48:13 PM PDT 24 May 19 01:48:16 PM PDT 24 503416650 ps
T850 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1058426138 May 19 01:47:47 PM PDT 24 May 19 01:47:55 PM PDT 24 7890315051 ps
T851 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2913392404 May 19 01:48:08 PM PDT 24 May 19 01:48:09 PM PDT 24 343495424 ps
T852 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2025726045 May 19 01:47:53 PM PDT 24 May 19 01:47:58 PM PDT 24 5186562397 ps
T853 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1865725916 May 19 01:48:01 PM PDT 24 May 19 01:48:04 PM PDT 24 474207247 ps
T854 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.300688739 May 19 01:48:23 PM PDT 24 May 19 01:48:25 PM PDT 24 360182846 ps
T855 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3901749586 May 19 01:47:54 PM PDT 24 May 19 01:47:56 PM PDT 24 686355187 ps
T856 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1468053658 May 19 01:48:09 PM PDT 24 May 19 01:48:13 PM PDT 24 908305504 ps
T115 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.62549731 May 19 01:47:46 PM PDT 24 May 19 01:48:06 PM PDT 24 24208133304 ps
T857 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.4248333666 May 19 01:48:07 PM PDT 24 May 19 01:48:08 PM PDT 24 410990602 ps
T116 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.4208277349 May 19 01:48:00 PM PDT 24 May 19 01:48:02 PM PDT 24 550297307 ps
T858 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.4190103564 May 19 01:48:22 PM PDT 24 May 19 01:48:24 PM PDT 24 436385388 ps
T859 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3409577246 May 19 01:48:05 PM PDT 24 May 19 01:48:08 PM PDT 24 405638690 ps
T860 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2307605673 May 19 01:47:42 PM PDT 24 May 19 01:47:46 PM PDT 24 600826298 ps
T364 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.734162280 May 19 01:48:02 PM PDT 24 May 19 01:48:23 PM PDT 24 7739634552 ps
T861 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1906608548 May 19 01:47:53 PM PDT 24 May 19 01:48:01 PM PDT 24 4257535139 ps
T862 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3886877198 May 19 01:48:28 PM PDT 24 May 19 01:48:31 PM PDT 24 380598191 ps
T863 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1311815307 May 19 01:47:38 PM PDT 24 May 19 01:47:41 PM PDT 24 309565340 ps
T864 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.15384884 May 19 01:48:06 PM PDT 24 May 19 01:48:08 PM PDT 24 609111121 ps
T865 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2676835305 May 19 01:48:00 PM PDT 24 May 19 01:48:03 PM PDT 24 473177082 ps
T866 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.488270196 May 19 01:47:49 PM PDT 24 May 19 01:47:53 PM PDT 24 1095747777 ps
T867 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2170471923 May 19 01:47:57 PM PDT 24 May 19 01:47:59 PM PDT 24 425628941 ps
T868 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.4082022584 May 19 01:47:53 PM PDT 24 May 19 01:47:55 PM PDT 24 414692287 ps
T869 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2277903103 May 19 01:47:43 PM PDT 24 May 19 01:47:46 PM PDT 24 714261514 ps
T870 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.975087069 May 19 01:47:39 PM PDT 24 May 19 01:47:41 PM PDT 24 602233657 ps
T117 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3978729398 May 19 01:47:49 PM PDT 24 May 19 01:47:51 PM PDT 24 577994220 ps
T871 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3365545033 May 19 01:47:55 PM PDT 24 May 19 01:47:57 PM PDT 24 329791300 ps
T872 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3735503288 May 19 01:47:43 PM PDT 24 May 19 01:47:45 PM PDT 24 419536738 ps
T118 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.274298942 May 19 01:47:42 PM PDT 24 May 19 01:47:46 PM PDT 24 1045906518 ps
T119 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2510152262 May 19 01:47:51 PM PDT 24 May 19 01:47:53 PM PDT 24 404691964 ps
T873 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3456566786 May 19 01:47:54 PM PDT 24 May 19 01:47:58 PM PDT 24 307768670 ps
T874 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1427988107 May 19 01:47:54 PM PDT 24 May 19 01:47:57 PM PDT 24 538760565 ps
T875 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.269551280 May 19 01:48:11 PM PDT 24 May 19 01:48:15 PM PDT 24 461266471 ps
T876 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1959438543 May 19 01:48:17 PM PDT 24 May 19 01:48:20 PM PDT 24 442702255 ps
T877 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.780734579 May 19 01:47:48 PM PDT 24 May 19 01:47:50 PM PDT 24 389451337 ps
T878 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.4156755338 May 19 01:47:55 PM PDT 24 May 19 01:47:57 PM PDT 24 541861935 ps
T68 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1983976768 May 19 01:47:40 PM PDT 24 May 19 01:47:44 PM PDT 24 4368717713 ps
T879 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3689033731 May 19 01:48:09 PM PDT 24 May 19 01:48:11 PM PDT 24 337058123 ps
T880 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.129196214 May 19 01:47:56 PM PDT 24 May 19 01:47:59 PM PDT 24 420701473 ps
T881 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4220954721 May 19 01:47:38 PM PDT 24 May 19 01:47:40 PM PDT 24 465895460 ps
T882 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.831151775 May 19 01:48:10 PM PDT 24 May 19 01:48:13 PM PDT 24 670033802 ps
T883 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2599643954 May 19 01:47:41 PM PDT 24 May 19 01:47:53 PM PDT 24 4740068403 ps
T120 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.232296727 May 19 01:47:46 PM PDT 24 May 19 01:47:48 PM PDT 24 694106923 ps
T884 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1002724946 May 19 01:47:45 PM PDT 24 May 19 01:47:52 PM PDT 24 4311372806 ps
T885 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4132247769 May 19 01:47:47 PM PDT 24 May 19 01:47:50 PM PDT 24 759603929 ps
T886 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1355006443 May 19 01:47:59 PM PDT 24 May 19 01:48:11 PM PDT 24 4635559630 ps
T887 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1495223516 May 19 01:47:43 PM PDT 24 May 19 01:47:46 PM PDT 24 447536852 ps
T888 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.943573500 May 19 01:47:42 PM PDT 24 May 19 01:47:45 PM PDT 24 448733896 ps
T889 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.339228984 May 19 01:48:13 PM PDT 24 May 19 01:48:15 PM PDT 24 444637789 ps
T890 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1915763674 May 19 01:47:43 PM PDT 24 May 19 01:47:45 PM PDT 24 486612583 ps
T891 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2269554268 May 19 01:48:18 PM PDT 24 May 19 01:48:20 PM PDT 24 355872285 ps
T892 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1339586297 May 19 01:48:12 PM PDT 24 May 19 01:48:13 PM PDT 24 541237914 ps
T893 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3258648057 May 19 01:48:03 PM PDT 24 May 19 01:48:05 PM PDT 24 493819583 ps
T894 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3975081919 May 19 01:48:04 PM PDT 24 May 19 01:48:06 PM PDT 24 484386174 ps
T895 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2454273097 May 19 01:48:09 PM PDT 24 May 19 01:48:11 PM PDT 24 601819398 ps
T896 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1149752483 May 19 01:48:14 PM PDT 24 May 19 01:48:17 PM PDT 24 400735375 ps
T897 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1976492541 May 19 01:47:48 PM PDT 24 May 19 01:47:52 PM PDT 24 1325445329 ps
T898 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.153703953 May 19 01:47:39 PM PDT 24 May 19 01:47:41 PM PDT 24 308368911 ps
T899 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1759230087 May 19 01:48:10 PM PDT 24 May 19 01:48:28 PM PDT 24 4984164200 ps
T900 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2788085895 May 19 01:47:50 PM PDT 24 May 19 01:47:53 PM PDT 24 5305494257 ps
T901 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3414310283 May 19 01:48:16 PM PDT 24 May 19 01:48:18 PM PDT 24 425285482 ps
T902 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2115012958 May 19 01:48:14 PM PDT 24 May 19 01:48:17 PM PDT 24 316415851 ps
T365 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3310104328 May 19 01:47:53 PM PDT 24 May 19 01:47:59 PM PDT 24 4628282016 ps
T903 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1946355159 May 19 01:47:53 PM PDT 24 May 19 01:47:55 PM PDT 24 600686903 ps
T904 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.4058551925 May 19 01:47:41 PM PDT 24 May 19 01:47:43 PM PDT 24 427315918 ps
T905 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2976752343 May 19 01:47:55 PM PDT 24 May 19 01:47:57 PM PDT 24 599616659 ps
T906 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.890210929 May 19 01:47:43 PM PDT 24 May 19 01:47:45 PM PDT 24 397997103 ps
T907 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3704189484 May 19 01:47:54 PM PDT 24 May 19 01:48:02 PM PDT 24 4369870018 ps
T908 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2348532154 May 19 01:47:58 PM PDT 24 May 19 01:48:01 PM PDT 24 579507848 ps
T909 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1163452434 May 19 01:48:10 PM PDT 24 May 19 01:48:12 PM PDT 24 419069985 ps
T910 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1548135197 May 19 01:47:56 PM PDT 24 May 19 01:48:04 PM PDT 24 4087874917 ps
T911 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2810322453 May 19 01:48:14 PM PDT 24 May 19 01:48:17 PM PDT 24 455086388 ps
T912 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3969325996 May 19 01:47:40 PM PDT 24 May 19 01:47:47 PM PDT 24 2412932668 ps
T913 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2715722111 May 19 01:47:58 PM PDT 24 May 19 01:48:01 PM PDT 24 567721502 ps
T363 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2162949539 May 19 01:47:52 PM PDT 24 May 19 01:48:04 PM PDT 24 4251678730 ps
T914 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3905171319 May 19 01:47:40 PM PDT 24 May 19 01:47:41 PM PDT 24 521073135 ps
T915 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1673772448 May 19 01:48:22 PM PDT 24 May 19 01:48:24 PM PDT 24 580497915 ps
T916 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.4153246280 May 19 01:47:41 PM PDT 24 May 19 01:47:45 PM PDT 24 448550618 ps
T917 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.584674116 May 19 01:47:49 PM PDT 24 May 19 01:48:02 PM PDT 24 4513605445 ps
T918 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2283110714 May 19 01:47:56 PM PDT 24 May 19 01:48:01 PM PDT 24 2398934387 ps

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1425911343
Short name T7
Test name
Test status
Simulation time 114165507385 ps
CPU time 217.21 seconds
Started May 19 01:35:15 PM PDT 24
Finished May 19 01:38:53 PM PDT 24
Peak memory 211400 kb
Host smart-9527de31-d7ab-45fd-9611-1170ee0c11ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425911343 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1425911343
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1006921177
Short name T3
Test name
Test status
Simulation time 511598752997 ps
CPU time 669.58 seconds
Started May 19 01:33:51 PM PDT 24
Finished May 19 01:45:02 PM PDT 24
Peak memory 201832 kb
Host smart-081dab55-ebb8-401b-910a-5e48cf9ffd93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006921177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1006921177
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2129736625
Short name T36
Test name
Test status
Simulation time 198098868129 ps
CPU time 156.27 seconds
Started May 19 01:34:03 PM PDT 24
Finished May 19 01:36:42 PM PDT 24
Peak memory 210524 kb
Host smart-8cfdce44-41df-4bfa-9cbf-9b5ce02b785e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129736625 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2129736625
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1933629531
Short name T16
Test name
Test status
Simulation time 158082078614 ps
CPU time 35.15 seconds
Started May 19 01:34:02 PM PDT 24
Finished May 19 01:34:40 PM PDT 24
Peak memory 210100 kb
Host smart-a0610fe0-b14b-4dd5-a422-11f24856557c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933629531 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1933629531
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3787626969
Short name T256
Test name
Test status
Simulation time 492016926583 ps
CPU time 1120.05 seconds
Started May 19 01:38:44 PM PDT 24
Finished May 19 01:57:25 PM PDT 24
Peak memory 201884 kb
Host smart-1f5f2150-2711-40a8-921b-245debdd49fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787626969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3787626969
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1103834141
Short name T42
Test name
Test status
Simulation time 267565057433 ps
CPU time 381.22 seconds
Started May 19 01:33:55 PM PDT 24
Finished May 19 01:40:17 PM PDT 24
Peak memory 210452 kb
Host smart-44f47088-bf17-4714-a2e2-e0aacdeda873
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103834141 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1103834141
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.242718624
Short name T31
Test name
Test status
Simulation time 133388719360 ps
CPU time 180.2 seconds
Started May 19 01:37:49 PM PDT 24
Finished May 19 01:40:50 PM PDT 24
Peak memory 210488 kb
Host smart-b2cf4e83-3de1-4e67-8c44-0c006e4d07be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242718624 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.242718624
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.875904944
Short name T272
Test name
Test status
Simulation time 521812773620 ps
CPU time 400.01 seconds
Started May 19 01:33:33 PM PDT 24
Finished May 19 01:40:15 PM PDT 24
Peak memory 201772 kb
Host smart-eef7343f-ca60-40d7-b3b1-23c4e4d1e2a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875904944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.875904944
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.4092406244
Short name T131
Test name
Test status
Simulation time 554454862401 ps
CPU time 1200.61 seconds
Started May 19 01:34:32 PM PDT 24
Finished May 19 01:54:33 PM PDT 24
Peak memory 201892 kb
Host smart-97e62d7c-7a80-4abd-ad9d-f930083e4528
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092406244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.4092406244
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3557418494
Short name T51
Test name
Test status
Simulation time 9779067598 ps
CPU time 4.51 seconds
Started May 19 01:48:01 PM PDT 24
Finished May 19 01:48:06 PM PDT 24
Peak memory 201948 kb
Host smart-aac55f16-fe81-4016-877f-af0423425e8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557418494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3557418494
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1568711843
Short name T247
Test name
Test status
Simulation time 510915571241 ps
CPU time 1230.51 seconds
Started May 19 01:34:56 PM PDT 24
Finished May 19 01:55:28 PM PDT 24
Peak memory 201792 kb
Host smart-2e7c5b79-b72d-42c5-a8a1-4a1fb4107f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568711843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1568711843
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1033204531
Short name T258
Test name
Test status
Simulation time 535409366486 ps
CPU time 1330.76 seconds
Started May 19 01:36:55 PM PDT 24
Finished May 19 01:59:07 PM PDT 24
Peak memory 201796 kb
Host smart-ca6c4e81-6929-499e-ad1a-4a87d6dce959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033204531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1033204531
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3946830691
Short name T153
Test name
Test status
Simulation time 522300133270 ps
CPU time 195.87 seconds
Started May 19 01:37:08 PM PDT 24
Finished May 19 01:40:24 PM PDT 24
Peak memory 202076 kb
Host smart-7d9bee54-a31d-4b0c-8f6c-8216c13f8eae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946830691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3946830691
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1857724267
Short name T5
Test name
Test status
Simulation time 358898834863 ps
CPU time 126.02 seconds
Started May 19 01:33:56 PM PDT 24
Finished May 19 01:36:03 PM PDT 24
Peak memory 201808 kb
Host smart-b15eeb60-c1fd-48a7-9a20-318a4a9b4114
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857724267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1857724267
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.553583611
Short name T55
Test name
Test status
Simulation time 8215547911 ps
CPU time 18.97 seconds
Started May 19 01:33:40 PM PDT 24
Finished May 19 01:34:00 PM PDT 24
Peak memory 218424 kb
Host smart-d1b035ac-1ce2-4880-b6d9-ba04c9d11ca2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553583611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.553583611
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.424224431
Short name T109
Test name
Test status
Simulation time 515427701 ps
CPU time 1.15 seconds
Started May 19 01:48:02 PM PDT 24
Finished May 19 01:48:03 PM PDT 24
Peak memory 201568 kb
Host smart-6dbd9796-d0bf-415c-9cbe-c288bdf81f93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424224431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.424224431
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.769762353
Short name T270
Test name
Test status
Simulation time 573233907725 ps
CPU time 1221.92 seconds
Started May 19 01:34:01 PM PDT 24
Finished May 19 01:54:24 PM PDT 24
Peak memory 201836 kb
Host smart-0c8cdba9-281b-45e2-9fa1-647cc287a2e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769762353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.769762353
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2584964566
Short name T29
Test name
Test status
Simulation time 341219444447 ps
CPU time 216.2 seconds
Started May 19 01:35:08 PM PDT 24
Finished May 19 01:38:45 PM PDT 24
Peak memory 201800 kb
Host smart-370ceda4-17f6-4657-8408-3023ac0aadae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584964566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2584964566
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3308992559
Short name T189
Test name
Test status
Simulation time 1241302168475 ps
CPU time 291.07 seconds
Started May 19 01:38:48 PM PDT 24
Finished May 19 01:43:39 PM PDT 24
Peak memory 210120 kb
Host smart-d09922e9-945d-41fa-8114-de5d63468763
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308992559 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3308992559
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1235353057
Short name T60
Test name
Test status
Simulation time 1139295467 ps
CPU time 2.62 seconds
Started May 19 01:47:58 PM PDT 24
Finished May 19 01:48:01 PM PDT 24
Peak memory 210100 kb
Host smart-f265bf64-6f43-43dd-a766-3348278b60ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235353057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1235353057
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1326782798
Short name T223
Test name
Test status
Simulation time 391586352245 ps
CPU time 120.62 seconds
Started May 19 01:33:51 PM PDT 24
Finished May 19 01:35:53 PM PDT 24
Peak memory 201880 kb
Host smart-4d39b764-40c2-446b-a4f9-e2be04d0ad9b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326782798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1326782798
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.190480343
Short name T172
Test name
Test status
Simulation time 500873445930 ps
CPU time 141.39 seconds
Started May 19 01:38:26 PM PDT 24
Finished May 19 01:40:48 PM PDT 24
Peak memory 201900 kb
Host smart-923a5411-0fe0-498c-9774-b5b321bf7d58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190480343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.190480343
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1017804098
Short name T140
Test name
Test status
Simulation time 490257816946 ps
CPU time 315.13 seconds
Started May 19 01:34:18 PM PDT 24
Finished May 19 01:39:34 PM PDT 24
Peak memory 201772 kb
Host smart-24c1ac42-6320-49b8-afad-a4fc214cd60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017804098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1017804098
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3213077656
Short name T265
Test name
Test status
Simulation time 166681167235 ps
CPU time 418.61 seconds
Started May 19 01:37:10 PM PDT 24
Finished May 19 01:44:09 PM PDT 24
Peak memory 202044 kb
Host smart-337cf035-a1fb-4a30-8715-164aef03335a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213077656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3213077656
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.171013535
Short name T257
Test name
Test status
Simulation time 521494010359 ps
CPU time 1207.07 seconds
Started May 19 01:33:29 PM PDT 24
Finished May 19 01:53:39 PM PDT 24
Peak memory 201808 kb
Host smart-f4b0f8c3-6d5a-4efb-8840-a67d5a6e7ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171013535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.171013535
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.96086437
Short name T220
Test name
Test status
Simulation time 327934149633 ps
CPU time 383.59 seconds
Started May 19 01:34:06 PM PDT 24
Finished May 19 01:40:32 PM PDT 24
Peak memory 201784 kb
Host smart-b26fc047-a250-450e-b514-cc8a0086f130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96086437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.96086437
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1064567880
Short name T293
Test name
Test status
Simulation time 38707779887 ps
CPU time 38.47 seconds
Started May 19 01:34:14 PM PDT 24
Finished May 19 01:34:55 PM PDT 24
Peak memory 202012 kb
Host smart-89136a36-3ee9-4a70-a9f0-423dd2dfbad3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064567880 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1064567880
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3037427601
Short name T245
Test name
Test status
Simulation time 532029205464 ps
CPU time 312.34 seconds
Started May 19 01:33:26 PM PDT 24
Finished May 19 01:38:42 PM PDT 24
Peak memory 201768 kb
Host smart-c493d256-0447-4100-a6a4-ba82c5d27751
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037427601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3037427601
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1194819751
Short name T129
Test name
Test status
Simulation time 373028631684 ps
CPU time 837.73 seconds
Started May 19 01:35:16 PM PDT 24
Finished May 19 01:49:14 PM PDT 24
Peak memory 201796 kb
Host smart-8718177a-6732-4e23-a1b0-e0bbae109e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194819751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1194819751
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1177889080
Short name T374
Test name
Test status
Simulation time 345066856 ps
CPU time 1.48 seconds
Started May 19 01:33:52 PM PDT 24
Finished May 19 01:33:55 PM PDT 24
Peak memory 201480 kb
Host smart-ed1e709b-034b-4292-9866-e720c2788c03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177889080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1177889080
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2181613124
Short name T20
Test name
Test status
Simulation time 342696803338 ps
CPU time 213.05 seconds
Started May 19 01:37:00 PM PDT 24
Finished May 19 01:40:33 PM PDT 24
Peak memory 210072 kb
Host smart-7a99551e-9804-4d11-9cc1-a7a292f20445
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181613124 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2181613124
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.4253861893
Short name T12
Test name
Test status
Simulation time 334064414390 ps
CPU time 718.88 seconds
Started May 19 01:34:32 PM PDT 24
Finished May 19 01:46:32 PM PDT 24
Peak memory 201800 kb
Host smart-9c651737-95bc-4a8d-b71e-9bef4625adc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253861893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.4253861893
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.564055959
Short name T146
Test name
Test status
Simulation time 108248557946 ps
CPU time 221 seconds
Started May 19 01:34:32 PM PDT 24
Finished May 19 01:38:14 PM PDT 24
Peak memory 210164 kb
Host smart-b8a2e2e9-d905-4401-9b3a-492bd0a521cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564055959 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.564055959
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2207442065
Short name T309
Test name
Test status
Simulation time 523616079197 ps
CPU time 212.44 seconds
Started May 19 01:35:44 PM PDT 24
Finished May 19 01:39:17 PM PDT 24
Peak memory 201832 kb
Host smart-8d2cb144-8bc1-4ae0-98af-df97e7b0e164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207442065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2207442065
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2723809481
Short name T271
Test name
Test status
Simulation time 175911990351 ps
CPU time 392.62 seconds
Started May 19 01:33:58 PM PDT 24
Finished May 19 01:40:31 PM PDT 24
Peak memory 201808 kb
Host smart-11cef8b9-d114-4a7c-bf7a-5229a77ee5d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723809481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2723809481
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3884697842
Short name T213
Test name
Test status
Simulation time 555863371905 ps
CPU time 629.31 seconds
Started May 19 01:34:37 PM PDT 24
Finished May 19 01:45:07 PM PDT 24
Peak memory 201816 kb
Host smart-2cad36e9-ed67-4a18-bb7d-0f495241802e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884697842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3884697842
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.844216772
Short name T154
Test name
Test status
Simulation time 197847788670 ps
CPU time 296.92 seconds
Started May 19 01:35:39 PM PDT 24
Finished May 19 01:40:37 PM PDT 24
Peak memory 201776 kb
Host smart-182d21d2-564d-4b70-809c-5c058ba37e91
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844216772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.844216772
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.245393780
Short name T234
Test name
Test status
Simulation time 437148279688 ps
CPU time 410.96 seconds
Started May 19 01:34:14 PM PDT 24
Finished May 19 01:41:08 PM PDT 24
Peak memory 202080 kb
Host smart-4a5e8ed6-1b69-4813-98ab-14c9becb6c49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245393780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
245393780
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3516412056
Short name T187
Test name
Test status
Simulation time 167606827730 ps
CPU time 142.65 seconds
Started May 19 01:38:10 PM PDT 24
Finished May 19 01:40:33 PM PDT 24
Peak memory 201764 kb
Host smart-b0e7e228-a3c5-4614-a58b-4b70f5a63d43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516412056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3516412056
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.585884752
Short name T331
Test name
Test status
Simulation time 338277036185 ps
CPU time 693.71 seconds
Started May 19 01:34:21 PM PDT 24
Finished May 19 01:45:56 PM PDT 24
Peak memory 201800 kb
Host smart-a5d201ac-201a-42ec-a330-109bc7a3104c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585884752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.585884752
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1708368014
Short name T308
Test name
Test status
Simulation time 380232207364 ps
CPU time 271.93 seconds
Started May 19 01:34:24 PM PDT 24
Finished May 19 01:38:56 PM PDT 24
Peak memory 210464 kb
Host smart-751d1960-1745-4e46-8c9e-d02f2095c7f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708368014 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1708368014
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.725723992
Short name T287
Test name
Test status
Simulation time 359941622521 ps
CPU time 300.21 seconds
Started May 19 01:33:33 PM PDT 24
Finished May 19 01:38:36 PM PDT 24
Peak memory 201768 kb
Host smart-db7da5e5-2702-4730-ac5d-19110e244686
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725723992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.725723992
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.4213723409
Short name T276
Test name
Test status
Simulation time 488431974684 ps
CPU time 360.88 seconds
Started May 19 01:35:11 PM PDT 24
Finished May 19 01:41:12 PM PDT 24
Peak memory 201848 kb
Host smart-0d16355b-ebd4-4f5b-be66-3b1f4d7cec40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213723409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.4213723409
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2643016227
Short name T251
Test name
Test status
Simulation time 528536940937 ps
CPU time 1308.63 seconds
Started May 19 01:34:11 PM PDT 24
Finished May 19 01:56:01 PM PDT 24
Peak memory 201828 kb
Host smart-e634b5d5-f101-4de9-a53e-757a43bdd5e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643016227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2643016227
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.113399013
Short name T32
Test name
Test status
Simulation time 496918607275 ps
CPU time 1248.02 seconds
Started May 19 01:34:13 PM PDT 24
Finished May 19 01:55:04 PM PDT 24
Peak memory 201824 kb
Host smart-c43d269b-e7ab-4f5e-bb7f-c5ac761542c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113399013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
113399013
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.668406365
Short name T243
Test name
Test status
Simulation time 333273540226 ps
CPU time 830.1 seconds
Started May 19 01:35:52 PM PDT 24
Finished May 19 01:49:43 PM PDT 24
Peak memory 201880 kb
Host smart-7404020d-3b39-4980-ab88-6162dcfa6ac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668406365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
668406365
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.978637490
Short name T230
Test name
Test status
Simulation time 132144586920 ps
CPU time 655.91 seconds
Started May 19 01:34:09 PM PDT 24
Finished May 19 01:45:06 PM PDT 24
Peak memory 202120 kb
Host smart-f4243f6c-8c01-4640-a50f-190cf4d79b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978637490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.978637490
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1367337406
Short name T379
Test name
Test status
Simulation time 160659641801 ps
CPU time 96.13 seconds
Started May 19 01:33:24 PM PDT 24
Finished May 19 01:35:04 PM PDT 24
Peak memory 201704 kb
Host smart-4feee4be-fb14-43a4-b5c6-3c3a3b74a5f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367337406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1367337406
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2523623100
Short name T273
Test name
Test status
Simulation time 333398588083 ps
CPU time 120.4 seconds
Started May 19 01:34:15 PM PDT 24
Finished May 19 01:36:17 PM PDT 24
Peak memory 201828 kb
Host smart-bebe8339-ff40-4620-8b02-00d3abf3cc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523623100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2523623100
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2100974287
Short name T305
Test name
Test status
Simulation time 164763604198 ps
CPU time 126.94 seconds
Started May 19 01:37:35 PM PDT 24
Finished May 19 01:39:43 PM PDT 24
Peak memory 202084 kb
Host smart-043be218-f918-449c-a421-0bae63d43c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100974287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2100974287
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1748394576
Short name T268
Test name
Test status
Simulation time 467862022077 ps
CPU time 362.8 seconds
Started May 19 01:33:57 PM PDT 24
Finished May 19 01:40:00 PM PDT 24
Peak memory 210488 kb
Host smart-ab1fef0e-32aa-4df3-b3f6-268e74541bc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748394576 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1748394576
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3529642255
Short name T76
Test name
Test status
Simulation time 62467627298 ps
CPU time 144.05 seconds
Started May 19 01:34:11 PM PDT 24
Finished May 19 01:36:36 PM PDT 24
Peak memory 210732 kb
Host smart-17816885-3c61-4048-a9fb-b5686433db14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529642255 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3529642255
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2322413275
Short name T142
Test name
Test status
Simulation time 706393655043 ps
CPU time 1358.31 seconds
Started May 19 01:34:56 PM PDT 24
Finished May 19 01:57:37 PM PDT 24
Peak memory 201860 kb
Host smart-ab3368ed-6dc9-45db-9865-86812b054183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322413275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2322413275
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1812325615
Short name T326
Test name
Test status
Simulation time 158194053703 ps
CPU time 281.75 seconds
Started May 19 01:33:51 PM PDT 24
Finished May 19 01:38:35 PM PDT 24
Peak memory 218368 kb
Host smart-747236f4-a976-4d51-9bd0-095ba77f0579
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812325615 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1812325615
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3697782735
Short name T291
Test name
Test status
Simulation time 165482223131 ps
CPU time 99.41 seconds
Started May 19 01:37:35 PM PDT 24
Finished May 19 01:39:15 PM PDT 24
Peak memory 201772 kb
Host smart-ad7d9c50-76db-416f-8e37-a725483f8b10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697782735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3697782735
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.560609719
Short name T315
Test name
Test status
Simulation time 87216395792 ps
CPU time 116.43 seconds
Started May 19 01:33:38 PM PDT 24
Finished May 19 01:35:36 PM PDT 24
Peak memory 210504 kb
Host smart-0d71603d-8f0a-44a0-87a7-0e4f1a5bb6b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560609719 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.560609719
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1050527814
Short name T22
Test name
Test status
Simulation time 54034547969 ps
CPU time 137.24 seconds
Started May 19 01:33:40 PM PDT 24
Finished May 19 01:35:59 PM PDT 24
Peak memory 210564 kb
Host smart-86719c88-6dcb-4991-af03-47f861bf73c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050527814 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1050527814
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.763680060
Short name T37
Test name
Test status
Simulation time 31829832646 ps
CPU time 75.54 seconds
Started May 19 01:36:10 PM PDT 24
Finished May 19 01:37:26 PM PDT 24
Peak memory 210148 kb
Host smart-ef660069-86d9-404f-be9c-26ec4ded769d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763680060 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.763680060
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2446593730
Short name T181
Test name
Test status
Simulation time 192325618264 ps
CPU time 239.83 seconds
Started May 19 01:37:20 PM PDT 24
Finished May 19 01:41:20 PM PDT 24
Peak memory 201844 kb
Host smart-e07de4ba-86ed-4894-8337-cca1b0bba6f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446593730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2446593730
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.103218000
Short name T125
Test name
Test status
Simulation time 4999488938 ps
CPU time 4.23 seconds
Started May 19 01:47:53 PM PDT 24
Finished May 19 01:47:58 PM PDT 24
Peak memory 202140 kb
Host smart-17e36a57-e753-4daf-8392-27fe5e57de92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103218000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.103218000
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2366651076
Short name T221
Test name
Test status
Simulation time 530517797262 ps
CPU time 86.56 seconds
Started May 19 01:34:28 PM PDT 24
Finished May 19 01:35:55 PM PDT 24
Peak memory 201844 kb
Host smart-93d162ff-a84d-4463-8809-2a0cb21b4f14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366651076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2366651076
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2009591857
Short name T144
Test name
Test status
Simulation time 365225745653 ps
CPU time 62.03 seconds
Started May 19 01:34:38 PM PDT 24
Finished May 19 01:35:41 PM PDT 24
Peak memory 201892 kb
Host smart-ad9f7fa6-bde7-4f6c-b15b-613b651f0a6e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009591857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2009591857
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.341297803
Short name T137
Test name
Test status
Simulation time 491342276325 ps
CPU time 310.95 seconds
Started May 19 01:34:43 PM PDT 24
Finished May 19 01:39:55 PM PDT 24
Peak memory 201840 kb
Host smart-5c2b42f9-0aef-4f9c-88a3-33fc99727fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341297803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.341297803
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1156126046
Short name T260
Test name
Test status
Simulation time 330814000989 ps
CPU time 205.21 seconds
Started May 19 01:34:55 PM PDT 24
Finished May 19 01:38:22 PM PDT 24
Peak memory 201920 kb
Host smart-92312cdb-617a-44ca-a083-5aecade5f597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156126046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1156126046
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1531966546
Short name T777
Test name
Test status
Simulation time 105357163682 ps
CPU time 429.34 seconds
Started May 19 01:35:15 PM PDT 24
Finished May 19 01:42:25 PM PDT 24
Peak memory 202176 kb
Host smart-1a2520bb-ac69-42b1-9b73-fde7cda782a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531966546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1531966546
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.552848295
Short name T328
Test name
Test status
Simulation time 355482237321 ps
CPU time 888.1 seconds
Started May 19 01:36:23 PM PDT 24
Finished May 19 01:51:12 PM PDT 24
Peak memory 201808 kb
Host smart-2abca596-a5fd-4a0e-af76-ca5dce523a78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552848295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
552848295
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2932511185
Short name T278
Test name
Test status
Simulation time 504081410683 ps
CPU time 311.27 seconds
Started May 19 01:33:45 PM PDT 24
Finished May 19 01:38:57 PM PDT 24
Peak memory 201884 kb
Host smart-d8407057-e12a-4b2e-8d6c-797e92f3b6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932511185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2932511185
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1454539653
Short name T516
Test name
Test status
Simulation time 114247550620 ps
CPU time 416.75 seconds
Started May 19 01:33:54 PM PDT 24
Finished May 19 01:40:52 PM PDT 24
Peak memory 202080 kb
Host smart-b3a7c68a-f54e-4b84-8649-181d9e18c35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454539653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1454539653
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.883395263
Short name T238
Test name
Test status
Simulation time 453860652772 ps
CPU time 478.26 seconds
Started May 19 01:33:51 PM PDT 24
Finished May 19 01:41:51 PM PDT 24
Peak memory 202108 kb
Host smart-461e007e-54b0-43d4-8fd0-d323ad061f67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883395263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
883395263
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2503469273
Short name T314
Test name
Test status
Simulation time 529711413309 ps
CPU time 1251.12 seconds
Started May 19 01:34:08 PM PDT 24
Finished May 19 01:55:01 PM PDT 24
Peak memory 201764 kb
Host smart-1a50b78b-0945-468f-8fd2-9e3e5fd790a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503469273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2503469273
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.4254712012
Short name T254
Test name
Test status
Simulation time 433378258725 ps
CPU time 293.23 seconds
Started May 19 01:34:13 PM PDT 24
Finished May 19 01:39:09 PM PDT 24
Peak memory 201848 kb
Host smart-b188fc8a-fc10-4e8d-9154-2537f185baf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254712012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.4254712012
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1421054492
Short name T280
Test name
Test status
Simulation time 556135826539 ps
CPU time 246.13 seconds
Started May 19 01:35:05 PM PDT 24
Finished May 19 01:39:11 PM PDT 24
Peak memory 201808 kb
Host smart-07d8b71a-9db8-4baa-9a28-46785896f13e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421054492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1421054492
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1341295116
Short name T240
Test name
Test status
Simulation time 85639968341 ps
CPU time 335.4 seconds
Started May 19 01:37:12 PM PDT 24
Finished May 19 01:42:47 PM PDT 24
Peak memory 202184 kb
Host smart-bd5546ae-f31d-47c2-bf1c-e3c4d44a1d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341295116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1341295116
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.4172163555
Short name T323
Test name
Test status
Simulation time 153397321255 ps
CPU time 78.7 seconds
Started May 19 01:38:02 PM PDT 24
Finished May 19 01:39:21 PM PDT 24
Peak memory 210208 kb
Host smart-103f7b55-7f7e-44bb-a013-5ebb7e3e120e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172163555 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.4172163555
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3641288586
Short name T833
Test name
Test status
Simulation time 480386718 ps
CPU time 3.36 seconds
Started May 19 01:47:53 PM PDT 24
Finished May 19 01:47:57 PM PDT 24
Peak memory 217884 kb
Host smart-7d87afbc-0397-4089-bc22-9866e52f6b65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641288586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3641288586
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3184271179
Short name T54
Test name
Test status
Simulation time 8077247382 ps
CPU time 20.75 seconds
Started May 19 01:47:37 PM PDT 24
Finished May 19 01:47:59 PM PDT 24
Peak memory 201968 kb
Host smart-3432f07c-aecd-4f2a-88a8-afd2b0cc9713
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184271179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3184271179
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1824976588
Short name T267
Test name
Test status
Simulation time 583969022239 ps
CPU time 1380.78 seconds
Started May 19 01:33:52 PM PDT 24
Finished May 19 01:56:54 PM PDT 24
Peak memory 201804 kb
Host smart-b63faafe-a4ca-4f79-b2ae-34fb037f9836
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824976588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1824976588
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3928985725
Short name T286
Test name
Test status
Simulation time 444392554387 ps
CPU time 263.93 seconds
Started May 19 01:34:05 PM PDT 24
Finished May 19 01:38:31 PM PDT 24
Peak memory 201844 kb
Host smart-d25b67c8-5ce5-4717-b708-a950d8e01f14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928985725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3928985725
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3149697201
Short name T35
Test name
Test status
Simulation time 237959435471 ps
CPU time 668.75 seconds
Started May 19 01:34:15 PM PDT 24
Finished May 19 01:45:26 PM PDT 24
Peak memory 210312 kb
Host smart-99d0bbdc-8549-457f-be8c-36081df9ee83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149697201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3149697201
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2818802207
Short name T318
Test name
Test status
Simulation time 344368856015 ps
CPU time 246.55 seconds
Started May 19 01:34:21 PM PDT 24
Finished May 19 01:38:28 PM PDT 24
Peak memory 201844 kb
Host smart-6b36fe83-cc02-40c5-a032-920583589fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818802207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2818802207
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2140775881
Short name T277
Test name
Test status
Simulation time 166935796349 ps
CPU time 411.64 seconds
Started May 19 01:34:32 PM PDT 24
Finished May 19 01:41:24 PM PDT 24
Peak memory 201860 kb
Host smart-388a666f-bebd-4d9d-a5cf-ef0bac442881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140775881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2140775881
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2511350972
Short name T340
Test name
Test status
Simulation time 355351597481 ps
CPU time 918.31 seconds
Started May 19 01:35:01 PM PDT 24
Finished May 19 01:50:21 PM PDT 24
Peak memory 201880 kb
Host smart-56a4bee8-8cfd-4fe2-b025-8c61ca08b5fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511350972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2511350972
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.79244821
Short name T136
Test name
Test status
Simulation time 331233294207 ps
CPU time 766.51 seconds
Started May 19 01:35:08 PM PDT 24
Finished May 19 01:47:54 PM PDT 24
Peak memory 201868 kb
Host smart-90f133f0-6df5-4222-af6c-262de6012d20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79244821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.79244821
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1179545229
Short name T227
Test name
Test status
Simulation time 119433101153 ps
CPU time 420.93 seconds
Started May 19 01:36:09 PM PDT 24
Finished May 19 01:43:10 PM PDT 24
Peak memory 202076 kb
Host smart-61301608-d162-4a13-9659-d941d8e4fb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179545229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1179545229
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1120961729
Short name T18
Test name
Test status
Simulation time 80572856673 ps
CPU time 149.77 seconds
Started May 19 01:33:36 PM PDT 24
Finished May 19 01:36:07 PM PDT 24
Peak memory 210448 kb
Host smart-4dc926d2-9bc8-4473-b4c2-c710d8285ab7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120961729 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1120961729
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3805717608
Short name T269
Test name
Test status
Simulation time 522984376389 ps
CPU time 744.16 seconds
Started May 19 01:33:37 PM PDT 24
Finished May 19 01:46:03 PM PDT 24
Peak memory 201776 kb
Host smart-dc29525a-8f4f-4daf-b01e-67766cacf215
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805717608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3805717608
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.274298942
Short name T118
Test name
Test status
Simulation time 1045906518 ps
CPU time 2.87 seconds
Started May 19 01:47:42 PM PDT 24
Finished May 19 01:47:46 PM PDT 24
Peak memory 201824 kb
Host smart-17652af8-f495-4a2c-ad69-63e35e22197c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274298942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.274298942
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1908445787
Short name T831
Test name
Test status
Simulation time 26352202562 ps
CPU time 37.74 seconds
Started May 19 01:47:42 PM PDT 24
Finished May 19 01:48:20 PM PDT 24
Peak memory 201944 kb
Host smart-028803fc-68de-45bf-bc49-868b317202b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908445787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1908445787
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3031094614
Short name T127
Test name
Test status
Simulation time 803797263 ps
CPU time 0.89 seconds
Started May 19 01:47:40 PM PDT 24
Finished May 19 01:47:41 PM PDT 24
Peak memory 201672 kb
Host smart-84b69df5-9507-4f73-bbfb-c994ccca0e05
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031094614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3031094614
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.4058551925
Short name T904
Test name
Test status
Simulation time 427315918 ps
CPU time 1.18 seconds
Started May 19 01:47:41 PM PDT 24
Finished May 19 01:47:43 PM PDT 24
Peak memory 201776 kb
Host smart-821562a2-5567-4a62-88dc-4784a9b10007
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058551925 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.4058551925
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4220954721
Short name T881
Test name
Test status
Simulation time 465895460 ps
CPU time 1.62 seconds
Started May 19 01:47:38 PM PDT 24
Finished May 19 01:47:40 PM PDT 24
Peak memory 201680 kb
Host smart-5b8c6d9a-d172-4e5f-a82e-da3223a41b31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220954721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.4220954721
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3543137571
Short name T806
Test name
Test status
Simulation time 334742922 ps
CPU time 1.44 seconds
Started May 19 01:47:53 PM PDT 24
Finished May 19 01:47:55 PM PDT 24
Peak memory 201648 kb
Host smart-dded3d2f-c5d8-4db4-ab75-515fa71155a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543137571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3543137571
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2025726045
Short name T852
Test name
Test status
Simulation time 5186562397 ps
CPU time 4.1 seconds
Started May 19 01:47:53 PM PDT 24
Finished May 19 01:47:58 PM PDT 24
Peak memory 201956 kb
Host smart-83b69b9a-ba78-4d63-9b41-d046c8c8311c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025726045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2025726045
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1311815307
Short name T863
Test name
Test status
Simulation time 309565340 ps
CPU time 2.75 seconds
Started May 19 01:47:38 PM PDT 24
Finished May 19 01:47:41 PM PDT 24
Peak memory 218524 kb
Host smart-3939e36c-673c-4127-8b19-637f27baa6ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311815307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1311815307
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2599643954
Short name T883
Test name
Test status
Simulation time 4740068403 ps
CPU time 11.54 seconds
Started May 19 01:47:41 PM PDT 24
Finished May 19 01:47:53 PM PDT 24
Peak memory 201984 kb
Host smart-ac066d81-e92a-4d53-870a-47a649881126
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599643954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2599643954
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1976492541
Short name T897
Test name
Test status
Simulation time 1325445329 ps
CPU time 4.01 seconds
Started May 19 01:47:48 PM PDT 24
Finished May 19 01:47:52 PM PDT 24
Peak memory 201864 kb
Host smart-126a783b-676d-4bf0-9d89-0799d3b327dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976492541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1976492541
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3262265377
Short name T114
Test name
Test status
Simulation time 19414705027 ps
CPU time 8.51 seconds
Started May 19 01:47:38 PM PDT 24
Finished May 19 01:47:47 PM PDT 24
Peak memory 201900 kb
Host smart-2179204b-c451-4e26-82b6-aa0cc2cf1252
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262265377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3262265377
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1965253549
Short name T113
Test name
Test status
Simulation time 1200752114 ps
CPU time 2.09 seconds
Started May 19 01:47:42 PM PDT 24
Finished May 19 01:47:45 PM PDT 24
Peak memory 201644 kb
Host smart-c6571221-c5e4-4b12-a2b1-543c90fdd936
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965253549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.1965253549
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.975087069
Short name T870
Test name
Test status
Simulation time 602233657 ps
CPU time 1.34 seconds
Started May 19 01:47:39 PM PDT 24
Finished May 19 01:47:41 PM PDT 24
Peak memory 201740 kb
Host smart-fb47371d-f868-4f92-905a-5634f19d5b3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975087069 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.975087069
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2045903276
Short name T126
Test name
Test status
Simulation time 338897851 ps
CPU time 1.42 seconds
Started May 19 01:47:41 PM PDT 24
Finished May 19 01:47:43 PM PDT 24
Peak memory 201672 kb
Host smart-e21ac331-b66c-4efe-ba76-abc1ee90c73e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045903276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2045903276
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3905171319
Short name T914
Test name
Test status
Simulation time 521073135 ps
CPU time 0.96 seconds
Started May 19 01:47:40 PM PDT 24
Finished May 19 01:47:41 PM PDT 24
Peak memory 201676 kb
Host smart-49c23243-85cb-4072-ab36-4718555028a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905171319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3905171319
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3969325996
Short name T912
Test name
Test status
Simulation time 2412932668 ps
CPU time 6.13 seconds
Started May 19 01:47:40 PM PDT 24
Finished May 19 01:47:47 PM PDT 24
Peak memory 201912 kb
Host smart-97968346-6854-41a9-a0bb-12b31e36be09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969325996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3969325996
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.4153246280
Short name T916
Test name
Test status
Simulation time 448550618 ps
CPU time 2.94 seconds
Started May 19 01:47:41 PM PDT 24
Finished May 19 01:47:45 PM PDT 24
Peak memory 217920 kb
Host smart-a0b42855-3db7-4c7a-8d55-83d3733d3cb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153246280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.4153246280
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1983976768
Short name T68
Test name
Test status
Simulation time 4368717713 ps
CPU time 3.68 seconds
Started May 19 01:47:40 PM PDT 24
Finished May 19 01:47:44 PM PDT 24
Peak memory 201968 kb
Host smart-7c4f8b94-99a9-485d-8292-95243d03775f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983976768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1983976768
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2348532154
Short name T908
Test name
Test status
Simulation time 579507848 ps
CPU time 2.25 seconds
Started May 19 01:47:58 PM PDT 24
Finished May 19 01:48:01 PM PDT 24
Peak memory 201708 kb
Host smart-b8ac96ce-ac10-4367-a8d4-babe636f1d8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348532154 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2348532154
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1427988107
Short name T874
Test name
Test status
Simulation time 538760565 ps
CPU time 1.36 seconds
Started May 19 01:47:54 PM PDT 24
Finished May 19 01:47:57 PM PDT 24
Peak memory 201672 kb
Host smart-1a26f83e-d571-4a04-a8ab-fc9e571b6171
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427988107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1427988107
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1813871734
Short name T837
Test name
Test status
Simulation time 473032002 ps
CPU time 1.15 seconds
Started May 19 01:47:51 PM PDT 24
Finished May 19 01:47:53 PM PDT 24
Peak memory 201700 kb
Host smart-7e7c4981-1d60-4d36-8175-16ee321f1377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813871734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1813871734
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3310104328
Short name T365
Test name
Test status
Simulation time 4628282016 ps
CPU time 4.61 seconds
Started May 19 01:47:53 PM PDT 24
Finished May 19 01:47:59 PM PDT 24
Peak memory 201928 kb
Host smart-9957462e-1331-4c3d-b883-9eeace0eb8f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310104328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3310104328
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3813501292
Short name T59
Test name
Test status
Simulation time 640650997 ps
CPU time 1.1 seconds
Started May 19 01:47:55 PM PDT 24
Finished May 19 01:47:57 PM PDT 24
Peak memory 201684 kb
Host smart-4508ad01-1115-4ac0-90c9-4d6007532a61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813501292 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3813501292
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2170471923
Short name T867
Test name
Test status
Simulation time 425628941 ps
CPU time 1.45 seconds
Started May 19 01:47:57 PM PDT 24
Finished May 19 01:47:59 PM PDT 24
Peak memory 201924 kb
Host smart-603ff63e-e373-4960-8195-5e56e2207d22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170471923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2170471923
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2216937855
Short name T830
Test name
Test status
Simulation time 542401531 ps
CPU time 0.91 seconds
Started May 19 01:47:56 PM PDT 24
Finished May 19 01:47:57 PM PDT 24
Peak memory 201612 kb
Host smart-d53b5397-2b79-4ca1-8d39-c18af934c472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216937855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2216937855
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2553762881
Short name T835
Test name
Test status
Simulation time 2931211266 ps
CPU time 1.93 seconds
Started May 19 01:47:55 PM PDT 24
Finished May 19 01:47:58 PM PDT 24
Peak memory 201704 kb
Host smart-227a4378-1669-473b-b434-0f7f58b02c0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553762881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2553762881
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1032171971
Short name T62
Test name
Test status
Simulation time 519408054 ps
CPU time 2.56 seconds
Started May 19 01:47:58 PM PDT 24
Finished May 19 01:48:01 PM PDT 24
Peak memory 202004 kb
Host smart-b220bbbd-9734-43c4-869e-9100e1d4cf8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032171971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1032171971
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1548135197
Short name T910
Test name
Test status
Simulation time 4087874917 ps
CPU time 6.29 seconds
Started May 19 01:47:56 PM PDT 24
Finished May 19 01:48:04 PM PDT 24
Peak memory 201952 kb
Host smart-422f1262-a7ad-4b79-981b-6561c185e56d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548135197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1548135197
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4194511596
Short name T848
Test name
Test status
Simulation time 443531742 ps
CPU time 1.04 seconds
Started May 19 01:47:56 PM PDT 24
Finished May 19 01:47:58 PM PDT 24
Peak memory 201736 kb
Host smart-96c93692-856b-4157-ab8e-f34f56ff0a27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194511596 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.4194511596
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.129196214
Short name T880
Test name
Test status
Simulation time 420701473 ps
CPU time 1.81 seconds
Started May 19 01:47:56 PM PDT 24
Finished May 19 01:47:59 PM PDT 24
Peak memory 201668 kb
Host smart-1d74694d-f173-4b21-b763-adf6e9258c13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129196214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.129196214
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3743910077
Short name T797
Test name
Test status
Simulation time 465233574 ps
CPU time 0.72 seconds
Started May 19 01:47:56 PM PDT 24
Finished May 19 01:47:57 PM PDT 24
Peak memory 201684 kb
Host smart-3159428f-afb0-458c-b8bd-60eef2fdea72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743910077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3743910077
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2283110714
Short name T918
Test name
Test status
Simulation time 2398934387 ps
CPU time 3.4 seconds
Started May 19 01:47:56 PM PDT 24
Finished May 19 01:48:01 PM PDT 24
Peak memory 201716 kb
Host smart-a3fb0348-94ac-4482-a151-e0dafc24182a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283110714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2283110714
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.4110377620
Short name T845
Test name
Test status
Simulation time 8757208227 ps
CPU time 17.55 seconds
Started May 19 01:48:03 PM PDT 24
Finished May 19 01:48:21 PM PDT 24
Peak memory 201900 kb
Host smart-8dec06dd-c243-43b0-99c3-52f62a9e3e05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110377620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.4110377620
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3877511688
Short name T79
Test name
Test status
Simulation time 418169582 ps
CPU time 1.25 seconds
Started May 19 01:48:02 PM PDT 24
Finished May 19 01:48:04 PM PDT 24
Peak memory 201984 kb
Host smart-e6574a63-09c0-43fc-8ced-ab1f4d67561f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877511688 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3877511688
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3258648057
Short name T893
Test name
Test status
Simulation time 493819583 ps
CPU time 0.92 seconds
Started May 19 01:48:03 PM PDT 24
Finished May 19 01:48:05 PM PDT 24
Peak memory 201664 kb
Host smart-e4cfe5c4-4918-4445-9a67-727b9516a77e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258648057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3258648057
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2143064768
Short name T811
Test name
Test status
Simulation time 2677583701 ps
CPU time 3.06 seconds
Started May 19 01:48:04 PM PDT 24
Finished May 19 01:48:07 PM PDT 24
Peak memory 201740 kb
Host smart-e043d75a-9c7c-44b2-9d4c-5fa752846f41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143064768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2143064768
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3860039112
Short name T53
Test name
Test status
Simulation time 544370591 ps
CPU time 1.85 seconds
Started May 19 01:48:03 PM PDT 24
Finished May 19 01:48:05 PM PDT 24
Peak memory 201988 kb
Host smart-0c245be8-8f6f-4a7e-a23d-a4e7dad85df7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860039112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3860039112
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.734162280
Short name T364
Test name
Test status
Simulation time 7739634552 ps
CPU time 20.8 seconds
Started May 19 01:48:02 PM PDT 24
Finished May 19 01:48:23 PM PDT 24
Peak memory 201920 kb
Host smart-2fb9c6a6-e89c-4834-9669-0bf5dd49803d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734162280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_in
tg_err.734162280
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3975081919
Short name T894
Test name
Test status
Simulation time 484386174 ps
CPU time 1.41 seconds
Started May 19 01:48:04 PM PDT 24
Finished May 19 01:48:06 PM PDT 24
Peak memory 201736 kb
Host smart-21879729-fd8d-46ca-b28b-877296182413
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975081919 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3975081919
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.4208277349
Short name T116
Test name
Test status
Simulation time 550297307 ps
CPU time 1.04 seconds
Started May 19 01:48:00 PM PDT 24
Finished May 19 01:48:02 PM PDT 24
Peak memory 201704 kb
Host smart-3b3a537a-ba3e-4116-8252-d098e032b87c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208277349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.4208277349
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.187228584
Short name T799
Test name
Test status
Simulation time 493710117 ps
CPU time 1.19 seconds
Started May 19 01:48:01 PM PDT 24
Finished May 19 01:48:03 PM PDT 24
Peak memory 201700 kb
Host smart-da50833a-8ac7-4f89-8b05-a5c18dd4866e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187228584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.187228584
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3686354702
Short name T123
Test name
Test status
Simulation time 2367605292 ps
CPU time 8.15 seconds
Started May 19 01:48:01 PM PDT 24
Finished May 19 01:48:09 PM PDT 24
Peak memory 201740 kb
Host smart-4cd0fd07-ffe4-4914-8c77-d2b7a658c571
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686354702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3686354702
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2676835305
Short name T865
Test name
Test status
Simulation time 473177082 ps
CPU time 2.6 seconds
Started May 19 01:48:00 PM PDT 24
Finished May 19 01:48:03 PM PDT 24
Peak memory 202208 kb
Host smart-e518ca97-3ff6-4b6c-a66a-616564546e26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676835305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2676835305
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1355006443
Short name T886
Test name
Test status
Simulation time 4635559630 ps
CPU time 11.95 seconds
Started May 19 01:47:59 PM PDT 24
Finished May 19 01:48:11 PM PDT 24
Peak memory 201956 kb
Host smart-d0b8ec35-bccf-4a9a-8273-53adc1bfb874
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355006443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1355006443
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3541423626
Short name T78
Test name
Test status
Simulation time 519168225 ps
CPU time 1.09 seconds
Started May 19 01:48:10 PM PDT 24
Finished May 19 01:48:12 PM PDT 24
Peak memory 201700 kb
Host smart-a19a38eb-9a48-4f16-a2eb-95ccf2d3bac9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541423626 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3541423626
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2713529164
Short name T121
Test name
Test status
Simulation time 623361682 ps
CPU time 0.93 seconds
Started May 19 01:48:02 PM PDT 24
Finished May 19 01:48:03 PM PDT 24
Peak memory 201632 kb
Host smart-70845b42-3ea5-4ebb-93ce-d8d31d8ec605
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713529164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2713529164
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1865725916
Short name T853
Test name
Test status
Simulation time 474207247 ps
CPU time 1.92 seconds
Started May 19 01:48:01 PM PDT 24
Finished May 19 01:48:04 PM PDT 24
Peak memory 201588 kb
Host smart-4940be5c-ce51-438e-b9c2-db86e64240e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865725916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1865725916
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1993207163
Short name T839
Test name
Test status
Simulation time 2488193270 ps
CPU time 2.53 seconds
Started May 19 01:48:11 PM PDT 24
Finished May 19 01:48:15 PM PDT 24
Peak memory 201932 kb
Host smart-123c61e6-7fa0-46b7-99f3-92b713f301c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993207163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1993207163
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2441084206
Short name T842
Test name
Test status
Simulation time 467894719 ps
CPU time 3.17 seconds
Started May 19 01:48:02 PM PDT 24
Finished May 19 01:48:06 PM PDT 24
Peak memory 201916 kb
Host smart-1c1bca24-a97d-4616-ab5e-a8c558963572
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441084206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2441084206
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.831151775
Short name T882
Test name
Test status
Simulation time 670033802 ps
CPU time 2.4 seconds
Started May 19 01:48:10 PM PDT 24
Finished May 19 01:48:13 PM PDT 24
Peak memory 201740 kb
Host smart-bae39bad-fb3d-4764-9c07-82bed8bbfd2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831151775 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.831151775
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.992999809
Short name T832
Test name
Test status
Simulation time 513585239 ps
CPU time 1.92 seconds
Started May 19 01:48:10 PM PDT 24
Finished May 19 01:48:13 PM PDT 24
Peak memory 201620 kb
Host smart-a9bfb388-a444-4ace-9b47-02443a026a2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992999809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.992999809
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2454273097
Short name T895
Test name
Test status
Simulation time 601819398 ps
CPU time 0.73 seconds
Started May 19 01:48:09 PM PDT 24
Finished May 19 01:48:11 PM PDT 24
Peak memory 201648 kb
Host smart-85b7e7c3-d481-46fc-89db-02e35e4db559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454273097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2454273097
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3243965047
Short name T822
Test name
Test status
Simulation time 4857373582 ps
CPU time 8.74 seconds
Started May 19 01:48:05 PM PDT 24
Finished May 19 01:48:14 PM PDT 24
Peak memory 201876 kb
Host smart-83786b97-afcd-4db9-a473-5f4ec400534f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243965047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3243965047
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3409577246
Short name T859
Test name
Test status
Simulation time 405638690 ps
CPU time 2.45 seconds
Started May 19 01:48:05 PM PDT 24
Finished May 19 01:48:08 PM PDT 24
Peak memory 201952 kb
Host smart-2e529a3b-5c95-4f67-8b74-4094bf8239e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409577246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3409577246
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3669445184
Short name T841
Test name
Test status
Simulation time 4183587862 ps
CPU time 10.78 seconds
Started May 19 01:48:06 PM PDT 24
Finished May 19 01:48:18 PM PDT 24
Peak memory 201904 kb
Host smart-4d4de2cd-cd1d-4814-be47-513ede8ad6b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669445184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3669445184
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.4248333666
Short name T857
Test name
Test status
Simulation time 410990602 ps
CPU time 1.03 seconds
Started May 19 01:48:07 PM PDT 24
Finished May 19 01:48:08 PM PDT 24
Peak memory 201768 kb
Host smart-9b263b29-fdcc-4de7-999a-71fb8159e7db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248333666 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.4248333666
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1626133982
Short name T844
Test name
Test status
Simulation time 515731672 ps
CPU time 1.02 seconds
Started May 19 01:48:05 PM PDT 24
Finished May 19 01:48:07 PM PDT 24
Peak memory 201680 kb
Host smart-c944a7ae-6915-4ac2-9bb4-cda4c355e219
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626133982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1626133982
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.277917552
Short name T803
Test name
Test status
Simulation time 532011878 ps
CPU time 0.85 seconds
Started May 19 01:48:08 PM PDT 24
Finished May 19 01:48:10 PM PDT 24
Peak memory 201652 kb
Host smart-ad3d0c36-5c87-46f6-b2b6-86dcf49bfbe4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277917552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.277917552
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1759230087
Short name T899
Test name
Test status
Simulation time 4984164200 ps
CPU time 17.52 seconds
Started May 19 01:48:10 PM PDT 24
Finished May 19 01:48:28 PM PDT 24
Peak memory 201968 kb
Host smart-2be86e6e-101d-4407-9b9a-22176339c0ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759230087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1759230087
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1468053658
Short name T856
Test name
Test status
Simulation time 908305504 ps
CPU time 2.49 seconds
Started May 19 01:48:09 PM PDT 24
Finished May 19 01:48:13 PM PDT 24
Peak memory 210100 kb
Host smart-0ec81ec2-e5e0-4701-b8d6-1f3fdd6415f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468053658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1468053658
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3632381167
Short name T836
Test name
Test status
Simulation time 4339505044 ps
CPU time 4.73 seconds
Started May 19 01:48:07 PM PDT 24
Finished May 19 01:48:12 PM PDT 24
Peak memory 201928 kb
Host smart-0abb6297-6861-4ccf-838f-c83c0ae8656f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632381167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3632381167
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3715849593
Short name T843
Test name
Test status
Simulation time 487366587 ps
CPU time 0.86 seconds
Started May 19 01:48:09 PM PDT 24
Finished May 19 01:48:11 PM PDT 24
Peak memory 201744 kb
Host smart-501e0598-3405-4261-a0bf-6e4e62986ce0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715849593 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3715849593
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.15384884
Short name T864
Test name
Test status
Simulation time 609111121 ps
CPU time 1.04 seconds
Started May 19 01:48:06 PM PDT 24
Finished May 19 01:48:08 PM PDT 24
Peak memory 201640 kb
Host smart-86fd48be-0233-4c14-9925-62982c3efe90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15384884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.15384884
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1854873985
Short name T801
Test name
Test status
Simulation time 405732968 ps
CPU time 0.94 seconds
Started May 19 01:48:11 PM PDT 24
Finished May 19 01:48:13 PM PDT 24
Peak memory 201856 kb
Host smart-85ae773f-52fb-4942-b3f2-8e4655f256a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854873985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1854873985
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2459687064
Short name T48
Test name
Test status
Simulation time 4313560248 ps
CPU time 6.8 seconds
Started May 19 01:48:11 PM PDT 24
Finished May 19 01:48:19 PM PDT 24
Peak memory 201976 kb
Host smart-3a1da053-324e-40cd-91ee-d9536b244437
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459687064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2459687064
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2762706654
Short name T825
Test name
Test status
Simulation time 441311209 ps
CPU time 2.05 seconds
Started May 19 01:48:10 PM PDT 24
Finished May 19 01:48:13 PM PDT 24
Peak memory 201984 kb
Host smart-3cfba8d0-a012-48ba-8a42-0115c03fb132
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762706654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2762706654
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.974444843
Short name T818
Test name
Test status
Simulation time 4497206672 ps
CPU time 4.28 seconds
Started May 19 01:48:10 PM PDT 24
Finished May 19 01:48:15 PM PDT 24
Peak memory 201928 kb
Host smart-49f53246-0408-41d1-91a6-e655a8f8b264
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974444843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.974444843
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2123614487
Short name T819
Test name
Test status
Simulation time 1206284578 ps
CPU time 1.14 seconds
Started May 19 01:48:13 PM PDT 24
Finished May 19 01:48:15 PM PDT 24
Peak memory 201928 kb
Host smart-f6c19151-dcc9-4e86-9ec6-434c9f014f40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123614487 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2123614487
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3233459137
Short name T122
Test name
Test status
Simulation time 428622090 ps
CPU time 1.68 seconds
Started May 19 01:48:11 PM PDT 24
Finished May 19 01:48:13 PM PDT 24
Peak memory 201656 kb
Host smart-f626f3fb-731d-4462-be40-1a2d06eef988
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233459137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3233459137
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2533562258
Short name T814
Test name
Test status
Simulation time 316274537 ps
CPU time 0.81 seconds
Started May 19 01:48:10 PM PDT 24
Finished May 19 01:48:12 PM PDT 24
Peak memory 201676 kb
Host smart-790ee039-ab68-4dcb-bf3f-2062ca48c45b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533562258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2533562258
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3816813957
Short name T23
Test name
Test status
Simulation time 4201329513 ps
CPU time 16.57 seconds
Started May 19 01:48:12 PM PDT 24
Finished May 19 01:48:29 PM PDT 24
Peak memory 201924 kb
Host smart-73251e1b-393c-431a-ba2c-3c8753f3a742
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816813957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3816813957
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.269551280
Short name T875
Test name
Test status
Simulation time 461266471 ps
CPU time 2.8 seconds
Started May 19 01:48:11 PM PDT 24
Finished May 19 01:48:15 PM PDT 24
Peak memory 201808 kb
Host smart-733ae61f-9a0d-4f61-9100-e8e391861470
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269551280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.269551280
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1171052946
Short name T64
Test name
Test status
Simulation time 8736933057 ps
CPU time 12.02 seconds
Started May 19 01:48:09 PM PDT 24
Finished May 19 01:48:22 PM PDT 24
Peak memory 202196 kb
Host smart-8d2dfaba-1e4e-4ea2-a1e8-d46408212aa7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171052946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1171052946
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.394558232
Short name T112
Test name
Test status
Simulation time 1010826507 ps
CPU time 2.81 seconds
Started May 19 01:47:50 PM PDT 24
Finished May 19 01:47:53 PM PDT 24
Peak memory 201868 kb
Host smart-f5ee7d23-f8ef-48c5-b5b1-71078602d59d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394558232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.394558232
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.62549731
Short name T115
Test name
Test status
Simulation time 24208133304 ps
CPU time 19.86 seconds
Started May 19 01:47:46 PM PDT 24
Finished May 19 01:48:06 PM PDT 24
Peak memory 201960 kb
Host smart-4ef10d82-83fd-4265-ae0a-48c075690d2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62549731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_ba
sh.62549731
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.232296727
Short name T120
Test name
Test status
Simulation time 694106923 ps
CPU time 1.59 seconds
Started May 19 01:47:46 PM PDT 24
Finished May 19 01:47:48 PM PDT 24
Peak memory 201660 kb
Host smart-1bc58077-c2e5-4379-a3ae-6424c36ba14a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232296727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.232296727
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1495223516
Short name T887
Test name
Test status
Simulation time 447536852 ps
CPU time 1.92 seconds
Started May 19 01:47:43 PM PDT 24
Finished May 19 01:47:46 PM PDT 24
Peak memory 201652 kb
Host smart-37b2c03a-7521-4aa8-a92b-a4595af9e924
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495223516 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1495223516
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3735503288
Short name T872
Test name
Test status
Simulation time 419536738 ps
CPU time 1.88 seconds
Started May 19 01:47:43 PM PDT 24
Finished May 19 01:47:45 PM PDT 24
Peak memory 201684 kb
Host smart-3ff743c3-a13d-4be5-a17c-ff834424f1c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735503288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3735503288
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1176849385
Short name T846
Test name
Test status
Simulation time 499619226 ps
CPU time 1.53 seconds
Started May 19 01:47:38 PM PDT 24
Finished May 19 01:47:40 PM PDT 24
Peak memory 201680 kb
Host smart-e1db4166-d1ff-4240-ac77-2866246e8a40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176849385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1176849385
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3885386056
Short name T49
Test name
Test status
Simulation time 2912298829 ps
CPU time 2.64 seconds
Started May 19 01:47:47 PM PDT 24
Finished May 19 01:47:51 PM PDT 24
Peak memory 201780 kb
Host smart-59f53359-edbf-4cfa-ad77-f7270b126853
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885386056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3885386056
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.153703953
Short name T898
Test name
Test status
Simulation time 308368911 ps
CPU time 1.94 seconds
Started May 19 01:47:39 PM PDT 24
Finished May 19 01:47:41 PM PDT 24
Peak memory 201932 kb
Host smart-f50ad911-a795-4884-9424-14dccb6695c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153703953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.153703953
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2875413230
Short name T847
Test name
Test status
Simulation time 309789673 ps
CPU time 1.38 seconds
Started May 19 01:48:14 PM PDT 24
Finished May 19 01:48:17 PM PDT 24
Peak memory 201536 kb
Host smart-f942a877-c33d-4004-8532-db7e65a2ac7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875413230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2875413230
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.376909038
Short name T802
Test name
Test status
Simulation time 513001928 ps
CPU time 1.78 seconds
Started May 19 01:48:14 PM PDT 24
Finished May 19 01:48:17 PM PDT 24
Peak memory 201660 kb
Host smart-a23d2c97-980b-45f8-8c1d-e1efd73006c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376909038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.376909038
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1553665357
Short name T805
Test name
Test status
Simulation time 307030713 ps
CPU time 1.32 seconds
Started May 19 01:48:15 PM PDT 24
Finished May 19 01:48:17 PM PDT 24
Peak memory 201628 kb
Host smart-8cf44fff-35ed-42ad-80b0-6654bb68b6eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553665357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1553665357
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1339586297
Short name T892
Test name
Test status
Simulation time 541237914 ps
CPU time 0.79 seconds
Started May 19 01:48:12 PM PDT 24
Finished May 19 01:48:13 PM PDT 24
Peak memory 201664 kb
Host smart-ef35c76f-77f8-4a7b-bf22-88064c7255b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339586297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1339586297
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1038168027
Short name T809
Test name
Test status
Simulation time 430898815 ps
CPU time 1.15 seconds
Started May 19 01:48:09 PM PDT 24
Finished May 19 01:48:11 PM PDT 24
Peak memory 201696 kb
Host smart-04bbfb6d-cc1d-4232-a073-a7dd2576b85e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038168027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1038168027
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2913392404
Short name T851
Test name
Test status
Simulation time 343495424 ps
CPU time 0.83 seconds
Started May 19 01:48:08 PM PDT 24
Finished May 19 01:48:09 PM PDT 24
Peak memory 201624 kb
Host smart-0b32e5ad-cbed-4ae4-b636-a6dbf9ea7c38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913392404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2913392404
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1163452434
Short name T909
Test name
Test status
Simulation time 419069985 ps
CPU time 0.71 seconds
Started May 19 01:48:10 PM PDT 24
Finished May 19 01:48:12 PM PDT 24
Peak memory 201928 kb
Host smart-bfa7d50b-0f7b-4b8c-84e7-28a95928d07e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163452434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1163452434
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1228600300
Short name T804
Test name
Test status
Simulation time 354191175 ps
CPU time 0.84 seconds
Started May 19 01:48:14 PM PDT 24
Finished May 19 01:48:16 PM PDT 24
Peak memory 201540 kb
Host smart-e3bbf6bc-06a9-417b-9db0-7481bd574e40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228600300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1228600300
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1461224772
Short name T807
Test name
Test status
Simulation time 479833494 ps
CPU time 0.92 seconds
Started May 19 01:48:10 PM PDT 24
Finished May 19 01:48:11 PM PDT 24
Peak memory 201624 kb
Host smart-8e724ce3-505d-44a1-8644-fc6703f36a53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461224772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1461224772
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.585580049
Short name T821
Test name
Test status
Simulation time 489829951 ps
CPU time 1.76 seconds
Started May 19 01:48:15 PM PDT 24
Finished May 19 01:48:17 PM PDT 24
Peak memory 201624 kb
Host smart-b3b3908c-0e0e-49b9-81bf-4a442fa792ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585580049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.585580049
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2277903103
Short name T869
Test name
Test status
Simulation time 714261514 ps
CPU time 2.57 seconds
Started May 19 01:47:43 PM PDT 24
Finished May 19 01:47:46 PM PDT 24
Peak memory 201912 kb
Host smart-9b50c73f-5f34-41e3-bee7-7f09c4fbdb64
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277903103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2277903103
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1136571985
Short name T838
Test name
Test status
Simulation time 26776493090 ps
CPU time 102.38 seconds
Started May 19 01:47:43 PM PDT 24
Finished May 19 01:49:26 PM PDT 24
Peak memory 201904 kb
Host smart-8513669a-7ac4-4245-8a0c-bb2759d7d386
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136571985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1136571985
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.4020488951
Short name T108
Test name
Test status
Simulation time 680533018 ps
CPU time 2.24 seconds
Started May 19 01:47:44 PM PDT 24
Finished May 19 01:47:47 PM PDT 24
Peak memory 201664 kb
Host smart-f23a1457-6cf3-4822-adaa-738974a749c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020488951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.4020488951
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1915763674
Short name T890
Test name
Test status
Simulation time 486612583 ps
CPU time 1.26 seconds
Started May 19 01:47:43 PM PDT 24
Finished May 19 01:47:45 PM PDT 24
Peak memory 201764 kb
Host smart-1ceb416b-2109-43b7-92d8-7286847a23cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915763674 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1915763674
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.890210929
Short name T906
Test name
Test status
Simulation time 397997103 ps
CPU time 1.03 seconds
Started May 19 01:47:43 PM PDT 24
Finished May 19 01:47:45 PM PDT 24
Peak memory 201648 kb
Host smart-9a718c2f-c6bd-42af-be35-258306002c25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890210929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.890210929
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.943573500
Short name T888
Test name
Test status
Simulation time 448733896 ps
CPU time 1.71 seconds
Started May 19 01:47:42 PM PDT 24
Finished May 19 01:47:45 PM PDT 24
Peak memory 201704 kb
Host smart-e88d9d73-b0cf-4d70-a64c-66301f64341a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943573500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.943573500
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.590508703
Short name T828
Test name
Test status
Simulation time 2812377727 ps
CPU time 3.81 seconds
Started May 19 01:47:42 PM PDT 24
Finished May 19 01:47:47 PM PDT 24
Peak memory 201964 kb
Host smart-46d48925-e083-4b71-9d73-3b88b57d7aa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590508703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ct
rl_same_csr_outstanding.590508703
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2307605673
Short name T860
Test name
Test status
Simulation time 600826298 ps
CPU time 3.48 seconds
Started May 19 01:47:42 PM PDT 24
Finished May 19 01:47:46 PM PDT 24
Peak memory 210136 kb
Host smart-4ecaee78-9cc5-4de1-8a94-eff13705f379
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307605673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2307605673
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3442821450
Short name T50
Test name
Test status
Simulation time 4092420511 ps
CPU time 10.24 seconds
Started May 19 01:47:44 PM PDT 24
Finished May 19 01:47:55 PM PDT 24
Peak memory 202000 kb
Host smart-a3a85714-118b-4a7c-8f26-c35c79497015
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442821450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3442821450
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3140579874
Short name T829
Test name
Test status
Simulation time 356446292 ps
CPU time 1.52 seconds
Started May 19 01:48:10 PM PDT 24
Finished May 19 01:48:13 PM PDT 24
Peak memory 201660 kb
Host smart-40345318-eaca-4fe2-8171-152acae25f5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140579874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3140579874
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3689033731
Short name T879
Test name
Test status
Simulation time 337058123 ps
CPU time 0.79 seconds
Started May 19 01:48:09 PM PDT 24
Finished May 19 01:48:11 PM PDT 24
Peak memory 201640 kb
Host smart-29728b9c-f1a6-4575-be0a-b6b9b131b7bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689033731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3689033731
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.300688739
Short name T854
Test name
Test status
Simulation time 360182846 ps
CPU time 0.88 seconds
Started May 19 01:48:23 PM PDT 24
Finished May 19 01:48:25 PM PDT 24
Peak memory 201680 kb
Host smart-f06e21d2-d751-4e05-9838-40a9c2cfe86d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300688739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.300688739
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.339228984
Short name T889
Test name
Test status
Simulation time 444637789 ps
CPU time 1.61 seconds
Started May 19 01:48:13 PM PDT 24
Finished May 19 01:48:15 PM PDT 24
Peak memory 201676 kb
Host smart-1c683a89-4fd7-402b-90e7-8abfd5b87f97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339228984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.339228984
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3414310283
Short name T901
Test name
Test status
Simulation time 425285482 ps
CPU time 1.14 seconds
Started May 19 01:48:16 PM PDT 24
Finished May 19 01:48:18 PM PDT 24
Peak memory 201852 kb
Host smart-6d4b6dbd-8417-462f-b1b1-4eed7c4f44d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414310283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3414310283
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1149752483
Short name T896
Test name
Test status
Simulation time 400735375 ps
CPU time 1.56 seconds
Started May 19 01:48:14 PM PDT 24
Finished May 19 01:48:17 PM PDT 24
Peak memory 201644 kb
Host smart-c68b9bce-aeec-4774-b40e-fe22c7df02ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149752483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1149752483
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3886877198
Short name T862
Test name
Test status
Simulation time 380598191 ps
CPU time 1.58 seconds
Started May 19 01:48:28 PM PDT 24
Finished May 19 01:48:31 PM PDT 24
Peak memory 201644 kb
Host smart-72fc14cb-0be1-4fb5-bdb8-728f78cd84c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886877198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3886877198
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1959438543
Short name T876
Test name
Test status
Simulation time 442702255 ps
CPU time 1.72 seconds
Started May 19 01:48:17 PM PDT 24
Finished May 19 01:48:20 PM PDT 24
Peak memory 201684 kb
Host smart-aa738906-c6c4-4139-8b20-fe01ceb37faf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959438543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1959438543
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3262641215
Short name T813
Test name
Test status
Simulation time 465099215 ps
CPU time 1.21 seconds
Started May 19 01:48:28 PM PDT 24
Finished May 19 01:48:30 PM PDT 24
Peak memory 201668 kb
Host smart-4094ceb2-fb59-40f1-b43b-f252065204a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262641215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3262641215
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2269554268
Short name T891
Test name
Test status
Simulation time 355872285 ps
CPU time 1.57 seconds
Started May 19 01:48:18 PM PDT 24
Finished May 19 01:48:20 PM PDT 24
Peak memory 201640 kb
Host smart-149866e4-f351-434e-90f1-02a18301f7b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269554268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2269554268
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4132247769
Short name T885
Test name
Test status
Simulation time 759603929 ps
CPU time 3.15 seconds
Started May 19 01:47:47 PM PDT 24
Finished May 19 01:47:50 PM PDT 24
Peak memory 201900 kb
Host smart-b16944cc-9608-4e21-9a14-a5deb58916e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132247769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.4132247769
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1779533708
Short name T111
Test name
Test status
Simulation time 49486710758 ps
CPU time 157.43 seconds
Started May 19 01:47:49 PM PDT 24
Finished May 19 01:50:28 PM PDT 24
Peak memory 201900 kb
Host smart-ded2f8f5-b19e-4f85-bc89-ef1cda775e5d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779533708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1779533708
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.488270196
Short name T866
Test name
Test status
Simulation time 1095747777 ps
CPU time 3.2 seconds
Started May 19 01:47:49 PM PDT 24
Finished May 19 01:47:53 PM PDT 24
Peak memory 201640 kb
Host smart-32733ff7-f323-4c49-9cec-18a2065f9749
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488270196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.488270196
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2556805296
Short name T77
Test name
Test status
Simulation time 425338256 ps
CPU time 1.04 seconds
Started May 19 01:47:54 PM PDT 24
Finished May 19 01:47:57 PM PDT 24
Peak memory 201736 kb
Host smart-75c2b3be-8cb8-4aa7-8143-feee4f89efbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556805296 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2556805296
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3481787338
Short name T827
Test name
Test status
Simulation time 560174721 ps
CPU time 1.12 seconds
Started May 19 01:47:49 PM PDT 24
Finished May 19 01:47:50 PM PDT 24
Peak memory 201684 kb
Host smart-7c21c27b-bf0e-41c6-ad05-9f600838401c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481787338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3481787338
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2170487926
Short name T815
Test name
Test status
Simulation time 487235678 ps
CPU time 0.78 seconds
Started May 19 01:47:41 PM PDT 24
Finished May 19 01:47:42 PM PDT 24
Peak memory 201856 kb
Host smart-4bbe1427-fe10-46a9-be5b-091d5de6954d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170487926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2170487926
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1956654894
Short name T824
Test name
Test status
Simulation time 2372762837 ps
CPU time 3.63 seconds
Started May 19 01:47:50 PM PDT 24
Finished May 19 01:47:54 PM PDT 24
Peak memory 201712 kb
Host smart-6300327a-744d-4bd3-a54f-1e17ff799e5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956654894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1956654894
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1984901580
Short name T66
Test name
Test status
Simulation time 2955326392 ps
CPU time 3.21 seconds
Started May 19 01:47:48 PM PDT 24
Finished May 19 01:47:52 PM PDT 24
Peak memory 211488 kb
Host smart-5c91477c-3cc7-4a0f-9414-6052dafa250a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984901580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1984901580
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1002724946
Short name T884
Test name
Test status
Simulation time 4311372806 ps
CPU time 6.52 seconds
Started May 19 01:47:45 PM PDT 24
Finished May 19 01:47:52 PM PDT 24
Peak memory 201900 kb
Host smart-73fc09df-ecb0-490b-9565-6fcd92e7e495
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002724946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1002724946
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2810322453
Short name T911
Test name
Test status
Simulation time 455086388 ps
CPU time 1.68 seconds
Started May 19 01:48:14 PM PDT 24
Finished May 19 01:48:17 PM PDT 24
Peak memory 201664 kb
Host smart-0280f9eb-48a6-42d0-b248-29d8d12ce443
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810322453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2810322453
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.4190103564
Short name T858
Test name
Test status
Simulation time 436385388 ps
CPU time 0.82 seconds
Started May 19 01:48:22 PM PDT 24
Finished May 19 01:48:24 PM PDT 24
Peak memory 201684 kb
Host smart-79c93536-80f7-4a9e-9a97-6aaae8e48f1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190103564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.4190103564
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.173509805
Short name T849
Test name
Test status
Simulation time 503416650 ps
CPU time 1.85 seconds
Started May 19 01:48:13 PM PDT 24
Finished May 19 01:48:16 PM PDT 24
Peak memory 201668 kb
Host smart-18dd27d2-d2eb-4710-b7b7-8f9d6e156650
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173509805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.173509805
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.18381583
Short name T820
Test name
Test status
Simulation time 385079493 ps
CPU time 0.86 seconds
Started May 19 01:48:23 PM PDT 24
Finished May 19 01:48:25 PM PDT 24
Peak memory 201668 kb
Host smart-dbbae8cf-21a8-4fd3-9d32-e9dfe1f36ad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18381583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.18381583
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1062908768
Short name T823
Test name
Test status
Simulation time 341906017 ps
CPU time 0.82 seconds
Started May 19 01:48:14 PM PDT 24
Finished May 19 01:48:15 PM PDT 24
Peak memory 201688 kb
Host smart-35fb2142-311e-4080-81b2-af8e81286324
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062908768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1062908768
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2811221988
Short name T810
Test name
Test status
Simulation time 325212172 ps
CPU time 0.8 seconds
Started May 19 01:48:15 PM PDT 24
Finished May 19 01:48:16 PM PDT 24
Peak memory 201644 kb
Host smart-1797e97d-814e-4bd5-8b60-433a52871a4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811221988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2811221988
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2983300990
Short name T800
Test name
Test status
Simulation time 499977222 ps
CPU time 1.85 seconds
Started May 19 01:48:23 PM PDT 24
Finished May 19 01:48:26 PM PDT 24
Peak memory 201716 kb
Host smart-df285613-6737-427a-95b7-c4c6112fa512
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983300990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.2983300990
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2115012958
Short name T902
Test name
Test status
Simulation time 316415851 ps
CPU time 1 seconds
Started May 19 01:48:14 PM PDT 24
Finished May 19 01:48:17 PM PDT 24
Peak memory 201656 kb
Host smart-968d1ae2-dafb-496b-a238-ec34f731d659
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115012958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2115012958
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3128397451
Short name T816
Test name
Test status
Simulation time 429992675 ps
CPU time 1.2 seconds
Started May 19 01:48:19 PM PDT 24
Finished May 19 01:48:21 PM PDT 24
Peak memory 201684 kb
Host smart-3d861d23-e5a9-4b76-be19-3173b8d378ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128397451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3128397451
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1673772448
Short name T915
Test name
Test status
Simulation time 580497915 ps
CPU time 0.87 seconds
Started May 19 01:48:22 PM PDT 24
Finished May 19 01:48:24 PM PDT 24
Peak memory 201680 kb
Host smart-84c1e144-5f2f-4511-9c32-b2be6dc1e3d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673772448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.1673772448
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1946355159
Short name T903
Test name
Test status
Simulation time 600686903 ps
CPU time 1.11 seconds
Started May 19 01:47:53 PM PDT 24
Finished May 19 01:47:55 PM PDT 24
Peak memory 201716 kb
Host smart-40866cdc-41e0-40c8-b840-ce92def0a6d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946355159 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1946355159
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3531977994
Short name T110
Test name
Test status
Simulation time 442090161 ps
CPU time 1.07 seconds
Started May 19 01:47:50 PM PDT 24
Finished May 19 01:47:52 PM PDT 24
Peak memory 201700 kb
Host smart-cea02027-e9f5-476b-8d6e-fe05f50e7930
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531977994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3531977994
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.4082022584
Short name T868
Test name
Test status
Simulation time 414692287 ps
CPU time 1.19 seconds
Started May 19 01:47:53 PM PDT 24
Finished May 19 01:47:55 PM PDT 24
Peak memory 201644 kb
Host smart-de10d596-562d-4ab9-b9f3-fc231ec75a74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082022584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.4082022584
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1116246743
Short name T817
Test name
Test status
Simulation time 2660106614 ps
CPU time 7.17 seconds
Started May 19 01:47:46 PM PDT 24
Finished May 19 01:47:54 PM PDT 24
Peak memory 201700 kb
Host smart-fc89c080-96af-478a-9d23-c786fa4b63a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116246743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1116246743
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1758836875
Short name T65
Test name
Test status
Simulation time 1590337150 ps
CPU time 2.58 seconds
Started May 19 01:47:48 PM PDT 24
Finished May 19 01:47:51 PM PDT 24
Peak memory 217788 kb
Host smart-6926d67c-dbd8-4e10-a8a7-f0861a29aa1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758836875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1758836875
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1058426138
Short name T850
Test name
Test status
Simulation time 7890315051 ps
CPU time 7.31 seconds
Started May 19 01:47:47 PM PDT 24
Finished May 19 01:47:55 PM PDT 24
Peak memory 201904 kb
Host smart-4d5eb0da-538a-449b-bcd1-904deac87304
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058426138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1058426138
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1251248734
Short name T67
Test name
Test status
Simulation time 461877892 ps
CPU time 1.3 seconds
Started May 19 01:47:49 PM PDT 24
Finished May 19 01:47:52 PM PDT 24
Peak memory 201736 kb
Host smart-32531e66-963c-498a-9c20-64be411b3619
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251248734 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1251248734
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3978729398
Short name T117
Test name
Test status
Simulation time 577994220 ps
CPU time 0.98 seconds
Started May 19 01:47:49 PM PDT 24
Finished May 19 01:47:51 PM PDT 24
Peak memory 201636 kb
Host smart-67d1f89f-f1f2-488c-945d-6456f2818f28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978729398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3978729398
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.780734579
Short name T877
Test name
Test status
Simulation time 389451337 ps
CPU time 1.5 seconds
Started May 19 01:47:48 PM PDT 24
Finished May 19 01:47:50 PM PDT 24
Peak memory 201640 kb
Host smart-1e034f5f-bd9f-4d93-a0ab-9196c69bd096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780734579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.780734579
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.584674116
Short name T917
Test name
Test status
Simulation time 4513605445 ps
CPU time 11.96 seconds
Started May 19 01:47:49 PM PDT 24
Finished May 19 01:48:02 PM PDT 24
Peak memory 201912 kb
Host smart-edab813e-58b3-4009-a92b-fdadd1ff8798
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584674116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.584674116
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1972394222
Short name T61
Test name
Test status
Simulation time 562815103 ps
CPU time 2 seconds
Started May 19 01:47:51 PM PDT 24
Finished May 19 01:47:53 PM PDT 24
Peak memory 202016 kb
Host smart-eddb8d35-7ae5-4fd4-ad99-122881506756
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972394222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1972394222
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2788085895
Short name T900
Test name
Test status
Simulation time 5305494257 ps
CPU time 2.67 seconds
Started May 19 01:47:50 PM PDT 24
Finished May 19 01:47:53 PM PDT 24
Peak memory 201932 kb
Host smart-cb894ae4-85f7-435f-b64f-82ed284ab20c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788085895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2788085895
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2715722111
Short name T913
Test name
Test status
Simulation time 567721502 ps
CPU time 2.05 seconds
Started May 19 01:47:58 PM PDT 24
Finished May 19 01:48:01 PM PDT 24
Peak memory 201752 kb
Host smart-3e924313-8ecd-4662-8109-32715a215c4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715722111 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2715722111
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3365545033
Short name T871
Test name
Test status
Simulation time 329791300 ps
CPU time 1.51 seconds
Started May 19 01:47:55 PM PDT 24
Finished May 19 01:47:57 PM PDT 24
Peak memory 201664 kb
Host smart-40761ad8-21dc-479a-85e9-6a773a9f42ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365545033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3365545033
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.322592094
Short name T812
Test name
Test status
Simulation time 365854771 ps
CPU time 0.8 seconds
Started May 19 01:47:55 PM PDT 24
Finished May 19 01:47:57 PM PDT 24
Peak memory 201604 kb
Host smart-ca4ae3e4-11f3-4123-a242-06c090369cc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322592094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.322592094
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1511125509
Short name T124
Test name
Test status
Simulation time 2817656174 ps
CPU time 9.23 seconds
Started May 19 01:47:54 PM PDT 24
Finished May 19 01:48:04 PM PDT 24
Peak memory 202008 kb
Host smart-47e5dd71-3178-43b6-8913-c895682007db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511125509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1511125509
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3456566786
Short name T873
Test name
Test status
Simulation time 307768670 ps
CPU time 2.75 seconds
Started May 19 01:47:54 PM PDT 24
Finished May 19 01:47:58 PM PDT 24
Peak memory 218284 kb
Host smart-086d82b1-aff5-4c6f-ba00-f4d71ba4f145
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456566786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3456566786
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.99215371
Short name T52
Test name
Test status
Simulation time 4672580277 ps
CPU time 12.75 seconds
Started May 19 01:47:51 PM PDT 24
Finished May 19 01:48:05 PM PDT 24
Peak memory 201936 kb
Host smart-2f67a9a5-5d44-410d-99fa-89b7ae64b6e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99215371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_intg
_err.99215371
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.4156755338
Short name T878
Test name
Test status
Simulation time 541861935 ps
CPU time 1.21 seconds
Started May 19 01:47:55 PM PDT 24
Finished May 19 01:47:57 PM PDT 24
Peak memory 201680 kb
Host smart-16940cdb-27fb-4b2a-9e57-4e491a69971f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156755338 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.4156755338
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3901749586
Short name T855
Test name
Test status
Simulation time 686355187 ps
CPU time 0.89 seconds
Started May 19 01:47:54 PM PDT 24
Finished May 19 01:47:56 PM PDT 24
Peak memory 201644 kb
Host smart-b6064538-7742-4110-ac29-b62060eb9f87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901749586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3901749586
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1513566341
Short name T808
Test name
Test status
Simulation time 466826299 ps
CPU time 1.23 seconds
Started May 19 01:47:55 PM PDT 24
Finished May 19 01:47:57 PM PDT 24
Peak memory 201656 kb
Host smart-daa3925d-5a70-41e6-a6ca-005b1d24a50c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513566341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1513566341
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.650888898
Short name T826
Test name
Test status
Simulation time 2854067161 ps
CPU time 2.24 seconds
Started May 19 01:47:54 PM PDT 24
Finished May 19 01:47:57 PM PDT 24
Peak memory 201728 kb
Host smart-c90b3148-60a8-4f4e-a768-84256c1aa4dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650888898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.650888898
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.447533441
Short name T834
Test name
Test status
Simulation time 613187869 ps
CPU time 4.13 seconds
Started May 19 01:47:55 PM PDT 24
Finished May 19 01:48:00 PM PDT 24
Peak memory 217872 kb
Host smart-7bc7896e-bc4c-4d3d-993e-ee00aa44ea6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447533441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.447533441
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2162949539
Short name T363
Test name
Test status
Simulation time 4251678730 ps
CPU time 11.43 seconds
Started May 19 01:47:52 PM PDT 24
Finished May 19 01:48:04 PM PDT 24
Peak memory 201968 kb
Host smart-e05ef5cc-001e-4f7b-9763-b41ef4e9b27c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162949539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2162949539
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2976752343
Short name T905
Test name
Test status
Simulation time 599616659 ps
CPU time 1.18 seconds
Started May 19 01:47:55 PM PDT 24
Finished May 19 01:47:57 PM PDT 24
Peak memory 201696 kb
Host smart-451e73c0-95d3-488f-a64e-ccf49a3f457b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976752343 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2976752343
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2510152262
Short name T119
Test name
Test status
Simulation time 404691964 ps
CPU time 1.72 seconds
Started May 19 01:47:51 PM PDT 24
Finished May 19 01:47:53 PM PDT 24
Peak memory 201656 kb
Host smart-c5e84c14-6254-4d84-904d-485a5d7d1cac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510152262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2510152262
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2769188200
Short name T798
Test name
Test status
Simulation time 490028815 ps
CPU time 0.77 seconds
Started May 19 01:47:53 PM PDT 24
Finished May 19 01:47:54 PM PDT 24
Peak memory 201668 kb
Host smart-73fdfd25-8783-426a-8140-94d62e9b7543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769188200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2769188200
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1906608548
Short name T861
Test name
Test status
Simulation time 4257535139 ps
CPU time 8 seconds
Started May 19 01:47:53 PM PDT 24
Finished May 19 01:48:01 PM PDT 24
Peak memory 202004 kb
Host smart-7905af50-45b1-4ce5-84d8-97d4188d41a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906608548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1906608548
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.307254017
Short name T840
Test name
Test status
Simulation time 405473448 ps
CPU time 2.28 seconds
Started May 19 01:47:54 PM PDT 24
Finished May 19 01:47:57 PM PDT 24
Peak memory 201936 kb
Host smart-0072516b-98ea-4868-9752-0e85dd6403e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307254017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.307254017
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3704189484
Short name T907
Test name
Test status
Simulation time 4369870018 ps
CPU time 6.77 seconds
Started May 19 01:47:54 PM PDT 24
Finished May 19 01:48:02 PM PDT 24
Peak memory 201928 kb
Host smart-3ee4e973-e723-4d03-80c8-87fd3b1bbf4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704189484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3704189484
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.19067563
Short name T102
Test name
Test status
Simulation time 400203519 ps
CPU time 1.04 seconds
Started May 19 01:33:31 PM PDT 24
Finished May 19 01:33:34 PM PDT 24
Peak memory 201796 kb
Host smart-5f9d8586-c22d-48ec-b8c4-442dc9a72393
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19067563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.19067563
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2678200129
Short name T783
Test name
Test status
Simulation time 164665845647 ps
CPU time 78.05 seconds
Started May 19 01:33:29 PM PDT 24
Finished May 19 01:34:50 PM PDT 24
Peak memory 201788 kb
Host smart-f72f5cbb-eef1-494c-ace4-00de2d79ba54
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678200129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2678200129
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.699816432
Short name T139
Test name
Test status
Simulation time 371667046449 ps
CPU time 796.13 seconds
Started May 19 01:33:25 PM PDT 24
Finished May 19 01:46:46 PM PDT 24
Peak memory 201740 kb
Host smart-b34f36c6-27a0-422f-bdb6-872357b09876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699816432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.699816432
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3475240084
Short name T157
Test name
Test status
Simulation time 164397628015 ps
CPU time 115.48 seconds
Started May 19 01:33:25 PM PDT 24
Finished May 19 01:35:25 PM PDT 24
Peak memory 201860 kb
Host smart-0a164252-c610-46cc-8b3c-5984dc617294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475240084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3475240084
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3275739443
Short name T757
Test name
Test status
Simulation time 166428478292 ps
CPU time 106.85 seconds
Started May 19 01:33:23 PM PDT 24
Finished May 19 01:35:12 PM PDT 24
Peak memory 201752 kb
Host smart-584881a4-4564-4bd5-8201-6503a8474213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275739443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3275739443
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3908280218
Short name T772
Test name
Test status
Simulation time 166508709060 ps
CPU time 410.99 seconds
Started May 19 01:33:26 PM PDT 24
Finished May 19 01:40:21 PM PDT 24
Peak memory 201516 kb
Host smart-4a169e47-9973-4747-9eb5-9fc35e300747
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908280218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3908280218
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3000175817
Short name T678
Test name
Test status
Simulation time 350552603697 ps
CPU time 439.8 seconds
Started May 19 01:33:33 PM PDT 24
Finished May 19 01:40:55 PM PDT 24
Peak memory 201788 kb
Host smart-c7e9926a-80df-4e60-814b-d20af5756a0b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000175817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3000175817
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3986668450
Short name T718
Test name
Test status
Simulation time 403801637214 ps
CPU time 223.77 seconds
Started May 19 01:33:30 PM PDT 24
Finished May 19 01:37:16 PM PDT 24
Peak memory 201780 kb
Host smart-e7dbb295-b821-463d-8c00-c1b5c5bdfe08
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986668450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3986668450
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.512231734
Short name T679
Test name
Test status
Simulation time 44217095067 ps
CPU time 27.94 seconds
Started May 19 01:33:31 PM PDT 24
Finished May 19 01:34:01 PM PDT 24
Peak memory 201600 kb
Host smart-e9eddfa6-255f-43cc-96bb-8d2215966b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512231734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.512231734
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.806544078
Short name T548
Test name
Test status
Simulation time 5356759690 ps
CPU time 15.67 seconds
Started May 19 01:33:23 PM PDT 24
Finished May 19 01:33:42 PM PDT 24
Peak memory 201632 kb
Host smart-f45f94a0-eccb-4a2c-a4e8-0337e1eabc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806544078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.806544078
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1048964519
Short name T497
Test name
Test status
Simulation time 5761125755 ps
CPU time 15.01 seconds
Started May 19 01:33:27 PM PDT 24
Finished May 19 01:33:46 PM PDT 24
Peak memory 201632 kb
Host smart-12e69756-06d3-4a6b-a1a7-12f48c818652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048964519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1048964519
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.519071033
Short name T34
Test name
Test status
Simulation time 170181715807 ps
CPU time 205.76 seconds
Started May 19 01:33:26 PM PDT 24
Finished May 19 01:36:56 PM PDT 24
Peak memory 201764 kb
Host smart-01ace0f3-4b0a-4cfb-8155-ef91d72ed795
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519071033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.519071033
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.999694971
Short name T512
Test name
Test status
Simulation time 96681933002 ps
CPU time 185.75 seconds
Started May 19 01:33:26 PM PDT 24
Finished May 19 01:36:36 PM PDT 24
Peak memory 217444 kb
Host smart-e91f58d5-e930-46cf-be73-8f8f853f8ef0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999694971 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.999694971
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.175767119
Short name T743
Test name
Test status
Simulation time 453122245 ps
CPU time 0.9 seconds
Started May 19 01:33:32 PM PDT 24
Finished May 19 01:33:35 PM PDT 24
Peak memory 201516 kb
Host smart-de76d4f8-7929-46f8-aaf5-0e96a7f7d6b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175767119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.175767119
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2325325158
Short name T148
Test name
Test status
Simulation time 162465492104 ps
CPU time 370.17 seconds
Started May 19 01:33:24 PM PDT 24
Finished May 19 01:39:38 PM PDT 24
Peak memory 201900 kb
Host smart-e02d6a7d-2ea4-4729-8956-6b517fda8600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325325158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2325325158
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2129202939
Short name T677
Test name
Test status
Simulation time 162387170267 ps
CPU time 197.56 seconds
Started May 19 01:33:28 PM PDT 24
Finished May 19 01:36:49 PM PDT 24
Peak memory 201808 kb
Host smart-ec7b8f81-df59-4474-ac93-2bf58cb3f7a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129202939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2129202939
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3689603425
Short name T546
Test name
Test status
Simulation time 490503664700 ps
CPU time 173.72 seconds
Started May 19 01:33:30 PM PDT 24
Finished May 19 01:36:26 PM PDT 24
Peak memory 201868 kb
Host smart-24294ee4-90dc-447d-89c7-b670d110b715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689603425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3689603425
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.17388082
Short name T435
Test name
Test status
Simulation time 158699961620 ps
CPU time 99.88 seconds
Started May 19 01:33:23 PM PDT 24
Finished May 19 01:35:07 PM PDT 24
Peak memory 201824 kb
Host smart-1e2910f0-a508-4b4f-bd19-4f46eaa7f691
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=17388082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed.17388082
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1781273803
Short name T347
Test name
Test status
Simulation time 181132442761 ps
CPU time 429.85 seconds
Started May 19 01:33:25 PM PDT 24
Finished May 19 01:40:39 PM PDT 24
Peak memory 201800 kb
Host smart-bfa49f47-22bc-4064-a003-2fe5b373233d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781273803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1781273803
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3572660166
Short name T611
Test name
Test status
Simulation time 202709901468 ps
CPU time 470.85 seconds
Started May 19 01:33:26 PM PDT 24
Finished May 19 01:41:21 PM PDT 24
Peak memory 201864 kb
Host smart-5db9bf9a-ec5d-402d-a211-b8debd62a34e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572660166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3572660166
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1346618416
Short name T469
Test name
Test status
Simulation time 107252485610 ps
CPU time 373.42 seconds
Started May 19 01:33:32 PM PDT 24
Finished May 19 01:39:47 PM PDT 24
Peak memory 202136 kb
Host smart-661cefd8-18cb-447e-b7d7-e735223d6bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346618416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1346618416
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3330920980
Short name T446
Test name
Test status
Simulation time 25101837742 ps
CPU time 15.68 seconds
Started May 19 01:33:40 PM PDT 24
Finished May 19 01:33:57 PM PDT 24
Peak memory 201644 kb
Host smart-24d6328c-b642-4fb1-a6d1-ad5dc492c9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330920980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3330920980
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3901092918
Short name T529
Test name
Test status
Simulation time 3250047286 ps
CPU time 2.61 seconds
Started May 19 01:33:47 PM PDT 24
Finished May 19 01:33:50 PM PDT 24
Peak memory 201524 kb
Host smart-579d9f76-3f26-4589-bdec-1dd48ea766a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901092918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3901092918
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.240934720
Short name T69
Test name
Test status
Simulation time 4849158116 ps
CPU time 3.49 seconds
Started May 19 01:33:31 PM PDT 24
Finished May 19 01:33:37 PM PDT 24
Peak memory 217456 kb
Host smart-5cbfd612-756c-47a7-8ccc-cdf8f9e85d6c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240934720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.240934720
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3415923602
Short name T418
Test name
Test status
Simulation time 6005843089 ps
CPU time 4.32 seconds
Started May 19 01:33:23 PM PDT 24
Finished May 19 01:33:31 PM PDT 24
Peak memory 201872 kb
Host smart-f5fbad3c-eb23-4a5d-bbc8-7d387d428f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415923602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3415923602
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.4257054561
Short name T292
Test name
Test status
Simulation time 171121635838 ps
CPU time 309.48 seconds
Started May 19 01:33:29 PM PDT 24
Finished May 19 01:38:41 PM PDT 24
Peak memory 201860 kb
Host smart-68b2942d-3d2c-4395-b0a1-279637a4e005
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257054561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
4257054561
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.433621568
Short name T768
Test name
Test status
Simulation time 205495799377 ps
CPU time 123.29 seconds
Started May 19 01:33:44 PM PDT 24
Finished May 19 01:35:48 PM PDT 24
Peak memory 201876 kb
Host smart-51d0440f-52f1-4035-bc42-68e89e89398a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433621568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati
ng.433621568
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1013250871
Short name T354
Test name
Test status
Simulation time 351812034404 ps
CPU time 781.43 seconds
Started May 19 01:33:40 PM PDT 24
Finished May 19 01:46:43 PM PDT 24
Peak memory 201716 kb
Host smart-6e52f99e-6d86-45fe-bce2-24d3aba995fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013250871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1013250871
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2091131843
Short name T770
Test name
Test status
Simulation time 492203624664 ps
CPU time 295.06 seconds
Started May 19 01:33:51 PM PDT 24
Finished May 19 01:38:48 PM PDT 24
Peak memory 201800 kb
Host smart-1c0f0507-4801-434e-a9ad-85d2cf382bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091131843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2091131843
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.179257548
Short name T486
Test name
Test status
Simulation time 495166818831 ps
CPU time 1225.81 seconds
Started May 19 01:33:57 PM PDT 24
Finished May 19 01:54:23 PM PDT 24
Peak memory 201788 kb
Host smart-f5a051e8-6af6-4480-b04c-53ea6da5e501
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=179257548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.179257548
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.631799543
Short name T750
Test name
Test status
Simulation time 325856279008 ps
CPU time 357.17 seconds
Started May 19 01:34:03 PM PDT 24
Finished May 19 01:40:02 PM PDT 24
Peak memory 201888 kb
Host smart-d63224a4-d2fd-4f46-bbfd-42c768f9b3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631799543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.631799543
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.4277262321
Short name T149
Test name
Test status
Simulation time 330343937700 ps
CPU time 186.9 seconds
Started May 19 01:33:51 PM PDT 24
Finished May 19 01:36:59 PM PDT 24
Peak memory 201772 kb
Host smart-f4a1e98d-66c6-4578-896c-c251c4165410
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277262321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.4277262321
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.863129045
Short name T730
Test name
Test status
Simulation time 215833241057 ps
CPU time 498.5 seconds
Started May 19 01:33:51 PM PDT 24
Finished May 19 01:42:11 PM PDT 24
Peak memory 201808 kb
Host smart-17eb7761-84b2-49d6-9771-f7e008edc02b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863129045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.863129045
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1095226012
Short name T654
Test name
Test status
Simulation time 110675692516 ps
CPU time 430.12 seconds
Started May 19 01:33:46 PM PDT 24
Finished May 19 01:40:57 PM PDT 24
Peak memory 202140 kb
Host smart-7e7cf8f7-d445-4ddf-839f-c6b4ff9d8885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095226012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1095226012
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1991885998
Short name T8
Test name
Test status
Simulation time 44991111180 ps
CPU time 86.53 seconds
Started May 19 01:33:51 PM PDT 24
Finished May 19 01:35:19 PM PDT 24
Peak memory 201660 kb
Host smart-d33d338a-da2a-4144-8f15-2c6f9326979b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991885998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1991885998
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2862321530
Short name T164
Test name
Test status
Simulation time 2721324417 ps
CPU time 2.16 seconds
Started May 19 01:33:51 PM PDT 24
Finished May 19 01:33:55 PM PDT 24
Peak memory 201556 kb
Host smart-fa2d3dd3-5b39-412b-9973-205094d5edf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862321530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2862321530
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3439129157
Short name T738
Test name
Test status
Simulation time 6052784890 ps
CPU time 4.47 seconds
Started May 19 01:33:42 PM PDT 24
Finished May 19 01:33:47 PM PDT 24
Peak memory 201540 kb
Host smart-3986a42b-9a39-4161-a1b6-3b5d01c6c35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439129157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3439129157
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1009984601
Short name T705
Test name
Test status
Simulation time 326263384415 ps
CPU time 805.27 seconds
Started May 19 01:34:06 PM PDT 24
Finished May 19 01:47:33 PM PDT 24
Peak memory 210376 kb
Host smart-8b16dacb-cef0-4ef6-b031-a81c3ab5d33e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009984601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1009984601
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3634236423
Short name T522
Test name
Test status
Simulation time 18307474700 ps
CPU time 45.81 seconds
Started May 19 01:33:50 PM PDT 24
Finished May 19 01:34:36 PM PDT 24
Peak memory 210184 kb
Host smart-9ac5b35f-0bfc-4359-874c-3dfa59505e90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634236423 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3634236423
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.930124753
Short name T542
Test name
Test status
Simulation time 517313809 ps
CPU time 1.25 seconds
Started May 19 01:34:03 PM PDT 24
Finished May 19 01:34:06 PM PDT 24
Peak memory 201460 kb
Host smart-46087873-e963-4aef-be4b-c76bdc7fc7cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930124753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.930124753
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.343671431
Short name T261
Test name
Test status
Simulation time 164373209226 ps
CPU time 51.69 seconds
Started May 19 01:33:51 PM PDT 24
Finished May 19 01:34:44 PM PDT 24
Peak memory 201840 kb
Host smart-46b50fa7-d88b-4a03-ab9f-929827ad4e4d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343671431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.343671431
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.4162080619
Short name T283
Test name
Test status
Simulation time 185368468914 ps
CPU time 204.84 seconds
Started May 19 01:33:53 PM PDT 24
Finished May 19 01:37:20 PM PDT 24
Peak memory 201764 kb
Host smart-7ca5c0d3-a7cd-46ff-8689-8a13c6f1b857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162080619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.4162080619
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1139128597
Short name T438
Test name
Test status
Simulation time 164797620429 ps
CPU time 402.02 seconds
Started May 19 01:33:48 PM PDT 24
Finished May 19 01:40:31 PM PDT 24
Peak memory 201864 kb
Host smart-415e7c36-87e8-43bc-b7ac-9c11bee16852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139128597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1139128597
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2466271051
Short name T668
Test name
Test status
Simulation time 493281600332 ps
CPU time 292.96 seconds
Started May 19 01:33:49 PM PDT 24
Finished May 19 01:38:43 PM PDT 24
Peak memory 201884 kb
Host smart-66a4ea33-d1f9-4f47-9330-98eca13d708b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466271051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2466271051
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2314324084
Short name T193
Test name
Test status
Simulation time 329831937786 ps
CPU time 52.94 seconds
Started May 19 01:33:59 PM PDT 24
Finished May 19 01:34:53 PM PDT 24
Peak memory 201836 kb
Host smart-21327d5f-55d9-4cde-a3d2-55241912864c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314324084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2314324084
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.642119288
Short name T608
Test name
Test status
Simulation time 492790430385 ps
CPU time 66.75 seconds
Started May 19 01:33:52 PM PDT 24
Finished May 19 01:35:00 PM PDT 24
Peak memory 201856 kb
Host smart-87e22cc2-2cd4-4fc8-8fe8-4053423f7ec0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=642119288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.642119288
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.4039518201
Short name T151
Test name
Test status
Simulation time 601348228022 ps
CPU time 361.91 seconds
Started May 19 01:33:52 PM PDT 24
Finished May 19 01:39:56 PM PDT 24
Peak memory 201776 kb
Host smart-ca183d71-96aa-4edb-bf63-a972cb6dab2a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039518201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.4039518201
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.1854247315
Short name T628
Test name
Test status
Simulation time 78864587829 ps
CPU time 449.72 seconds
Started May 19 01:33:52 PM PDT 24
Finished May 19 01:41:23 PM PDT 24
Peak memory 202084 kb
Host smart-39240af0-6a65-445c-ac8b-673b3eea82c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854247315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1854247315
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3651559649
Short name T195
Test name
Test status
Simulation time 45034934689 ps
CPU time 57.59 seconds
Started May 19 01:33:47 PM PDT 24
Finished May 19 01:34:45 PM PDT 24
Peak memory 201604 kb
Host smart-0064bc0a-a780-404d-afd3-af0bd3545134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651559649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3651559649
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1211548088
Short name T697
Test name
Test status
Simulation time 4158675296 ps
CPU time 3.56 seconds
Started May 19 01:34:04 PM PDT 24
Finished May 19 01:34:10 PM PDT 24
Peak memory 201524 kb
Host smart-e4f1bbfb-47d8-4717-ac11-b824349a06b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211548088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1211548088
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.945211418
Short name T644
Test name
Test status
Simulation time 6023184693 ps
CPU time 14.15 seconds
Started May 19 01:33:53 PM PDT 24
Finished May 19 01:34:09 PM PDT 24
Peak memory 201600 kb
Host smart-c13343e0-b47e-438e-8998-9b17969085ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945211418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.945211418
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2135815861
Short name T21
Test name
Test status
Simulation time 384934281904 ps
CPU time 286.56 seconds
Started May 19 01:33:49 PM PDT 24
Finished May 19 01:38:36 PM PDT 24
Peak memory 210520 kb
Host smart-69d0333c-b1b2-4c6a-8955-04faf007d513
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135815861 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2135815861
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3092502746
Short name T198
Test name
Test status
Simulation time 333205746 ps
CPU time 1.29 seconds
Started May 19 01:33:53 PM PDT 24
Finished May 19 01:33:56 PM PDT 24
Peak memory 201468 kb
Host smart-778cf37c-cb12-448f-8975-522f3ed060bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092502746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3092502746
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2877624838
Short name T215
Test name
Test status
Simulation time 332045296819 ps
CPU time 55.98 seconds
Started May 19 01:33:52 PM PDT 24
Finished May 19 01:34:49 PM PDT 24
Peak memory 201788 kb
Host smart-dbc1dccb-2831-4fd2-8728-b2989a9adb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877624838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2877624838
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2515548315
Short name T145
Test name
Test status
Simulation time 316487186662 ps
CPU time 657.84 seconds
Started May 19 01:33:55 PM PDT 24
Finished May 19 01:44:54 PM PDT 24
Peak memory 201772 kb
Host smart-f5d35ab9-e04e-4a81-9700-9122cbc6a37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515548315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2515548315
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.829412969
Short name T767
Test name
Test status
Simulation time 494234920424 ps
CPU time 781.62 seconds
Started May 19 01:33:55 PM PDT 24
Finished May 19 01:46:58 PM PDT 24
Peak memory 202040 kb
Host smart-f3b9bc11-4e63-46ec-bae4-f995cbe54a8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=829412969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrup
t_fixed.829412969
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2317540162
Short name T128
Test name
Test status
Simulation time 320270683014 ps
CPU time 780.08 seconds
Started May 19 01:33:47 PM PDT 24
Finished May 19 01:46:48 PM PDT 24
Peak memory 201768 kb
Host smart-620c2324-eee0-40a1-a9c2-6536392949d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317540162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2317540162
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.4066539707
Short name T170
Test name
Test status
Simulation time 490581406129 ps
CPU time 278.57 seconds
Started May 19 01:34:02 PM PDT 24
Finished May 19 01:38:42 PM PDT 24
Peak memory 201788 kb
Host smart-98705fad-9223-4bda-9600-edcb69e1ffbd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066539707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.4066539707
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1589202312
Short name T423
Test name
Test status
Simulation time 602358914989 ps
CPU time 424.83 seconds
Started May 19 01:34:12 PM PDT 24
Finished May 19 01:41:18 PM PDT 24
Peak memory 201840 kb
Host smart-ff995ebd-92e0-48c4-bd7c-1873b726327a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589202312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1589202312
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2070239612
Short name T43
Test name
Test status
Simulation time 100020703969 ps
CPU time 418.59 seconds
Started May 19 01:33:58 PM PDT 24
Finished May 19 01:40:57 PM PDT 24
Peak memory 202212 kb
Host smart-23620616-f7a3-4fe5-9225-03565fef714d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070239612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2070239612
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2541911541
Short name T508
Test name
Test status
Simulation time 36854561746 ps
CPU time 16.46 seconds
Started May 19 01:34:03 PM PDT 24
Finished May 19 01:34:22 PM PDT 24
Peak memory 201884 kb
Host smart-34b8e6f4-d3e6-4489-a4d9-b865ed5df524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541911541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2541911541
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.4242968541
Short name T631
Test name
Test status
Simulation time 3731453862 ps
CPU time 8.73 seconds
Started May 19 01:34:09 PM PDT 24
Finished May 19 01:34:19 PM PDT 24
Peak memory 201580 kb
Host smart-18cbee1a-4fc6-49fa-bc54-2e64a79afa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242968541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.4242968541
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.264867579
Short name T184
Test name
Test status
Simulation time 5585115338 ps
CPU time 13.32 seconds
Started May 19 01:33:55 PM PDT 24
Finished May 19 01:34:10 PM PDT 24
Peak memory 201612 kb
Host smart-9dee1e45-f193-4a67-8d26-a1171d2a13b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264867579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.264867579
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2158286462
Short name T710
Test name
Test status
Simulation time 215789735541 ps
CPU time 201.22 seconds
Started May 19 01:34:02 PM PDT 24
Finished May 19 01:37:26 PM PDT 24
Peak memory 201844 kb
Host smart-c2d349d9-92c4-415a-9e65-e2f25e91e20a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158286462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2158286462
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2155554900
Short name T394
Test name
Test status
Simulation time 374426148 ps
CPU time 1.14 seconds
Started May 19 01:33:53 PM PDT 24
Finished May 19 01:33:56 PM PDT 24
Peak memory 201464 kb
Host smart-00ffa831-5bff-4a98-b963-639489097be8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155554900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2155554900
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.2848893821
Short name T252
Test name
Test status
Simulation time 190693436644 ps
CPU time 236.84 seconds
Started May 19 01:34:02 PM PDT 24
Finished May 19 01:38:01 PM PDT 24
Peak memory 201796 kb
Host smart-c46350fb-aff8-440b-80a8-b298a500ff2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848893821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.2848893821
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.889540863
Short name T556
Test name
Test status
Simulation time 493169260269 ps
CPU time 108.69 seconds
Started May 19 01:33:54 PM PDT 24
Finished May 19 01:35:44 PM PDT 24
Peak memory 201832 kb
Host smart-e1d7e042-1576-40af-8125-bcf6df5f2036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889540863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.889540863
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.797945962
Short name T523
Test name
Test status
Simulation time 498779369983 ps
CPU time 292.27 seconds
Started May 19 01:33:51 PM PDT 24
Finished May 19 01:38:44 PM PDT 24
Peak memory 201832 kb
Host smart-e89bf0aa-c83c-4e27-be6a-98db98f4634e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=797945962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrup
t_fixed.797945962
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1178627772
Short name T289
Test name
Test status
Simulation time 163852215198 ps
CPU time 412.94 seconds
Started May 19 01:33:53 PM PDT 24
Finished May 19 01:40:48 PM PDT 24
Peak memory 201752 kb
Host smart-e3035ac3-84d6-4c2c-8c2f-6be9793ec261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178627772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1178627772
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1315469221
Short name T382
Test name
Test status
Simulation time 494557634533 ps
CPU time 562.08 seconds
Started May 19 01:33:49 PM PDT 24
Finished May 19 01:43:11 PM PDT 24
Peak memory 202064 kb
Host smart-4f06afd6-b533-472d-b319-0f712145ee02
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315469221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1315469221
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2176901144
Short name T222
Test name
Test status
Simulation time 389967322399 ps
CPU time 493.66 seconds
Started May 19 01:34:02 PM PDT 24
Finished May 19 01:42:17 PM PDT 24
Peak memory 201824 kb
Host smart-408d6ba9-c580-43b5-83ff-8c3d6c6492cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176901144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2176901144
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2938524275
Short name T759
Test name
Test status
Simulation time 607783266894 ps
CPU time 728.91 seconds
Started May 19 01:34:02 PM PDT 24
Finished May 19 01:46:13 PM PDT 24
Peak memory 201792 kb
Host smart-22522e11-bb8c-4856-ab52-d37f9b225345
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938524275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2938524275
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.990817598
Short name T369
Test name
Test status
Simulation time 82786194213 ps
CPU time 294.94 seconds
Started May 19 01:33:53 PM PDT 24
Finished May 19 01:38:50 PM PDT 24
Peak memory 202076 kb
Host smart-38cc5d01-1979-4d25-92de-40a8841c9970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990817598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.990817598
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.4167762340
Short name T427
Test name
Test status
Simulation time 38921795659 ps
CPU time 47.24 seconds
Started May 19 01:33:53 PM PDT 24
Finished May 19 01:34:42 PM PDT 24
Peak memory 201588 kb
Host smart-f8eea467-d0fb-4614-8ff4-0b4a09e2e900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167762340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.4167762340
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1963867279
Short name T26
Test name
Test status
Simulation time 2820570312 ps
CPU time 7.5 seconds
Started May 19 01:33:51 PM PDT 24
Finished May 19 01:34:00 PM PDT 24
Peak memory 201588 kb
Host smart-88683256-e75f-4990-a896-9ff0e6a72575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963867279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1963867279
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1330906225
Short name T551
Test name
Test status
Simulation time 5537222026 ps
CPU time 13.36 seconds
Started May 19 01:33:53 PM PDT 24
Finished May 19 01:34:08 PM PDT 24
Peak memory 201596 kb
Host smart-7ea0917f-3c01-4a74-a1fc-6b7f08532028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330906225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1330906225
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.4109518863
Short name T242
Test name
Test status
Simulation time 317762711595 ps
CPU time 528.77 seconds
Started May 19 01:34:11 PM PDT 24
Finished May 19 01:43:01 PM PDT 24
Peak memory 210416 kb
Host smart-8f0c4ca3-4840-4f1c-94d1-3d88de7c5e5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109518863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.4109518863
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1344679412
Short name T440
Test name
Test status
Simulation time 361513898 ps
CPU time 0.88 seconds
Started May 19 01:34:13 PM PDT 24
Finished May 19 01:34:14 PM PDT 24
Peak memory 201460 kb
Host smart-d5676619-4086-47d1-8997-014c2806ad26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344679412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1344679412
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3831071474
Short name T330
Test name
Test status
Simulation time 504185961188 ps
CPU time 242.04 seconds
Started May 19 01:34:01 PM PDT 24
Finished May 19 01:38:05 PM PDT 24
Peak memory 201804 kb
Host smart-b36e0676-8ca3-413c-8bef-b54b985ddc9c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831071474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3831071474
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.787517465
Short name T694
Test name
Test status
Simulation time 328175313893 ps
CPU time 812.14 seconds
Started May 19 01:34:01 PM PDT 24
Finished May 19 01:47:35 PM PDT 24
Peak memory 201908 kb
Host smart-e71cb43c-83cd-4177-8a80-ca8038bf5539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787517465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.787517465
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.982572064
Short name T641
Test name
Test status
Simulation time 166543556222 ps
CPU time 64.52 seconds
Started May 19 01:34:04 PM PDT 24
Finished May 19 01:35:11 PM PDT 24
Peak memory 201636 kb
Host smart-39873aa2-d5b7-49c2-90e8-dca759c9ff24
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=982572064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.982572064
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2035020129
Short name T249
Test name
Test status
Simulation time 165627134874 ps
CPU time 98.3 seconds
Started May 19 01:33:53 PM PDT 24
Finished May 19 01:35:33 PM PDT 24
Peak memory 201752 kb
Host smart-d0c001b9-f6f3-469e-b3c4-f02e6466cabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035020129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2035020129
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.158697088
Short name T715
Test name
Test status
Simulation time 482708397525 ps
CPU time 255.2 seconds
Started May 19 01:34:08 PM PDT 24
Finished May 19 01:38:24 PM PDT 24
Peak memory 201824 kb
Host smart-81b2c082-a1cf-4801-b949-510aee5bf631
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=158697088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.158697088
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1907091088
Short name T573
Test name
Test status
Simulation time 360711067936 ps
CPU time 452.61 seconds
Started May 19 01:34:07 PM PDT 24
Finished May 19 01:41:42 PM PDT 24
Peak memory 201856 kb
Host smart-29a79c60-77ea-414b-9598-d8241cc308d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907091088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1907091088
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1358589825
Short name T461
Test name
Test status
Simulation time 382591886284 ps
CPU time 910.22 seconds
Started May 19 01:34:14 PM PDT 24
Finished May 19 01:49:26 PM PDT 24
Peak memory 201768 kb
Host smart-5348ca84-72cc-4f43-8b67-4b79a9e121b5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358589825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1358589825
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1265275082
Short name T793
Test name
Test status
Simulation time 92452565212 ps
CPU time 367.36 seconds
Started May 19 01:34:14 PM PDT 24
Finished May 19 01:40:23 PM PDT 24
Peak memory 202156 kb
Host smart-7da66ca5-664b-46e7-8089-661d935320e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265275082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1265275082
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2202168265
Short name T385
Test name
Test status
Simulation time 29557736904 ps
CPU time 36.05 seconds
Started May 19 01:34:04 PM PDT 24
Finished May 19 01:34:43 PM PDT 24
Peak memory 201660 kb
Host smart-9a1d6649-ee09-4087-bda6-1cf84f4a8f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202168265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2202168265
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3649891113
Short name T764
Test name
Test status
Simulation time 5095075414 ps
CPU time 3.61 seconds
Started May 19 01:34:05 PM PDT 24
Finished May 19 01:34:11 PM PDT 24
Peak memory 201644 kb
Host smart-bee50ddf-e2ed-4066-b33c-419df0a90b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649891113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3649891113
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.688795531
Short name T534
Test name
Test status
Simulation time 5729896089 ps
CPU time 7.98 seconds
Started May 19 01:34:03 PM PDT 24
Finished May 19 01:34:13 PM PDT 24
Peak memory 201652 kb
Host smart-83959e58-5df8-49f6-8d36-76b3797dc2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688795531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.688795531
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.836234440
Short name T601
Test name
Test status
Simulation time 209649055150 ps
CPU time 139.56 seconds
Started May 19 01:34:13 PM PDT 24
Finished May 19 01:36:34 PM PDT 24
Peak memory 201792 kb
Host smart-1c9c6a75-56cb-47e9-97e6-6c533bf0e7f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836234440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
836234440
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3307419791
Short name T317
Test name
Test status
Simulation time 74470245327 ps
CPU time 55.18 seconds
Started May 19 01:34:18 PM PDT 24
Finished May 19 01:35:14 PM PDT 24
Peak memory 210408 kb
Host smart-331c17cb-67d4-4bbd-abf7-6a7a543a1ec9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307419791 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3307419791
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.149334851
Short name T637
Test name
Test status
Simulation time 520696832 ps
CPU time 1.35 seconds
Started May 19 01:34:15 PM PDT 24
Finished May 19 01:34:18 PM PDT 24
Peak memory 201532 kb
Host smart-c8708cc5-3bef-49b7-ad6f-3eb9fd8ddd25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149334851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.149334851
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3232403994
Short name T106
Test name
Test status
Simulation time 197763242864 ps
CPU time 456.87 seconds
Started May 19 01:34:04 PM PDT 24
Finished May 19 01:41:43 PM PDT 24
Peak memory 201992 kb
Host smart-0ec22e7d-c184-4603-ac7a-584b3f122192
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232403994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3232403994
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2610919499
Short name T310
Test name
Test status
Simulation time 162832550106 ps
CPU time 374.31 seconds
Started May 19 01:34:04 PM PDT 24
Finished May 19 01:40:21 PM PDT 24
Peak memory 201716 kb
Host smart-2cb03ed2-11ad-4133-a813-34a1854a5489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610919499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2610919499
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1450254348
Short name T670
Test name
Test status
Simulation time 491411688173 ps
CPU time 130.35 seconds
Started May 19 01:34:11 PM PDT 24
Finished May 19 01:36:22 PM PDT 24
Peak memory 201804 kb
Host smart-dc005e45-e6a0-4bf4-963d-0adcbd11af0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450254348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1450254348
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3354877649
Short name T627
Test name
Test status
Simulation time 499961161452 ps
CPU time 1124.48 seconds
Started May 19 01:34:09 PM PDT 24
Finished May 19 01:52:55 PM PDT 24
Peak memory 201796 kb
Host smart-341aee22-60b8-4465-897e-334db4d6b4a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354877649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3354877649
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.751266893
Short name T192
Test name
Test status
Simulation time 334721945069 ps
CPU time 56.6 seconds
Started May 19 01:34:05 PM PDT 24
Finished May 19 01:35:04 PM PDT 24
Peak memory 201876 kb
Host smart-58c2d0c2-d046-47e9-8c77-f1a6d5d71af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751266893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.751266893
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.276582804
Short name T183
Test name
Test status
Simulation time 161472257833 ps
CPU time 58.42 seconds
Started May 19 01:34:03 PM PDT 24
Finished May 19 01:35:04 PM PDT 24
Peak memory 201808 kb
Host smart-c667e398-214e-409f-a242-6bc4fe4f6dca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=276582804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.276582804
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2013926290
Short name T313
Test name
Test status
Simulation time 526779299597 ps
CPU time 277.76 seconds
Started May 19 01:34:18 PM PDT 24
Finished May 19 01:38:57 PM PDT 24
Peak memory 201804 kb
Host smart-d5eca5d7-f173-4013-badb-f2e67156bbc6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013926290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2013926290
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2051572212
Short name T466
Test name
Test status
Simulation time 597285705644 ps
CPU time 1397.86 seconds
Started May 19 01:34:04 PM PDT 24
Finished May 19 01:57:24 PM PDT 24
Peak memory 201732 kb
Host smart-3b9b83c6-d97c-4b7c-bc81-985a47740ab4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051572212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2051572212
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3244472688
Short name T46
Test name
Test status
Simulation time 70367591847 ps
CPU time 259.7 seconds
Started May 19 01:34:01 PM PDT 24
Finished May 19 01:38:21 PM PDT 24
Peak memory 202128 kb
Host smart-5ed38f58-dc91-4ed0-93d2-c14e3df13471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244472688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3244472688
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3269886944
Short name T407
Test name
Test status
Simulation time 28801758667 ps
CPU time 34.47 seconds
Started May 19 01:34:07 PM PDT 24
Finished May 19 01:34:43 PM PDT 24
Peak memory 201608 kb
Host smart-ad92de65-6bc3-4263-a957-15bfae5210b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269886944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3269886944
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1338169676
Short name T501
Test name
Test status
Simulation time 3053166129 ps
CPU time 2.34 seconds
Started May 19 01:34:16 PM PDT 24
Finished May 19 01:34:20 PM PDT 24
Peak memory 201604 kb
Host smart-3c94fd04-07b9-48ab-a94a-e7699419de91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338169676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1338169676
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.438859385
Short name T553
Test name
Test status
Simulation time 5993422601 ps
CPU time 4.71 seconds
Started May 19 01:34:04 PM PDT 24
Finished May 19 01:34:11 PM PDT 24
Peak memory 201624 kb
Host smart-8a3d091e-7b4a-43f4-a904-f4be07d9c6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438859385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.438859385
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2323712432
Short name T320
Test name
Test status
Simulation time 329286420113 ps
CPU time 172.92 seconds
Started May 19 01:34:07 PM PDT 24
Finished May 19 01:37:02 PM PDT 24
Peak memory 201856 kb
Host smart-57e54ef5-3dab-4259-aab0-d765fb7ab7bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323712432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2323712432
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.63745255
Short name T656
Test name
Test status
Simulation time 104163111178 ps
CPU time 123.09 seconds
Started May 19 01:34:01 PM PDT 24
Finished May 19 01:36:06 PM PDT 24
Peak memory 210420 kb
Host smart-00bae4fb-fac2-4375-ab60-0e84a0feff30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63745255 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.63745255
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3108172920
Short name T401
Test name
Test status
Simulation time 445972925 ps
CPU time 1.8 seconds
Started May 19 01:34:17 PM PDT 24
Finished May 19 01:34:21 PM PDT 24
Peak memory 201496 kb
Host smart-d6da9c16-84cf-450f-9d75-6a4ad6ac00c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108172920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3108172920
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2938904698
Short name T669
Test name
Test status
Simulation time 166851866833 ps
CPU time 109.82 seconds
Started May 19 01:34:13 PM PDT 24
Finished May 19 01:36:04 PM PDT 24
Peak memory 201760 kb
Host smart-fc1c2ac3-01bd-4b8c-9d95-e56ca235cb6e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938904698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2938904698
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3018042529
Short name T660
Test name
Test status
Simulation time 479002863822 ps
CPU time 562.38 seconds
Started May 19 01:34:04 PM PDT 24
Finished May 19 01:43:28 PM PDT 24
Peak memory 201848 kb
Host smart-d60b61cd-5194-4c5a-a5fb-a7a242ea56c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018042529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3018042529
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.4233922909
Short name T549
Test name
Test status
Simulation time 165323729112 ps
CPU time 92.34 seconds
Started May 19 01:34:05 PM PDT 24
Finished May 19 01:35:40 PM PDT 24
Peak memory 201820 kb
Host smart-ef885417-c162-49c1-bd74-06b39e84596b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233922909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.4233922909
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3394173818
Short name T723
Test name
Test status
Simulation time 495678003130 ps
CPU time 282.23 seconds
Started May 19 01:34:07 PM PDT 24
Finished May 19 01:38:51 PM PDT 24
Peak memory 201892 kb
Host smart-6e897c05-cf5f-41a8-8a08-101d3a51ce55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394173818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3394173818
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2283846019
Short name T386
Test name
Test status
Simulation time 165095944264 ps
CPU time 397.71 seconds
Started May 19 01:34:02 PM PDT 24
Finished May 19 01:40:41 PM PDT 24
Peak memory 201756 kb
Host smart-0ee048ca-d19c-4627-ae01-bd34d4c3e554
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283846019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2283846019
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.284474929
Short name T719
Test name
Test status
Simulation time 197523346322 ps
CPU time 457.64 seconds
Started May 19 01:34:18 PM PDT 24
Finished May 19 01:41:57 PM PDT 24
Peak memory 201792 kb
Host smart-e09d645a-6296-4b4a-aba9-67008187261c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284474929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.284474929
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2657698372
Short name T45
Test name
Test status
Simulation time 136726148156 ps
CPU time 534.43 seconds
Started May 19 01:34:11 PM PDT 24
Finished May 19 01:43:07 PM PDT 24
Peak memory 202124 kb
Host smart-12d911e1-ff1d-4c25-8792-4b1ee5fb27de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657698372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2657698372
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2450581672
Short name T561
Test name
Test status
Simulation time 22040347012 ps
CPU time 51.03 seconds
Started May 19 01:34:14 PM PDT 24
Finished May 19 01:35:07 PM PDT 24
Peak memory 201648 kb
Host smart-23a8e350-34e8-40bc-9b2c-29960e6a4dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450581672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2450581672
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2851869573
Short name T535
Test name
Test status
Simulation time 3698436241 ps
CPU time 9.5 seconds
Started May 19 01:34:14 PM PDT 24
Finished May 19 01:34:26 PM PDT 24
Peak memory 201528 kb
Host smart-336906c4-849f-40f9-a056-0b47bfa6799c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851869573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2851869573
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3027632863
Short name T455
Test name
Test status
Simulation time 5882484332 ps
CPU time 3.43 seconds
Started May 19 01:34:04 PM PDT 24
Finished May 19 01:34:10 PM PDT 24
Peak memory 201616 kb
Host smart-9d3b0963-c857-43d3-8c21-70fbe391416f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027632863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3027632863
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3727447636
Short name T790
Test name
Test status
Simulation time 246219680283 ps
CPU time 785.79 seconds
Started May 19 01:34:09 PM PDT 24
Finished May 19 01:47:16 PM PDT 24
Peak memory 202112 kb
Host smart-35e02860-5eaa-42f8-8d3f-dca67210ce34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727447636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3727447636
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2381974629
Short name T586
Test name
Test status
Simulation time 528228577 ps
CPU time 1.31 seconds
Started May 19 01:34:15 PM PDT 24
Finished May 19 01:34:18 PM PDT 24
Peak memory 201488 kb
Host smart-163820eb-4df7-4561-a6ce-f631e20ba8b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381974629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2381974629
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.4214551013
Short name T360
Test name
Test status
Simulation time 507202685700 ps
CPU time 117.73 seconds
Started May 19 01:34:04 PM PDT 24
Finished May 19 01:36:04 PM PDT 24
Peak memory 201852 kb
Host smart-772b8fe6-29c2-42d9-b4db-3c95db6dea83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214551013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.4214551013
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.89296128
Short name T763
Test name
Test status
Simulation time 331023650027 ps
CPU time 66.95 seconds
Started May 19 01:34:07 PM PDT 24
Finished May 19 01:35:15 PM PDT 24
Peak memory 201808 kb
Host smart-d198116e-9636-4622-9228-c6fc20140756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89296128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.89296128
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3929209448
Short name T338
Test name
Test status
Simulation time 323470153760 ps
CPU time 322.37 seconds
Started May 19 01:34:03 PM PDT 24
Finished May 19 01:39:28 PM PDT 24
Peak memory 201788 kb
Host smart-82c91de5-db1e-4823-b622-36f6876452b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929209448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3929209448
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2349849993
Short name T162
Test name
Test status
Simulation time 328459505600 ps
CPU time 725.79 seconds
Started May 19 01:34:01 PM PDT 24
Finished May 19 01:46:09 PM PDT 24
Peak memory 201796 kb
Host smart-9d7e2b96-c3a8-45d7-acec-3c68ff5b919f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349849993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2349849993
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3422775692
Short name T640
Test name
Test status
Simulation time 495893693073 ps
CPU time 1188.79 seconds
Started May 19 01:34:10 PM PDT 24
Finished May 19 01:54:00 PM PDT 24
Peak memory 201896 kb
Host smart-ab65756f-c85e-4257-a466-eaa78a561fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422775692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3422775692
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.4041219024
Short name T528
Test name
Test status
Simulation time 331664457444 ps
CPU time 804.06 seconds
Started May 19 01:34:04 PM PDT 24
Finished May 19 01:47:30 PM PDT 24
Peak memory 202060 kb
Host smart-83639c44-88b9-411a-a6e9-c981d237b24e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041219024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.4041219024
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3014182184
Short name T744
Test name
Test status
Simulation time 580902762885 ps
CPU time 666.75 seconds
Started May 19 01:34:13 PM PDT 24
Finished May 19 01:45:21 PM PDT 24
Peak memory 201768 kb
Host smart-02468bea-ce46-4a6c-a1bd-ae480bf4e165
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014182184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3014182184
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3672917825
Short name T663
Test name
Test status
Simulation time 409232451049 ps
CPU time 945.35 seconds
Started May 19 01:34:10 PM PDT 24
Finished May 19 01:49:57 PM PDT 24
Peak memory 201836 kb
Host smart-daafe94a-7bb3-4200-a1ef-a53f9d81d8fe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672917825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3672917825
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2488464751
Short name T739
Test name
Test status
Simulation time 79098445963 ps
CPU time 282.42 seconds
Started May 19 01:34:01 PM PDT 24
Finished May 19 01:38:44 PM PDT 24
Peak memory 202136 kb
Host smart-32dad699-56ba-48a0-9a08-4aa12a2151f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488464751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2488464751
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3748894518
Short name T224
Test name
Test status
Simulation time 28695105565 ps
CPU time 17.56 seconds
Started May 19 01:34:14 PM PDT 24
Finished May 19 01:34:34 PM PDT 24
Peak memory 201592 kb
Host smart-9b11f315-961d-449e-bdf1-17d851328080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748894518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3748894518
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3469581777
Short name T430
Test name
Test status
Simulation time 3533805673 ps
CPU time 9.66 seconds
Started May 19 01:34:08 PM PDT 24
Finished May 19 01:34:19 PM PDT 24
Peak memory 201544 kb
Host smart-7c86d4cf-fa46-42aa-affd-f20b364d7e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469581777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3469581777
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2449780996
Short name T775
Test name
Test status
Simulation time 5821179027 ps
CPU time 15.3 seconds
Started May 19 01:34:16 PM PDT 24
Finished May 19 01:34:33 PM PDT 24
Peak memory 201640 kb
Host smart-87c08fea-5028-4bcb-a772-134aee498ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449780996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2449780996
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1300230871
Short name T214
Test name
Test status
Simulation time 360360198193 ps
CPU time 207.93 seconds
Started May 19 01:34:06 PM PDT 24
Finished May 19 01:37:36 PM PDT 24
Peak memory 201812 kb
Host smart-0dce4757-6c0b-4df8-b4ab-dfda260be387
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300230871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1300230871
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.449540813
Short name T327
Test name
Test status
Simulation time 144457423055 ps
CPU time 455.08 seconds
Started May 19 01:34:06 PM PDT 24
Finished May 19 01:41:43 PM PDT 24
Peak memory 211452 kb
Host smart-fcdf310e-06c6-4141-80f6-a0d09d9eb995
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449540813 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.449540813
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.2636057426
Short name T400
Test name
Test status
Simulation time 425330613 ps
CPU time 0.86 seconds
Started May 19 01:34:18 PM PDT 24
Finished May 19 01:34:20 PM PDT 24
Peak memory 201492 kb
Host smart-3cff6039-3491-4aaf-8cdd-aa6dae91b21d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636057426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2636057426
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2182973359
Short name T507
Test name
Test status
Simulation time 175144475613 ps
CPU time 57.53 seconds
Started May 19 01:34:17 PM PDT 24
Finished May 19 01:35:16 PM PDT 24
Peak memory 201824 kb
Host smart-facb831a-26b1-48cb-9175-28930196c7ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182973359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2182973359
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3884042621
Short name T250
Test name
Test status
Simulation time 164819004337 ps
CPU time 212.26 seconds
Started May 19 01:34:11 PM PDT 24
Finished May 19 01:37:44 PM PDT 24
Peak memory 201780 kb
Host smart-3a2b0390-035b-4b38-a159-f777bf03b7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884042621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3884042621
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2508799661
Short name T429
Test name
Test status
Simulation time 489584453550 ps
CPU time 615.14 seconds
Started May 19 01:34:11 PM PDT 24
Finished May 19 01:44:27 PM PDT 24
Peak memory 201812 kb
Host smart-1a7f293d-2ee3-459e-ba98-fae51c3a275a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508799661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2508799661
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.699333798
Short name T577
Test name
Test status
Simulation time 327996752653 ps
CPU time 264.14 seconds
Started May 19 01:34:13 PM PDT 24
Finished May 19 01:38:40 PM PDT 24
Peak memory 201776 kb
Host smart-0afdfda9-87a3-4bb1-b67b-31dc63095d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699333798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.699333798
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2764012929
Short name T141
Test name
Test status
Simulation time 493030397659 ps
CPU time 240.64 seconds
Started May 19 01:34:03 PM PDT 24
Finished May 19 01:38:06 PM PDT 24
Peak memory 201760 kb
Host smart-5ae6f287-d29b-47d9-b5ba-d69dc22ed5ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764012929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2764012929
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2445867205
Short name T638
Test name
Test status
Simulation time 203039454484 ps
CPU time 473.96 seconds
Started May 19 01:34:04 PM PDT 24
Finished May 19 01:42:01 PM PDT 24
Peak memory 202000 kb
Host smart-eb82fcf2-fcab-4fad-a496-6ee8b7df3a04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445867205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2445867205
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2361511551
Short name T203
Test name
Test status
Simulation time 189131276357 ps
CPU time 103.25 seconds
Started May 19 01:34:05 PM PDT 24
Finished May 19 01:35:51 PM PDT 24
Peak memory 201824 kb
Host smart-5fd0b126-7c93-47e9-adec-c8a4c8473abc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361511551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2361511551
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.341430137
Short name T746
Test name
Test status
Simulation time 119601522873 ps
CPU time 557.25 seconds
Started May 19 01:34:18 PM PDT 24
Finished May 19 01:43:37 PM PDT 24
Peak memory 202140 kb
Host smart-ff465ac8-a885-48b6-9fe7-8ef951196d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341430137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.341430137
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.4186910291
Short name T210
Test name
Test status
Simulation time 44482507230 ps
CPU time 94.1 seconds
Started May 19 01:34:17 PM PDT 24
Finished May 19 01:35:52 PM PDT 24
Peak memory 201624 kb
Host smart-5372d9d4-ccb2-4ec6-843b-586b79e5d9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186910291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.4186910291
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1980070025
Short name T506
Test name
Test status
Simulation time 4004339357 ps
CPU time 5.04 seconds
Started May 19 01:34:06 PM PDT 24
Finished May 19 01:34:13 PM PDT 24
Peak memory 201560 kb
Host smart-cb51f186-4c73-4722-8873-d817c0642ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980070025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1980070025
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3638231335
Short name T598
Test name
Test status
Simulation time 5771763644 ps
CPU time 4.18 seconds
Started May 19 01:34:13 PM PDT 24
Finished May 19 01:34:20 PM PDT 24
Peak memory 201648 kb
Host smart-a387a6b4-5e2f-4833-a757-31a6a9ea27d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638231335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3638231335
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.243621078
Short name T761
Test name
Test status
Simulation time 48778766774 ps
CPU time 60.25 seconds
Started May 19 01:34:06 PM PDT 24
Finished May 19 01:35:09 PM PDT 24
Peak memory 211168 kb
Host smart-7a610794-5142-45f7-a01d-8ea8bf2c0033
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243621078 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.243621078
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.40870559
Short name T721
Test name
Test status
Simulation time 396167255 ps
CPU time 0.93 seconds
Started May 19 01:34:07 PM PDT 24
Finished May 19 01:34:10 PM PDT 24
Peak memory 201560 kb
Host smart-443b9ac4-d4ba-4a8b-8745-66b65dbc9ef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40870559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.40870559
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1219885968
Short name T342
Test name
Test status
Simulation time 161493058247 ps
CPU time 97.6 seconds
Started May 19 01:34:06 PM PDT 24
Finished May 19 01:35:45 PM PDT 24
Peak memory 201912 kb
Host smart-26220b1f-c8dd-4e19-88f2-0422a4427406
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219885968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1219885968
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2488308473
Short name T294
Test name
Test status
Simulation time 511874842157 ps
CPU time 1238.41 seconds
Started May 19 01:34:17 PM PDT 24
Finished May 19 01:54:57 PM PDT 24
Peak memory 201820 kb
Host smart-f82ee08b-b8b4-4270-9ccc-49eb532cace5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488308473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2488308473
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3632852985
Short name T178
Test name
Test status
Simulation time 500584766044 ps
CPU time 589.36 seconds
Started May 19 01:34:07 PM PDT 24
Finished May 19 01:43:58 PM PDT 24
Peak memory 201828 kb
Host smart-a0ac2a38-b12d-49d6-b8c9-f2e2ed1a1693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632852985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3632852985
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3471015306
Short name T786
Test name
Test status
Simulation time 167824900452 ps
CPU time 109.77 seconds
Started May 19 01:34:06 PM PDT 24
Finished May 19 01:35:58 PM PDT 24
Peak memory 201836 kb
Host smart-bc00b34d-b8fe-4e79-9c71-0aa4aacd604f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471015306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3471015306
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.947755739
Short name T24
Test name
Test status
Simulation time 160851254061 ps
CPU time 98.04 seconds
Started May 19 01:34:07 PM PDT 24
Finished May 19 01:35:47 PM PDT 24
Peak memory 201888 kb
Host smart-4dfc9ba3-4bfa-4344-b007-4f64954c7173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947755739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.947755739
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.4176717824
Short name T676
Test name
Test status
Simulation time 327750702625 ps
CPU time 806.62 seconds
Started May 19 01:34:20 PM PDT 24
Finished May 19 01:47:47 PM PDT 24
Peak memory 201812 kb
Host smart-8f27ccf5-a9b8-4ee0-9813-11d2a931e3b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176717824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.4176717824
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1698435409
Short name T448
Test name
Test status
Simulation time 198285457354 ps
CPU time 444.35 seconds
Started May 19 01:34:18 PM PDT 24
Finished May 19 01:41:44 PM PDT 24
Peak memory 201804 kb
Host smart-dff813c9-440b-4249-a103-12ca682cf82e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698435409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1698435409
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1136277305
Short name T604
Test name
Test status
Simulation time 606212320308 ps
CPU time 1513.24 seconds
Started May 19 01:34:06 PM PDT 24
Finished May 19 01:59:22 PM PDT 24
Peak memory 201828 kb
Host smart-b0698eb4-71e3-402f-be35-1a428892d73f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136277305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1136277305
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1692897824
Short name T367
Test name
Test status
Simulation time 76731520417 ps
CPU time 265.46 seconds
Started May 19 01:34:17 PM PDT 24
Finished May 19 01:38:44 PM PDT 24
Peak memory 202132 kb
Host smart-d4445a9a-3667-4fb1-8e9d-4cc469698350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692897824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1692897824
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1439011750
Short name T521
Test name
Test status
Simulation time 26767452576 ps
CPU time 33.35 seconds
Started May 19 01:34:14 PM PDT 24
Finished May 19 01:34:49 PM PDT 24
Peak memory 201636 kb
Host smart-cb170d19-18f5-4179-81b7-0e13f7145110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439011750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1439011750
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2519126488
Short name T760
Test name
Test status
Simulation time 5209094632 ps
CPU time 3.52 seconds
Started May 19 01:34:08 PM PDT 24
Finished May 19 01:34:13 PM PDT 24
Peak memory 201680 kb
Host smart-8ea36e9b-4ea8-45ff-a8b6-17ece4eb713b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519126488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2519126488
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.4142103775
Short name T733
Test name
Test status
Simulation time 5722390098 ps
CPU time 8.38 seconds
Started May 19 01:34:20 PM PDT 24
Finished May 19 01:34:29 PM PDT 24
Peak memory 201660 kb
Host smart-4f48619f-f189-4fe2-9b34-bb43c6cbd29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142103775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.4142103775
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.4024609804
Short name T781
Test name
Test status
Simulation time 208648766826 ps
CPU time 516.79 seconds
Started May 19 01:34:14 PM PDT 24
Finished May 19 01:42:53 PM PDT 24
Peak memory 201820 kb
Host smart-9949c900-4e50-45f6-a019-259eef4f701e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024609804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.4024609804
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.670340064
Short name T40
Test name
Test status
Simulation time 301432554845 ps
CPU time 220.66 seconds
Started May 19 01:34:18 PM PDT 24
Finished May 19 01:38:00 PM PDT 24
Peak memory 202288 kb
Host smart-55b09030-349b-4842-854e-19d697617529
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670340064 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.670340064
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3880740363
Short name T688
Test name
Test status
Simulation time 404443790 ps
CPU time 0.75 seconds
Started May 19 01:33:36 PM PDT 24
Finished May 19 01:33:38 PM PDT 24
Peak memory 201444 kb
Host smart-c6cf4bd9-03f5-4faf-b609-a9ba3b04ba0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880740363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3880740363
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.296962742
Short name T295
Test name
Test status
Simulation time 345887325774 ps
CPU time 818.27 seconds
Started May 19 01:33:53 PM PDT 24
Finished May 19 01:47:33 PM PDT 24
Peak memory 201888 kb
Host smart-75855fe2-846a-4661-9b50-fb085501fe55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296962742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.296962742
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2550791401
Short name T519
Test name
Test status
Simulation time 158093110507 ps
CPU time 94.36 seconds
Started May 19 01:33:33 PM PDT 24
Finished May 19 01:35:10 PM PDT 24
Peak memory 201808 kb
Host smart-2e73da95-dd76-40bf-9b57-d050abe6d818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550791401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2550791401
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1979697133
Short name T452
Test name
Test status
Simulation time 325346661887 ps
CPU time 720.5 seconds
Started May 19 01:33:30 PM PDT 24
Finished May 19 01:45:33 PM PDT 24
Peak memory 201972 kb
Host smart-b71813a1-03b2-40c0-8f03-896ef4ff304c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979697133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1979697133
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1923027853
Short name T211
Test name
Test status
Simulation time 327422230585 ps
CPU time 258.05 seconds
Started May 19 01:33:32 PM PDT 24
Finished May 19 01:37:52 PM PDT 24
Peak memory 201816 kb
Host smart-e493ed80-b72c-4a96-859d-4f9db9140e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923027853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1923027853
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.4214758089
Short name T405
Test name
Test status
Simulation time 161816112154 ps
CPU time 347.55 seconds
Started May 19 01:33:51 PM PDT 24
Finished May 19 01:39:40 PM PDT 24
Peak memory 201824 kb
Host smart-79eec484-0c16-490c-96ab-a155e57bcc7c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214758089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.4214758089
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.568046527
Short name T588
Test name
Test status
Simulation time 342434581533 ps
CPU time 245.31 seconds
Started May 19 01:33:27 PM PDT 24
Finished May 19 01:37:36 PM PDT 24
Peak memory 201788 kb
Host smart-85c65157-dbe4-4eaf-bcdf-97e4df53d19c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568046527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.568046527
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.239358346
Short name T188
Test name
Test status
Simulation time 199162441851 ps
CPU time 127.79 seconds
Started May 19 01:33:34 PM PDT 24
Finished May 19 01:35:44 PM PDT 24
Peak memory 201796 kb
Host smart-784ccf7d-7b41-4298-b077-da79bb158e5d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239358346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.239358346
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1081180419
Short name T462
Test name
Test status
Simulation time 91730490389 ps
CPU time 455.98 seconds
Started May 19 01:33:44 PM PDT 24
Finished May 19 01:41:21 PM PDT 24
Peak memory 202196 kb
Host smart-c07d3682-5372-4fe9-9454-684ffa90a322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081180419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1081180419
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.191751165
Short name T1
Test name
Test status
Simulation time 29415064285 ps
CPU time 32.6 seconds
Started May 19 01:33:30 PM PDT 24
Finished May 19 01:34:05 PM PDT 24
Peak memory 201808 kb
Host smart-3444d89a-7500-42aa-abf4-29d31d0b9f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191751165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.191751165
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2275396443
Short name T468
Test name
Test status
Simulation time 4521995860 ps
CPU time 6.26 seconds
Started May 19 01:33:38 PM PDT 24
Finished May 19 01:33:45 PM PDT 24
Peak memory 201644 kb
Host smart-a16960e4-195a-4afe-9138-cabaedb5b823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275396443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2275396443
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1751123236
Short name T56
Test name
Test status
Simulation time 8288845131 ps
CPU time 6.35 seconds
Started May 19 01:33:42 PM PDT 24
Finished May 19 01:33:49 PM PDT 24
Peak memory 218420 kb
Host smart-49307da3-4643-452d-bf10-dd213ee1527e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751123236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1751123236
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2061091290
Short name T788
Test name
Test status
Simulation time 5753118348 ps
CPU time 14.42 seconds
Started May 19 01:33:29 PM PDT 24
Finished May 19 01:33:47 PM PDT 24
Peak memory 201624 kb
Host smart-5fdd2854-fb12-4d6b-bdaf-8f43c3c729cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061091290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2061091290
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2949671372
Short name T584
Test name
Test status
Simulation time 201786412526 ps
CPU time 121.91 seconds
Started May 19 01:33:38 PM PDT 24
Finished May 19 01:35:42 PM PDT 24
Peak memory 201784 kb
Host smart-f4c0baa1-a7bf-4291-b633-d8ca1ba9a1b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949671372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2949671372
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3074451238
Short name T362
Test name
Test status
Simulation time 101580069861 ps
CPU time 197.35 seconds
Started May 19 01:33:44 PM PDT 24
Finished May 19 01:37:03 PM PDT 24
Peak memory 202456 kb
Host smart-2125f10b-b9fe-4624-a153-886a3007ca38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074451238 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3074451238
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2387397395
Short name T373
Test name
Test status
Simulation time 482969286 ps
CPU time 1.05 seconds
Started May 19 01:34:14 PM PDT 24
Finished May 19 01:34:18 PM PDT 24
Peak memory 201480 kb
Host smart-08632d2d-a688-4d70-bf5c-7fa2736b5b76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387397395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2387397395
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.850187577
Short name T173
Test name
Test status
Simulation time 517259770692 ps
CPU time 630.06 seconds
Started May 19 01:34:18 PM PDT 24
Finished May 19 01:44:50 PM PDT 24
Peak memory 201828 kb
Host smart-b8d67424-102b-4a9a-8a1f-4223b03f5ec9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850187577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.850187577
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.574661493
Short name T357
Test name
Test status
Simulation time 356027556434 ps
CPU time 435.67 seconds
Started May 19 01:34:18 PM PDT 24
Finished May 19 01:41:35 PM PDT 24
Peak memory 201832 kb
Host smart-bddf68e2-1205-4e81-a0bc-3f13d0b3a7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574661493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.574661493
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.85150191
Short name T702
Test name
Test status
Simulation time 320131650971 ps
CPU time 195.73 seconds
Started May 19 01:34:17 PM PDT 24
Finished May 19 01:37:35 PM PDT 24
Peak memory 201836 kb
Host smart-00dd7460-7c52-48f2-b794-d60a098775e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85150191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.85150191
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2711496490
Short name T541
Test name
Test status
Simulation time 324115269008 ps
CPU time 98.47 seconds
Started May 19 01:34:16 PM PDT 24
Finished May 19 01:35:56 PM PDT 24
Peak memory 201820 kb
Host smart-7e8a62a4-b221-404b-9a7b-cd5d6441ee3b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711496490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2711496490
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3438572988
Short name T684
Test name
Test status
Simulation time 496002585169 ps
CPU time 296.7 seconds
Started May 19 01:34:18 PM PDT 24
Finished May 19 01:39:16 PM PDT 24
Peak memory 201804 kb
Host smart-2ff60bf9-8a76-49d9-9dce-cb58ddbf0f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438572988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3438572988
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2502164466
Short name T555
Test name
Test status
Simulation time 329507969983 ps
CPU time 794.4 seconds
Started May 19 01:34:07 PM PDT 24
Finished May 19 01:47:23 PM PDT 24
Peak memory 201808 kb
Host smart-3bec1aea-4500-482d-9caa-a68807744f40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502164466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2502164466
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.1160834256
Short name T290
Test name
Test status
Simulation time 366975802869 ps
CPU time 452.04 seconds
Started May 19 01:34:20 PM PDT 24
Finished May 19 01:41:52 PM PDT 24
Peak memory 201912 kb
Host smart-baacea5c-cbed-4e66-b6b6-3cac9e97fa3f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160834256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.1160834256
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.48639661
Short name T432
Test name
Test status
Simulation time 610223734829 ps
CPU time 344.32 seconds
Started May 19 01:34:06 PM PDT 24
Finished May 19 01:39:52 PM PDT 24
Peak memory 201916 kb
Host smart-6e7df36c-a3fa-4378-9876-735d5e359ef4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48639661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.a
dc_ctrl_filters_wakeup_fixed.48639661
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2230511471
Short name T748
Test name
Test status
Simulation time 119375179606 ps
CPU time 568.39 seconds
Started May 19 01:34:23 PM PDT 24
Finished May 19 01:43:52 PM PDT 24
Peak memory 202120 kb
Host smart-8bf53bac-5165-47c7-9fc4-8ac3d2c0253d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230511471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2230511471
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3491927578
Short name T513
Test name
Test status
Simulation time 24666516635 ps
CPU time 57.9 seconds
Started May 19 01:34:07 PM PDT 24
Finished May 19 01:35:07 PM PDT 24
Peak memory 201660 kb
Host smart-a2a7fc05-a8b8-4388-b952-c52ce1747872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491927578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3491927578
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.519866841
Short name T683
Test name
Test status
Simulation time 3804109384 ps
CPU time 5.73 seconds
Started May 19 01:34:15 PM PDT 24
Finished May 19 01:34:23 PM PDT 24
Peak memory 201572 kb
Host smart-73440e8d-f128-4265-acdf-df20a7e087d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519866841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.519866841
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2056467209
Short name T445
Test name
Test status
Simulation time 5786910761 ps
CPU time 15.05 seconds
Started May 19 01:34:16 PM PDT 24
Finished May 19 01:34:33 PM PDT 24
Peak memory 201652 kb
Host smart-492f67ae-b9c1-4dee-9d3b-08a44b58d008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056467209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2056467209
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3645433020
Short name T639
Test name
Test status
Simulation time 57865493621 ps
CPU time 172.04 seconds
Started May 19 01:34:09 PM PDT 24
Finished May 19 01:37:02 PM PDT 24
Peak memory 210316 kb
Host smart-bef1b96b-65b3-4baf-ad2e-25216fce380f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645433020 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3645433020
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1987985815
Short name T14
Test name
Test status
Simulation time 290577261 ps
CPU time 1.22 seconds
Started May 19 01:34:13 PM PDT 24
Finished May 19 01:34:16 PM PDT 24
Peak memory 201516 kb
Host smart-7fda75ac-bbaa-4e8b-a060-2611ca4e0c60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987985815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1987985815
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1692583959
Short name T334
Test name
Test status
Simulation time 329173598463 ps
CPU time 192.51 seconds
Started May 19 01:34:13 PM PDT 24
Finished May 19 01:37:27 PM PDT 24
Peak memory 201808 kb
Host smart-768310cd-f09b-4958-980d-32480c5e9cd3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692583959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1692583959
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2315744013
Short name T319
Test name
Test status
Simulation time 183109735845 ps
CPU time 446.53 seconds
Started May 19 01:34:12 PM PDT 24
Finished May 19 01:41:40 PM PDT 24
Peak memory 201820 kb
Host smart-cab529cd-b2da-4362-9b4e-d1a7558b7f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315744013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2315744013
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2072323063
Short name T632
Test name
Test status
Simulation time 169247532319 ps
CPU time 203.72 seconds
Started May 19 01:34:11 PM PDT 24
Finished May 19 01:37:36 PM PDT 24
Peak memory 201760 kb
Host smart-a54dd995-b667-4654-9e8e-6757c842a6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072323063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2072323063
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3004122421
Short name T649
Test name
Test status
Simulation time 165289007966 ps
CPU time 28.34 seconds
Started May 19 01:34:11 PM PDT 24
Finished May 19 01:34:41 PM PDT 24
Peak memory 201752 kb
Host smart-3a09e27f-c6e8-449a-a70e-9bdde2857898
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004122421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3004122421
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3328699290
Short name T207
Test name
Test status
Simulation time 490732191449 ps
CPU time 142.77 seconds
Started May 19 01:34:09 PM PDT 24
Finished May 19 01:36:33 PM PDT 24
Peak memory 202112 kb
Host smart-7a209d05-7171-4543-9cbc-a040daca95ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328699290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3328699290
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2771242503
Short name T583
Test name
Test status
Simulation time 329718825939 ps
CPU time 208.78 seconds
Started May 19 01:34:17 PM PDT 24
Finished May 19 01:37:48 PM PDT 24
Peak memory 201752 kb
Host smart-753b67fe-43a8-46e9-87a2-097c3d3e2602
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771242503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2771242503
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2111082633
Short name T311
Test name
Test status
Simulation time 537814597885 ps
CPU time 1224.69 seconds
Started May 19 01:34:08 PM PDT 24
Finished May 19 01:54:35 PM PDT 24
Peak memory 201848 kb
Host smart-3092e7fd-f229-4b51-94f3-4aa4c4d604b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111082633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2111082633
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.680286348
Short name T101
Test name
Test status
Simulation time 399375069548 ps
CPU time 229.01 seconds
Started May 19 01:34:14 PM PDT 24
Finished May 19 01:38:06 PM PDT 24
Peak memory 201816 kb
Host smart-2730360e-785e-475b-8c4b-9da1888db893
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680286348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.680286348
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1135959963
Short name T524
Test name
Test status
Simulation time 98088112785 ps
CPU time 362.26 seconds
Started May 19 01:34:13 PM PDT 24
Finished May 19 01:40:17 PM PDT 24
Peak memory 202200 kb
Host smart-4a5ac4c7-4164-4ac5-9dcd-b0c59dd0856a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135959963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1135959963
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.459600693
Short name T517
Test name
Test status
Simulation time 23239241740 ps
CPU time 26.12 seconds
Started May 19 01:34:11 PM PDT 24
Finished May 19 01:34:38 PM PDT 24
Peak memory 201520 kb
Host smart-4e475103-34d4-4e89-8934-810193f06db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459600693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.459600693
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3542013412
Short name T454
Test name
Test status
Simulation time 4879348148 ps
CPU time 6.03 seconds
Started May 19 01:34:14 PM PDT 24
Finished May 19 01:34:22 PM PDT 24
Peak memory 201912 kb
Host smart-ce883334-aa20-44e5-b01c-b92e0e2b55ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542013412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3542013412
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.411109355
Short name T511
Test name
Test status
Simulation time 6033068541 ps
CPU time 7.89 seconds
Started May 19 01:34:21 PM PDT 24
Finished May 19 01:34:29 PM PDT 24
Peak memory 201632 kb
Host smart-46269b4e-1e4d-4020-9614-f6242cae7da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411109355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.411109355
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2761892243
Short name T134
Test name
Test status
Simulation time 333509246145 ps
CPU time 374.92 seconds
Started May 19 01:34:09 PM PDT 24
Finished May 19 01:40:25 PM PDT 24
Peak memory 201788 kb
Host smart-7d0429b3-5f3d-4daf-929e-cbf1f02de57b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761892243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2761892243
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3009388488
Short name T336
Test name
Test status
Simulation time 455238107067 ps
CPU time 339.37 seconds
Started May 19 01:34:11 PM PDT 24
Finished May 19 01:39:52 PM PDT 24
Peak memory 210376 kb
Host smart-3ebf21ee-4610-466f-b92b-4881931b9328
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009388488 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3009388488
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3625114670
Short name T27
Test name
Test status
Simulation time 310366633 ps
CPU time 1.31 seconds
Started May 19 01:34:17 PM PDT 24
Finished May 19 01:34:20 PM PDT 24
Peak memory 201532 kb
Host smart-b98de0c5-44d3-4e6c-bd45-e7228d9a28d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625114670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3625114670
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.945816648
Short name T300
Test name
Test status
Simulation time 163120566279 ps
CPU time 394.41 seconds
Started May 19 01:34:12 PM PDT 24
Finished May 19 01:40:48 PM PDT 24
Peak memory 201836 kb
Host smart-89cb564f-7db2-4262-b03b-015c736b7825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945816648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.945816648
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3302838149
Short name T526
Test name
Test status
Simulation time 321006411439 ps
CPU time 725.24 seconds
Started May 19 01:34:14 PM PDT 24
Finished May 19 01:46:22 PM PDT 24
Peak memory 202048 kb
Host smart-0889fccd-bd0d-493b-9575-b89c96b6026c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302838149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3302838149
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1359661642
Short name T780
Test name
Test status
Simulation time 165178207587 ps
CPU time 105.66 seconds
Started May 19 01:34:08 PM PDT 24
Finished May 19 01:35:56 PM PDT 24
Peak memory 201760 kb
Host smart-9f65fbda-1fb4-4b6c-990e-2c442c616762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359661642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1359661642
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1016304000
Short name T390
Test name
Test status
Simulation time 161955829920 ps
CPU time 303.16 seconds
Started May 19 01:34:17 PM PDT 24
Finished May 19 01:39:22 PM PDT 24
Peak memory 201784 kb
Host smart-acadf0cf-084c-49aa-a3bb-0f041ad2d44d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016304000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1016304000
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.374833646
Short name T155
Test name
Test status
Simulation time 392770329895 ps
CPU time 179.66 seconds
Started May 19 01:34:17 PM PDT 24
Finished May 19 01:37:19 PM PDT 24
Peak memory 201916 kb
Host smart-587ee6a8-d373-4858-8e9c-7c977dadcbc1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374833646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.374833646
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3617645664
Short name T563
Test name
Test status
Simulation time 602265075832 ps
CPU time 1465.2 seconds
Started May 19 01:34:26 PM PDT 24
Finished May 19 01:58:52 PM PDT 24
Peak memory 201836 kb
Host smart-52297a46-c0be-4011-9038-4891df7a7e10
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617645664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3617645664
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3077059744
Short name T751
Test name
Test status
Simulation time 91631877421 ps
CPU time 375.56 seconds
Started May 19 01:34:15 PM PDT 24
Finished May 19 01:40:33 PM PDT 24
Peak memory 202124 kb
Host smart-83751881-d19e-4baf-a2d5-75af2fc99f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077059744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3077059744
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3537399380
Short name T395
Test name
Test status
Simulation time 37118219249 ps
CPU time 18.89 seconds
Started May 19 01:34:14 PM PDT 24
Finished May 19 01:34:35 PM PDT 24
Peak memory 201588 kb
Host smart-26d5c8cf-b41a-417d-940b-e4e46e6c2145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537399380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3537399380
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1036558129
Short name T554
Test name
Test status
Simulation time 2904867504 ps
CPU time 2.22 seconds
Started May 19 01:34:19 PM PDT 24
Finished May 19 01:34:22 PM PDT 24
Peak memory 201560 kb
Host smart-8c775d9a-e0ae-45da-80a8-48e61af6a284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036558129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1036558129
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3571252886
Short name T672
Test name
Test status
Simulation time 5887855791 ps
CPU time 3.94 seconds
Started May 19 01:34:20 PM PDT 24
Finished May 19 01:34:25 PM PDT 24
Peak memory 201624 kb
Host smart-533652ee-0956-410f-b90a-869a8c53e967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571252886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3571252886
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.4092853625
Short name T94
Test name
Test status
Simulation time 554399886 ps
CPU time 0.72 seconds
Started May 19 01:34:23 PM PDT 24
Finished May 19 01:34:24 PM PDT 24
Peak memory 201476 kb
Host smart-f8e9bbd2-22d5-4c9b-bdf4-f323cf1d87e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092853625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.4092853625
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2121288672
Short name T264
Test name
Test status
Simulation time 348675168576 ps
CPU time 784.09 seconds
Started May 19 01:34:13 PM PDT 24
Finished May 19 01:47:19 PM PDT 24
Peak memory 201804 kb
Host smart-ef7a4136-cfc7-44a3-86ce-8cd2e743a440
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121288672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2121288672
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2395633409
Short name T132
Test name
Test status
Simulation time 347891841711 ps
CPU time 736.45 seconds
Started May 19 01:34:12 PM PDT 24
Finished May 19 01:46:29 PM PDT 24
Peak memory 201828 kb
Host smart-3dc961ca-ff57-40cb-9321-251c19888af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395633409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2395633409
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3174503089
Short name T93
Test name
Test status
Simulation time 322137113055 ps
CPU time 686.41 seconds
Started May 19 01:34:15 PM PDT 24
Finished May 19 01:45:43 PM PDT 24
Peak memory 201760 kb
Host smart-bb3f0b83-bb66-4a4e-b24d-3362176dff8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174503089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3174503089
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2192451620
Short name T618
Test name
Test status
Simulation time 168999183114 ps
CPU time 354.58 seconds
Started May 19 01:34:15 PM PDT 24
Finished May 19 01:40:11 PM PDT 24
Peak memory 201740 kb
Host smart-f58ee5ca-73a3-440e-90b8-9d408f5f642c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192451620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2192451620
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2409055639
Short name T538
Test name
Test status
Simulation time 329604226610 ps
CPU time 154.59 seconds
Started May 19 01:34:15 PM PDT 24
Finished May 19 01:36:51 PM PDT 24
Peak memory 201736 kb
Host smart-31164a49-a001-43c9-9c4a-5d5e2543beef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409055639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2409055639
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3446186078
Short name T575
Test name
Test status
Simulation time 165968867824 ps
CPU time 214.9 seconds
Started May 19 01:34:16 PM PDT 24
Finished May 19 01:37:53 PM PDT 24
Peak memory 201756 kb
Host smart-cafa3567-ca93-488a-b979-55daf5bbba15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446186078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3446186078
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.24710387
Short name T332
Test name
Test status
Simulation time 378850694044 ps
CPU time 234.97 seconds
Started May 19 01:34:12 PM PDT 24
Finished May 19 01:38:08 PM PDT 24
Peak memory 202112 kb
Host smart-26569e3c-306a-4bdd-b687-81f86cf78632
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24710387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_w
akeup.24710387
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1253814098
Short name T377
Test name
Test status
Simulation time 201214721948 ps
CPU time 456.2 seconds
Started May 19 01:34:15 PM PDT 24
Finished May 19 01:41:53 PM PDT 24
Peak memory 201816 kb
Host smart-313fdbbd-e298-4988-98bb-24871995b301
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253814098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1253814098
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3009213580
Short name T648
Test name
Test status
Simulation time 128554614547 ps
CPU time 550.1 seconds
Started May 19 01:34:23 PM PDT 24
Finished May 19 01:43:34 PM PDT 24
Peak memory 202148 kb
Host smart-fc58d1b3-b62a-4fd3-84f7-c16ea2e0d49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009213580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3009213580
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1487855619
Short name T470
Test name
Test status
Simulation time 21825105952 ps
CPU time 13.51 seconds
Started May 19 01:34:23 PM PDT 24
Finished May 19 01:34:37 PM PDT 24
Peak memory 201604 kb
Host smart-e6762b47-e856-4013-83d9-6338b266b08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487855619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1487855619
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2091737658
Short name T83
Test name
Test status
Simulation time 3976080639 ps
CPU time 3.25 seconds
Started May 19 01:34:18 PM PDT 24
Finished May 19 01:34:23 PM PDT 24
Peak memory 201552 kb
Host smart-4360c831-5604-44af-86be-071af027364c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091737658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2091737658
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2722898593
Short name T388
Test name
Test status
Simulation time 5908381682 ps
CPU time 3.06 seconds
Started May 19 01:34:13 PM PDT 24
Finished May 19 01:34:18 PM PDT 24
Peak memory 201660 kb
Host smart-598a661c-aa15-4fe6-b049-76b94c8ead79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722898593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2722898593
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1531238224
Short name T531
Test name
Test status
Simulation time 270972483168 ps
CPU time 1021.59 seconds
Started May 19 01:34:21 PM PDT 24
Finished May 19 01:51:24 PM PDT 24
Peak memory 218504 kb
Host smart-dd8a3ebe-1ee9-4600-8c7a-2f22b8f2a9a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531238224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1531238224
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3371884387
Short name T376
Test name
Test status
Simulation time 393635980 ps
CPU time 1.08 seconds
Started May 19 01:34:26 PM PDT 24
Finished May 19 01:34:27 PM PDT 24
Peak memory 201520 kb
Host smart-a6131972-2dcf-49e9-aa93-ab6aa744a87c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371884387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3371884387
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3182372135
Short name T81
Test name
Test status
Simulation time 351977695657 ps
CPU time 115.11 seconds
Started May 19 01:34:30 PM PDT 24
Finished May 19 01:36:26 PM PDT 24
Peak memory 201800 kb
Host smart-a48bb85c-1ecb-4e91-9467-a98e9a287be0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182372135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3182372135
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.177702542
Short name T135
Test name
Test status
Simulation time 327894867510 ps
CPU time 50.97 seconds
Started May 19 01:34:23 PM PDT 24
Finished May 19 01:35:14 PM PDT 24
Peak memory 201820 kb
Host smart-82c927d1-ba2b-4c6d-9255-3af17a5bd14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177702542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.177702542
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3628659172
Short name T591
Test name
Test status
Simulation time 157117513981 ps
CPU time 355.05 seconds
Started May 19 01:34:32 PM PDT 24
Finished May 19 01:40:28 PM PDT 24
Peak memory 201796 kb
Host smart-794fba03-0487-42af-9563-9c171f1b533b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628659172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3628659172
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1537271580
Short name T343
Test name
Test status
Simulation time 334833558798 ps
CPU time 406.61 seconds
Started May 19 01:34:19 PM PDT 24
Finished May 19 01:41:07 PM PDT 24
Peak memory 201884 kb
Host smart-dbd155ab-774d-4bb9-a043-751b315bf0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537271580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1537271580
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1733076546
Short name T103
Test name
Test status
Simulation time 492343894659 ps
CPU time 1057.26 seconds
Started May 19 01:34:16 PM PDT 24
Finished May 19 01:51:55 PM PDT 24
Peak memory 202044 kb
Host smart-badff38f-726c-4256-be73-ca0fa52758b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733076546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1733076546
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1550358771
Short name T303
Test name
Test status
Simulation time 356508483417 ps
CPU time 498.68 seconds
Started May 19 01:34:22 PM PDT 24
Finished May 19 01:42:41 PM PDT 24
Peak memory 201812 kb
Host smart-07c90618-893e-4b53-aa55-47736a76bb3d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550358771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1550358771
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2945834772
Short name T453
Test name
Test status
Simulation time 391185393364 ps
CPU time 136.84 seconds
Started May 19 01:34:27 PM PDT 24
Finished May 19 01:36:45 PM PDT 24
Peak memory 201800 kb
Host smart-ba76bfff-c3dd-4c30-b792-97eaf69fff3a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945834772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2945834772
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1005887710
Short name T689
Test name
Test status
Simulation time 100270984160 ps
CPU time 453.54 seconds
Started May 19 01:34:24 PM PDT 24
Finished May 19 01:41:58 PM PDT 24
Peak memory 202084 kb
Host smart-710940b8-86f8-42ab-bb81-eaab776346c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005887710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1005887710
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2731180557
Short name T794
Test name
Test status
Simulation time 35896648938 ps
CPU time 16.84 seconds
Started May 19 01:34:26 PM PDT 24
Finished May 19 01:34:44 PM PDT 24
Peak memory 201648 kb
Host smart-aa8df0d2-4ff6-4e80-abe0-ddbd42d580f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731180557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2731180557
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.218038462
Short name T711
Test name
Test status
Simulation time 3099152508 ps
CPU time 2.52 seconds
Started May 19 01:34:21 PM PDT 24
Finished May 19 01:34:24 PM PDT 24
Peak memory 201540 kb
Host smart-40560103-85b0-4ef5-994c-106f537dd1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218038462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.218038462
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2862279940
Short name T425
Test name
Test status
Simulation time 5820454399 ps
CPU time 4.57 seconds
Started May 19 01:34:24 PM PDT 24
Finished May 19 01:34:29 PM PDT 24
Peak memory 201652 kb
Host smart-2c68c2eb-d478-4327-8573-ccadc70cce5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862279940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2862279940
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2922113886
Short name T150
Test name
Test status
Simulation time 337503693492 ps
CPU time 150.88 seconds
Started May 19 01:34:21 PM PDT 24
Finished May 19 01:36:52 PM PDT 24
Peak memory 201916 kb
Host smart-4a3ffed3-6cbe-439b-b00d-2aeee205859b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922113886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2922113886
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3329451945
Short name T700
Test name
Test status
Simulation time 202296988603 ps
CPU time 152.75 seconds
Started May 19 01:34:28 PM PDT 24
Finished May 19 01:37:02 PM PDT 24
Peak memory 210156 kb
Host smart-17f78076-7bbb-4d8a-a542-f58d91625296
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329451945 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3329451945
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1517180597
Short name T428
Test name
Test status
Simulation time 341179327 ps
CPU time 0.97 seconds
Started May 19 01:34:32 PM PDT 24
Finished May 19 01:34:33 PM PDT 24
Peak memory 201420 kb
Host smart-3ee9dbfa-a5e8-420e-9b75-d82cb2d8764c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517180597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1517180597
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2292988052
Short name T324
Test name
Test status
Simulation time 323571712881 ps
CPU time 383.31 seconds
Started May 19 01:34:27 PM PDT 24
Finished May 19 01:40:51 PM PDT 24
Peak memory 201900 kb
Host smart-6a791aa1-deeb-4403-9eb7-9543acde2ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292988052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2292988052
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3614535470
Short name T675
Test name
Test status
Simulation time 164725430244 ps
CPU time 163.91 seconds
Started May 19 01:34:26 PM PDT 24
Finished May 19 01:37:10 PM PDT 24
Peak memory 201700 kb
Host smart-ba9998f1-21d0-4d93-8f0a-2dcfd7797eb9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614535470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3614535470
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2110278592
Short name T540
Test name
Test status
Simulation time 333374851034 ps
CPU time 871.87 seconds
Started May 19 01:34:30 PM PDT 24
Finished May 19 01:49:03 PM PDT 24
Peak memory 201860 kb
Host smart-b7452972-b0dd-48f7-8e43-84c18c55f507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110278592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2110278592
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3460350059
Short name T695
Test name
Test status
Simulation time 490220999482 ps
CPU time 1084.07 seconds
Started May 19 01:34:30 PM PDT 24
Finished May 19 01:52:34 PM PDT 24
Peak memory 201796 kb
Host smart-9254d54c-9196-46e2-b230-3114420b6802
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460350059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3460350059
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2246648721
Short name T443
Test name
Test status
Simulation time 395605853234 ps
CPU time 130.29 seconds
Started May 19 01:34:27 PM PDT 24
Finished May 19 01:36:38 PM PDT 24
Peak memory 201828 kb
Host smart-caef0981-2b4b-4943-88fb-172feba9b5be
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246648721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2246648721
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1185639012
Short name T82
Test name
Test status
Simulation time 111718357284 ps
CPU time 485.51 seconds
Started May 19 01:34:30 PM PDT 24
Finished May 19 01:42:36 PM PDT 24
Peak memory 202072 kb
Host smart-5c79f164-94c1-4267-952d-eef9893d2817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185639012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1185639012
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.4264227696
Short name T475
Test name
Test status
Simulation time 35534170903 ps
CPU time 22.91 seconds
Started May 19 01:34:32 PM PDT 24
Finished May 19 01:34:55 PM PDT 24
Peak memory 201648 kb
Host smart-c63dc563-5762-4fbe-a523-6f3cac00ed95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264227696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.4264227696
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.157695958
Short name T754
Test name
Test status
Simulation time 3639167936 ps
CPU time 9.29 seconds
Started May 19 01:34:30 PM PDT 24
Finished May 19 01:34:40 PM PDT 24
Peak memory 201556 kb
Host smart-7ce3803a-00e5-47a3-b03e-df3a668969e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157695958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.157695958
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1412682422
Short name T617
Test name
Test status
Simulation time 6002178608 ps
CPU time 7.95 seconds
Started May 19 01:34:26 PM PDT 24
Finished May 19 01:34:35 PM PDT 24
Peak memory 201868 kb
Host smart-1190be5d-2e8e-4bee-bd44-407060057361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412682422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1412682422
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1784598761
Short name T359
Test name
Test status
Simulation time 566550081850 ps
CPU time 305.73 seconds
Started May 19 01:34:31 PM PDT 24
Finished May 19 01:39:37 PM PDT 24
Peak memory 201780 kb
Host smart-d74aa244-a579-4edc-b18e-1b96b1892485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784598761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1784598761
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1317122229
Short name T597
Test name
Test status
Simulation time 304601661 ps
CPU time 1.29 seconds
Started May 19 01:34:43 PM PDT 24
Finished May 19 01:34:45 PM PDT 24
Peak memory 201492 kb
Host smart-f794ac75-7792-4566-8eb6-a7ea25f33d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317122229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1317122229
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.371466459
Short name T299
Test name
Test status
Simulation time 519225319577 ps
CPU time 342.48 seconds
Started May 19 01:34:39 PM PDT 24
Finished May 19 01:40:22 PM PDT 24
Peak memory 201832 kb
Host smart-efe6965c-b5cf-444b-82bb-bfdfe89c05ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371466459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.371466459
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2018761621
Short name T665
Test name
Test status
Simulation time 165821631854 ps
CPU time 302.5 seconds
Started May 19 01:34:32 PM PDT 24
Finished May 19 01:39:35 PM PDT 24
Peak memory 201836 kb
Host smart-b4d80654-0c17-4ba7-8b5b-c4d9de4cf3e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018761621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2018761621
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2895834435
Short name T722
Test name
Test status
Simulation time 162041347294 ps
CPU time 181.48 seconds
Started May 19 01:34:35 PM PDT 24
Finished May 19 01:37:37 PM PDT 24
Peak memory 201800 kb
Host smart-6f85fe83-9cb6-41c7-81d4-8983da90f3b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895834435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2895834435
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2272525703
Short name T498
Test name
Test status
Simulation time 197295092524 ps
CPU time 431.58 seconds
Started May 19 01:34:35 PM PDT 24
Finished May 19 01:41:47 PM PDT 24
Peak memory 201772 kb
Host smart-ee40ba75-67ab-4829-94af-a2a8d776e811
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272525703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2272525703
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3802902965
Short name T366
Test name
Test status
Simulation time 90048611699 ps
CPU time 501.97 seconds
Started May 19 01:34:46 PM PDT 24
Finished May 19 01:43:08 PM PDT 24
Peak memory 202076 kb
Host smart-35c2566c-e5fc-4b43-990f-62a87e05eb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802902965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3802902965
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.12216139
Short name T582
Test name
Test status
Simulation time 43789106911 ps
CPU time 52.76 seconds
Started May 19 01:34:36 PM PDT 24
Finished May 19 01:35:29 PM PDT 24
Peak memory 201648 kb
Host smart-4cfaceac-4532-4b32-9387-fa37a9a0fedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12216139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.12216139
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2896082394
Short name T503
Test name
Test status
Simulation time 3113197711 ps
CPU time 2.11 seconds
Started May 19 01:34:38 PM PDT 24
Finished May 19 01:34:41 PM PDT 24
Peak memory 201576 kb
Host smart-8c8d2bff-1c1f-474e-85a1-dece44f7471b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896082394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2896082394
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3152296071
Short name T713
Test name
Test status
Simulation time 5853439721 ps
CPU time 14.87 seconds
Started May 19 01:34:30 PM PDT 24
Finished May 19 01:34:46 PM PDT 24
Peak memory 201628 kb
Host smart-fad4bc05-13fd-4fd5-9d59-8c57127321e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152296071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3152296071
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2225776351
Short name T368
Test name
Test status
Simulation time 126456796648 ps
CPU time 256.16 seconds
Started May 19 01:34:41 PM PDT 24
Finished May 19 01:38:57 PM PDT 24
Peak memory 202112 kb
Host smart-5c863b32-871b-469c-8d6d-d352a08fee0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225776351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2225776351
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3980720521
Short name T38
Test name
Test status
Simulation time 10583482280 ps
CPU time 26.13 seconds
Started May 19 01:34:44 PM PDT 24
Finished May 19 01:35:10 PM PDT 24
Peak memory 201872 kb
Host smart-63f8a448-3383-4a3a-b4fa-092477805233
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980720521 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3980720521
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2538266099
Short name T567
Test name
Test status
Simulation time 304996588 ps
CPU time 0.79 seconds
Started May 19 01:34:56 PM PDT 24
Finished May 19 01:34:59 PM PDT 24
Peak memory 201772 kb
Host smart-cdc9784d-194b-4a34-bbba-7f0e91c3f492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538266099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2538266099
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1907334247
Short name T587
Test name
Test status
Simulation time 166288250020 ps
CPU time 109.56 seconds
Started May 19 01:34:55 PM PDT 24
Finished May 19 01:36:45 PM PDT 24
Peak memory 201812 kb
Host smart-3a0dd47d-d33e-4de2-b79d-d71ebc4e3cdd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907334247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1907334247
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.4105621960
Short name T650
Test name
Test status
Simulation time 329035994102 ps
CPU time 211.56 seconds
Started May 19 01:34:46 PM PDT 24
Finished May 19 01:38:18 PM PDT 24
Peak memory 201768 kb
Host smart-5224976c-9698-458a-b8ca-7d71384b33b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105621960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.4105621960
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.379151645
Short name T159
Test name
Test status
Simulation time 342001262249 ps
CPU time 202.22 seconds
Started May 19 01:34:43 PM PDT 24
Finished May 19 01:38:06 PM PDT 24
Peak memory 201744 kb
Host smart-470db77b-4af7-4025-8937-f54b451fdab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379151645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.379151645
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.4184516857
Short name T545
Test name
Test status
Simulation time 157631048840 ps
CPU time 308.62 seconds
Started May 19 01:34:41 PM PDT 24
Finished May 19 01:39:50 PM PDT 24
Peak memory 201868 kb
Host smart-32074666-4a20-4d26-8228-f19c58dea9a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184516857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.4184516857
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.306975943
Short name T657
Test name
Test status
Simulation time 574571388951 ps
CPU time 1394.23 seconds
Started May 19 01:34:56 PM PDT 24
Finished May 19 01:58:12 PM PDT 24
Peak memory 201856 kb
Host smart-30f71316-731d-4812-8d98-86d9dc2619ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306975943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.306975943
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.440429144
Short name T375
Test name
Test status
Simulation time 389537382228 ps
CPU time 429.1 seconds
Started May 19 01:34:55 PM PDT 24
Finished May 19 01:42:04 PM PDT 24
Peak memory 201716 kb
Host smart-fbd7ba7b-3f8e-4016-8f95-c41ae84f6fd0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440429144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.440429144
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2008455759
Short name T241
Test name
Test status
Simulation time 61350156548 ps
CPU time 367.53 seconds
Started May 19 01:34:54 PM PDT 24
Finished May 19 01:41:02 PM PDT 24
Peak memory 202092 kb
Host smart-c7adee21-4e34-417e-a9b0-8a96de5e9fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008455759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2008455759
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.749851182
Short name T490
Test name
Test status
Simulation time 29993334825 ps
CPU time 71.2 seconds
Started May 19 01:34:57 PM PDT 24
Finished May 19 01:36:10 PM PDT 24
Peak memory 201608 kb
Host smart-879800e6-7a99-4009-b31b-372f2e94fd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749851182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.749851182
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.389226072
Short name T420
Test name
Test status
Simulation time 4921487523 ps
CPU time 3.05 seconds
Started May 19 01:34:56 PM PDT 24
Finished May 19 01:35:01 PM PDT 24
Peak memory 201592 kb
Host smart-a8c9a7d5-b031-44c2-82d6-4d255c44b8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389226072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.389226072
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2908057680
Short name T532
Test name
Test status
Simulation time 5818272064 ps
CPU time 3.17 seconds
Started May 19 01:34:44 PM PDT 24
Finished May 19 01:34:48 PM PDT 24
Peak memory 201592 kb
Host smart-bfacf16a-56e4-4998-9b4b-100f923a8e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908057680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2908057680
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3501247252
Short name T263
Test name
Test status
Simulation time 224689325122 ps
CPU time 265.43 seconds
Started May 19 01:34:55 PM PDT 24
Finished May 19 01:39:22 PM PDT 24
Peak memory 210392 kb
Host smart-d6ed1987-6331-483c-8ad4-964d088e5c33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501247252 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3501247252
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.48475413
Short name T690
Test name
Test status
Simulation time 396267154 ps
CPU time 1.09 seconds
Started May 19 01:34:55 PM PDT 24
Finished May 19 01:34:56 PM PDT 24
Peak memory 201516 kb
Host smart-b9aaf45a-1c70-48b3-b2ec-351f6a1391b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48475413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.48475413
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1978490940
Short name T351
Test name
Test status
Simulation time 168199411149 ps
CPU time 389 seconds
Started May 19 01:34:55 PM PDT 24
Finished May 19 01:41:25 PM PDT 24
Peak memory 201900 kb
Host smart-db85226e-0f09-4843-8443-f5f8fd815765
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978490940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1978490940
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3759729858
Short name T205
Test name
Test status
Simulation time 546824294154 ps
CPU time 395.77 seconds
Started May 19 01:34:56 PM PDT 24
Finished May 19 01:41:34 PM PDT 24
Peak memory 201824 kb
Host smart-966d9728-c866-475c-8c98-6ec5661bd057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759729858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3759729858
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.589628483
Short name T589
Test name
Test status
Simulation time 326593833691 ps
CPU time 319.55 seconds
Started May 19 01:34:55 PM PDT 24
Finished May 19 01:40:17 PM PDT 24
Peak memory 201884 kb
Host smart-5c7f6f46-4425-4e59-82e6-0d3cb7ce609d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589628483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.589628483
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2705925509
Short name T6
Test name
Test status
Simulation time 161538537827 ps
CPU time 189.38 seconds
Started May 19 01:34:55 PM PDT 24
Finished May 19 01:38:06 PM PDT 24
Peak memory 201816 kb
Host smart-cbdcb1f6-f121-47d8-a309-d13a93a71b65
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705925509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2705925509
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.74015356
Short name T766
Test name
Test status
Simulation time 495061877293 ps
CPU time 1136.73 seconds
Started May 19 01:34:57 PM PDT 24
Finished May 19 01:53:55 PM PDT 24
Peak memory 201760 kb
Host smart-68fef455-923a-4ac2-97a9-10447d213863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74015356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.74015356
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.927348292
Short name T756
Test name
Test status
Simulation time 492956307953 ps
CPU time 1096.42 seconds
Started May 19 01:34:56 PM PDT 24
Finished May 19 01:53:14 PM PDT 24
Peak memory 201784 kb
Host smart-5d184855-c24e-41e6-bcb3-ac2dc14100d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=927348292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.927348292
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.512476549
Short name T165
Test name
Test status
Simulation time 173154143142 ps
CPU time 372.62 seconds
Started May 19 01:34:57 PM PDT 24
Finished May 19 01:41:11 PM PDT 24
Peak memory 201900 kb
Host smart-28afbada-b476-4885-b13f-69a6f3f13aa9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512476549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.512476549
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.221858071
Short name T594
Test name
Test status
Simulation time 619012424439 ps
CPU time 428.58 seconds
Started May 19 01:34:56 PM PDT 24
Finished May 19 01:42:06 PM PDT 24
Peak memory 201768 kb
Host smart-970bb679-6bb0-47e6-bf29-155add1c88f9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221858071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.221858071
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2587285610
Short name T225
Test name
Test status
Simulation time 69038792373 ps
CPU time 372.1 seconds
Started May 19 01:34:57 PM PDT 24
Finished May 19 01:41:10 PM PDT 24
Peak memory 202096 kb
Host smart-5cd5c0f9-f80b-4c1c-b4bb-d901c464aff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587285610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2587285610
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1972816008
Short name T558
Test name
Test status
Simulation time 40401163659 ps
CPU time 89.28 seconds
Started May 19 01:34:57 PM PDT 24
Finished May 19 01:36:28 PM PDT 24
Peak memory 201588 kb
Host smart-6674ed2f-1843-4c95-94d2-8c1fc00b38e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972816008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1972816008
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2232558600
Short name T685
Test name
Test status
Simulation time 4081120294 ps
CPU time 10.85 seconds
Started May 19 01:34:55 PM PDT 24
Finished May 19 01:35:07 PM PDT 24
Peak memory 201580 kb
Host smart-6676302d-1353-4c0c-a928-adb6669f3843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232558600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2232558600
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.756600602
Short name T779
Test name
Test status
Simulation time 5740509031 ps
CPU time 3.81 seconds
Started May 19 01:34:56 PM PDT 24
Finished May 19 01:35:01 PM PDT 24
Peak memory 201612 kb
Host smart-4ddb3ed9-13f2-4f40-be37-3368eae9f328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756600602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.756600602
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.928707462
Short name T643
Test name
Test status
Simulation time 9929013379 ps
CPU time 7.58 seconds
Started May 19 01:34:56 PM PDT 24
Finished May 19 01:35:05 PM PDT 24
Peak memory 201660 kb
Host smart-8e7544d8-859d-44fe-9293-d7801aa48c5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928707462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
928707462
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.4126478853
Short name T229
Test name
Test status
Simulation time 131729420747 ps
CPU time 400.07 seconds
Started May 19 01:34:56 PM PDT 24
Finished May 19 01:41:38 PM PDT 24
Peak memory 210412 kb
Host smart-f09567df-fee6-479f-8482-4b3d257c99cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126478853 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.4126478853
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.119827108
Short name T412
Test name
Test status
Simulation time 437144141 ps
CPU time 1.62 seconds
Started May 19 01:35:01 PM PDT 24
Finished May 19 01:35:04 PM PDT 24
Peak memory 201488 kb
Host smart-934f66a9-17d8-46f4-a36b-57b6e6c8398f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119827108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.119827108
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.66182655
Short name T749
Test name
Test status
Simulation time 534184439607 ps
CPU time 1195.88 seconds
Started May 19 01:34:57 PM PDT 24
Finished May 19 01:54:55 PM PDT 24
Peak memory 201748 kb
Host smart-809ef891-f615-410c-a5ae-13dc29cd0896
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66182655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gatin
g.66182655
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1402216028
Short name T335
Test name
Test status
Simulation time 325053228689 ps
CPU time 74.75 seconds
Started May 19 01:34:57 PM PDT 24
Finished May 19 01:36:13 PM PDT 24
Peak memory 201744 kb
Host smart-560c717a-def6-4cc8-b885-92550e4a2df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402216028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1402216028
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2014844495
Short name T784
Test name
Test status
Simulation time 325237527222 ps
CPU time 376.78 seconds
Started May 19 01:34:56 PM PDT 24
Finished May 19 01:41:15 PM PDT 24
Peak memory 201800 kb
Host smart-f6b4d8cf-946b-4029-adf7-5e9d8fbff243
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014844495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2014844495
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.162544826
Short name T325
Test name
Test status
Simulation time 166747557566 ps
CPU time 32.17 seconds
Started May 19 01:34:57 PM PDT 24
Finished May 19 01:35:31 PM PDT 24
Peak memory 201808 kb
Host smart-026b5fd1-1bd5-4783-a26d-4cd2d6f9655d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162544826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.162544826
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1022168692
Short name T444
Test name
Test status
Simulation time 488704678848 ps
CPU time 516.65 seconds
Started May 19 01:34:56 PM PDT 24
Finished May 19 01:43:35 PM PDT 24
Peak memory 202048 kb
Host smart-3e2c86b3-90c2-4527-9b08-d148883789d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022168692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1022168692
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3127051036
Short name T349
Test name
Test status
Simulation time 621269803925 ps
CPU time 1351.63 seconds
Started May 19 01:35:06 PM PDT 24
Finished May 19 01:57:38 PM PDT 24
Peak memory 201812 kb
Host smart-f790ec35-c2a5-40fb-832d-9e3fe28f6b68
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127051036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3127051036
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1545748935
Short name T785
Test name
Test status
Simulation time 406369643091 ps
CPU time 87.15 seconds
Started May 19 01:34:56 PM PDT 24
Finished May 19 01:36:24 PM PDT 24
Peak memory 201824 kb
Host smart-6a3f09e6-8c24-43da-a0af-6ccd639e56c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545748935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1545748935
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2747051043
Short name T622
Test name
Test status
Simulation time 116041192257 ps
CPU time 380.33 seconds
Started May 19 01:34:57 PM PDT 24
Finished May 19 01:41:19 PM PDT 24
Peak memory 202172 kb
Host smart-649e3743-1259-456a-82fc-56a443afdeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747051043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2747051043
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.3359378639
Short name T701
Test name
Test status
Simulation time 41690137078 ps
CPU time 16.3 seconds
Started May 19 01:34:57 PM PDT 24
Finished May 19 01:35:15 PM PDT 24
Peak memory 201620 kb
Host smart-5f00ebf0-ef65-423e-984a-a31e1c891273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359378639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3359378639
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.690288268
Short name T562
Test name
Test status
Simulation time 4525404465 ps
CPU time 11.62 seconds
Started May 19 01:34:55 PM PDT 24
Finished May 19 01:35:08 PM PDT 24
Peak memory 201644 kb
Host smart-dca8be5c-da20-4960-bf2a-b63b9bb674c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690288268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.690288268
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1332918939
Short name T771
Test name
Test status
Simulation time 5695018629 ps
CPU time 13.37 seconds
Started May 19 01:34:55 PM PDT 24
Finished May 19 01:35:10 PM PDT 24
Peak memory 201628 kb
Host smart-88c59464-247b-4054-9a84-7403464b682c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332918939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1332918939
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2616294813
Short name T414
Test name
Test status
Simulation time 216285504957 ps
CPU time 313.84 seconds
Started May 19 01:35:01 PM PDT 24
Finished May 19 01:40:16 PM PDT 24
Peak memory 201800 kb
Host smart-fd142ac3-bf00-4b3e-939a-023c816c7da9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616294813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2616294813
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1410298808
Short name T358
Test name
Test status
Simulation time 173054545492 ps
CPU time 386.01 seconds
Started May 19 01:34:56 PM PDT 24
Finished May 19 01:41:24 PM PDT 24
Peak memory 210784 kb
Host smart-dc2763a6-8eef-419f-973a-8e3090a6b61c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410298808 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1410298808
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3974486240
Short name T397
Test name
Test status
Simulation time 339380837 ps
CPU time 1.47 seconds
Started May 19 01:33:35 PM PDT 24
Finished May 19 01:33:39 PM PDT 24
Peak memory 201468 kb
Host smart-2d1f1050-dc0b-4a5f-a1ec-00f3ca9735fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974486240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3974486240
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.4023055224
Short name T90
Test name
Test status
Simulation time 363996362147 ps
CPU time 216.64 seconds
Started May 19 01:33:56 PM PDT 24
Finished May 19 01:37:34 PM PDT 24
Peak memory 201844 kb
Host smart-212d48ef-2af8-4504-ac2a-fee2280ba53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023055224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.4023055224
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.730572808
Short name T105
Test name
Test status
Simulation time 163959323409 ps
CPU time 103.13 seconds
Started May 19 01:33:39 PM PDT 24
Finished May 19 01:35:24 PM PDT 24
Peak memory 201840 kb
Host smart-e05f6a6b-a253-422b-b8f2-57236c251cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730572808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.730572808
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.1749780391
Short name T491
Test name
Test status
Simulation time 327975317577 ps
CPU time 729.65 seconds
Started May 19 01:33:36 PM PDT 24
Finished May 19 01:45:47 PM PDT 24
Peak memory 201788 kb
Host smart-9e0ef0ff-f72a-4dbd-bbbc-a2f0a520ca98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749780391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.1749780391
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2057481302
Short name T9
Test name
Test status
Simulation time 328035986220 ps
CPU time 787.64 seconds
Started May 19 01:33:29 PM PDT 24
Finished May 19 01:46:40 PM PDT 24
Peak memory 201836 kb
Host smart-7e54f8e0-7fea-4580-b59c-8b7879c53860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057481302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2057481302
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3577159949
Short name T380
Test name
Test status
Simulation time 494786533425 ps
CPU time 278.24 seconds
Started May 19 01:33:29 PM PDT 24
Finished May 19 01:38:10 PM PDT 24
Peak memory 201884 kb
Host smart-6a678f41-b9fe-4d5d-a0a8-ce78261bdc6f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577159949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3577159949
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1763409188
Short name T716
Test name
Test status
Simulation time 593797542913 ps
CPU time 391.37 seconds
Started May 19 01:33:37 PM PDT 24
Finished May 19 01:40:10 PM PDT 24
Peak memory 201872 kb
Host smart-b08d3291-821f-4fb3-9289-0310442ca310
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763409188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1763409188
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.745212332
Short name T714
Test name
Test status
Simulation time 122026937599 ps
CPU time 424.17 seconds
Started May 19 01:33:45 PM PDT 24
Finished May 19 01:40:50 PM PDT 24
Peak memory 202180 kb
Host smart-ae445c23-28b0-4425-9f75-4b7cfd208568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745212332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.745212332
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2701392845
Short name T614
Test name
Test status
Simulation time 27852080809 ps
CPU time 62.96 seconds
Started May 19 01:33:36 PM PDT 24
Finished May 19 01:34:41 PM PDT 24
Peak memory 201588 kb
Host smart-664daf65-64b9-4a20-a508-5c315b16e102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701392845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2701392845
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2141997478
Short name T576
Test name
Test status
Simulation time 3526855830 ps
CPU time 2.66 seconds
Started May 19 01:33:43 PM PDT 24
Finished May 19 01:33:46 PM PDT 24
Peak memory 201548 kb
Host smart-92b1f2b0-1e2d-495a-a6d9-57143ea0410f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141997478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2141997478
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.862030567
Short name T57
Test name
Test status
Simulation time 8325807034 ps
CPU time 3.19 seconds
Started May 19 01:33:32 PM PDT 24
Finished May 19 01:33:37 PM PDT 24
Peak memory 218436 kb
Host smart-ccc8e3eb-c9c7-4f67-917a-3aae983aa079
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862030567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.862030567
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1238015398
Short name T606
Test name
Test status
Simulation time 6085633724 ps
CPU time 14.4 seconds
Started May 19 01:33:28 PM PDT 24
Finished May 19 01:33:46 PM PDT 24
Peak memory 201672 kb
Host smart-6ea091ea-7d72-4ebf-8610-9eb5538b6a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238015398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1238015398
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3004046755
Short name T306
Test name
Test status
Simulation time 494693481510 ps
CPU time 574.6 seconds
Started May 19 01:33:47 PM PDT 24
Finished May 19 01:43:22 PM PDT 24
Peak memory 201856 kb
Host smart-0aa0e488-63c3-4b3e-b040-f580351e4193
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004046755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3004046755
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.688727155
Short name T661
Test name
Test status
Simulation time 525944985 ps
CPU time 0.93 seconds
Started May 19 01:35:06 PM PDT 24
Finished May 19 01:35:07 PM PDT 24
Peak memory 201696 kb
Host smart-a89fc90d-3729-4ad2-889c-fa1bec898674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688727155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.688727155
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1687018345
Short name T629
Test name
Test status
Simulation time 164139802402 ps
CPU time 413.56 seconds
Started May 19 01:35:02 PM PDT 24
Finished May 19 01:41:56 PM PDT 24
Peak memory 201720 kb
Host smart-d6549894-99b5-4a1c-8a04-156c8e3d16b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687018345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1687018345
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2296907600
Short name T518
Test name
Test status
Simulation time 169356700997 ps
CPU time 203.31 seconds
Started May 19 01:35:03 PM PDT 24
Finished May 19 01:38:26 PM PDT 24
Peak memory 201756 kb
Host smart-e7800191-b20b-4e5a-bd33-a90a164c8137
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296907600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2296907600
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1120570932
Short name T616
Test name
Test status
Simulation time 329143539941 ps
CPU time 353.56 seconds
Started May 19 01:35:01 PM PDT 24
Finished May 19 01:40:56 PM PDT 24
Peak memory 201676 kb
Host smart-71d83c36-f29b-4fdc-82a1-79250f28e4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120570932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1120570932
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.521666762
Short name T620
Test name
Test status
Simulation time 326048282243 ps
CPU time 409.67 seconds
Started May 19 01:35:02 PM PDT 24
Finished May 19 01:41:52 PM PDT 24
Peak memory 201796 kb
Host smart-eb1b8d67-bc12-4c00-9067-d731529c6629
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=521666762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.521666762
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.524717939
Short name T686
Test name
Test status
Simulation time 579866322739 ps
CPU time 257.76 seconds
Started May 19 01:35:07 PM PDT 24
Finished May 19 01:39:25 PM PDT 24
Peak memory 202028 kb
Host smart-a6027db4-6a61-4ca3-9937-9b71081bdec7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524717939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
adc_ctrl_filters_wakeup_fixed.524717939
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2052103554
Short name T236
Test name
Test status
Simulation time 134662165288 ps
CPU time 447.94 seconds
Started May 19 01:35:05 PM PDT 24
Finished May 19 01:42:33 PM PDT 24
Peak memory 202020 kb
Host smart-c37686d6-7a9b-4ce6-997a-753d251bf4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052103554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2052103554
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2172535172
Short name T408
Test name
Test status
Simulation time 43696603991 ps
CPU time 96.48 seconds
Started May 19 01:35:05 PM PDT 24
Finished May 19 01:36:42 PM PDT 24
Peak memory 201652 kb
Host smart-c0c31edf-efa8-493a-aca1-2d6f4580f985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172535172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2172535172
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3491742991
Short name T505
Test name
Test status
Simulation time 4450333042 ps
CPU time 3.15 seconds
Started May 19 01:35:07 PM PDT 24
Finished May 19 01:35:11 PM PDT 24
Peak memory 201548 kb
Host smart-d2e5cda5-5a6f-436d-91ab-ff91c758cd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491742991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3491742991
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1864310928
Short name T525
Test name
Test status
Simulation time 5790730114 ps
CPU time 14.91 seconds
Started May 19 01:35:02 PM PDT 24
Finished May 19 01:35:17 PM PDT 24
Peak memory 201652 kb
Host smart-3d414290-475a-42e9-80b7-e8d11af0c415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864310928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1864310928
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2416429395
Short name T17
Test name
Test status
Simulation time 240830524399 ps
CPU time 129.67 seconds
Started May 19 01:35:06 PM PDT 24
Finished May 19 01:37:16 PM PDT 24
Peak memory 210532 kb
Host smart-ada7051a-5838-438b-ada1-102ae11a3a15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416429395 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2416429395
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.786218715
Short name T85
Test name
Test status
Simulation time 446371121 ps
CPU time 1.13 seconds
Started May 19 01:35:15 PM PDT 24
Finished May 19 01:35:16 PM PDT 24
Peak memory 201512 kb
Host smart-c98b788b-4066-4c96-a50e-72d2382835e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786218715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.786218715
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.595489069
Short name T133
Test name
Test status
Simulation time 168766378838 ps
CPU time 380.88 seconds
Started May 19 01:35:15 PM PDT 24
Finished May 19 01:41:37 PM PDT 24
Peak memory 201816 kb
Host smart-149d82c6-0715-4f88-b3c6-2691cb25ac69
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595489069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.595489069
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2611841405
Short name T450
Test name
Test status
Simulation time 490687487221 ps
CPU time 1164.63 seconds
Started May 19 01:35:12 PM PDT 24
Finished May 19 01:54:37 PM PDT 24
Peak memory 201804 kb
Host smart-4667d91c-9b82-461c-9b46-088afdef671c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611841405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2611841405
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1617390500
Short name T246
Test name
Test status
Simulation time 167612181491 ps
CPU time 399.34 seconds
Started May 19 01:35:11 PM PDT 24
Finished May 19 01:41:51 PM PDT 24
Peak memory 201872 kb
Host smart-8c890d82-31ec-4ae7-bd1b-2e1bac24eeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617390500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1617390500
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.341934786
Short name T422
Test name
Test status
Simulation time 327837591216 ps
CPU time 359.13 seconds
Started May 19 01:35:11 PM PDT 24
Finished May 19 01:41:10 PM PDT 24
Peak memory 201872 kb
Host smart-7da81d0a-5833-4d5e-b3f2-9265ee142295
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=341934786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.341934786
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.4051546849
Short name T543
Test name
Test status
Simulation time 180006712005 ps
CPU time 228.16 seconds
Started May 19 01:35:11 PM PDT 24
Finished May 19 01:38:59 PM PDT 24
Peak memory 202056 kb
Host smart-4d4408fb-d1e2-4d0f-8470-c57a6a96c64c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051546849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.4051546849
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3329006067
Short name T10
Test name
Test status
Simulation time 200158624067 ps
CPU time 233.69 seconds
Started May 19 01:35:15 PM PDT 24
Finished May 19 01:39:10 PM PDT 24
Peak memory 201800 kb
Host smart-02841e91-d61f-4c1e-b25b-563fd70034d0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329006067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3329006067
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.4958401
Short name T219
Test name
Test status
Simulation time 47066960461 ps
CPU time 110.99 seconds
Started May 19 01:35:15 PM PDT 24
Finished May 19 01:37:07 PM PDT 24
Peak memory 201932 kb
Host smart-bfe635b9-546a-4b1a-ab73-0f212b42e82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4958401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.4958401
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3840337099
Short name T536
Test name
Test status
Simulation time 5252947227 ps
CPU time 6.98 seconds
Started May 19 01:35:15 PM PDT 24
Finished May 19 01:35:23 PM PDT 24
Peak memory 201576 kb
Host smart-62a5d549-9a8b-4633-8837-bd11394e66c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840337099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3840337099
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3879602453
Short name T600
Test name
Test status
Simulation time 5993385089 ps
CPU time 2.45 seconds
Started May 19 01:35:11 PM PDT 24
Finished May 19 01:35:14 PM PDT 24
Peak memory 201604 kb
Host smart-31477850-1daf-422c-9231-5cbe7d490011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879602453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3879602453
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3521905081
Short name T197
Test name
Test status
Simulation time 172124103117 ps
CPU time 259.58 seconds
Started May 19 01:35:16 PM PDT 24
Finished May 19 01:39:36 PM PDT 24
Peak memory 201876 kb
Host smart-3e209d4f-7f99-451e-b03a-767b8d6154fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521905081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3521905081
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3375175238
Short name T398
Test name
Test status
Simulation time 426390792 ps
CPU time 1.62 seconds
Started May 19 01:35:24 PM PDT 24
Finished May 19 01:35:27 PM PDT 24
Peak memory 201492 kb
Host smart-5f0f4ab5-8655-4987-92f0-f243ee9e89e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375175238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3375175238
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.612282187
Short name T321
Test name
Test status
Simulation time 366248095758 ps
CPU time 806.47 seconds
Started May 19 01:35:20 PM PDT 24
Finished May 19 01:48:47 PM PDT 24
Peak memory 201904 kb
Host smart-5c750106-5f67-426c-a8bb-31826de7dace
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612282187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.612282187
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.1716534204
Short name T487
Test name
Test status
Simulation time 330802225927 ps
CPU time 195.75 seconds
Started May 19 01:35:22 PM PDT 24
Finished May 19 01:38:38 PM PDT 24
Peak memory 201824 kb
Host smart-1a658bc4-f18d-4a36-baf1-02ea9fa99b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716534204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1716534204
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3248738042
Short name T337
Test name
Test status
Simulation time 326264628010 ps
CPU time 373.63 seconds
Started May 19 01:35:20 PM PDT 24
Finished May 19 01:41:35 PM PDT 24
Peak memory 201772 kb
Host smart-6f06f80f-5c9c-4542-9de9-f60e8e50e1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248738042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3248738042
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1615153401
Short name T479
Test name
Test status
Simulation time 497660401632 ps
CPU time 141.43 seconds
Started May 19 01:35:22 PM PDT 24
Finished May 19 01:37:44 PM PDT 24
Peak memory 201776 kb
Host smart-9ed3c827-3998-4528-bfa6-8e0dd0b38ab6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615153401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1615153401
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2662085001
Short name T152
Test name
Test status
Simulation time 493936701638 ps
CPU time 226.6 seconds
Started May 19 01:35:20 PM PDT 24
Finished May 19 01:39:08 PM PDT 24
Peak memory 201784 kb
Host smart-1ff690ad-0713-4f74-9f27-911d34cd16f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662085001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2662085001
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1143259683
Short name T742
Test name
Test status
Simulation time 169552254913 ps
CPU time 343.45 seconds
Started May 19 01:35:22 PM PDT 24
Finished May 19 01:41:06 PM PDT 24
Peak memory 201880 kb
Host smart-848aa199-8cbc-48c4-8391-be2b04330777
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143259683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1143259683
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1886139218
Short name T346
Test name
Test status
Simulation time 548859239737 ps
CPU time 1245.45 seconds
Started May 19 01:35:21 PM PDT 24
Finished May 19 01:56:07 PM PDT 24
Peak memory 201868 kb
Host smart-1e7b23ca-0fbe-4d41-9dfb-a8206853ec37
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886139218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1886139218
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3243106686
Short name T574
Test name
Test status
Simulation time 605798430705 ps
CPU time 729.62 seconds
Started May 19 01:35:22 PM PDT 24
Finished May 19 01:47:33 PM PDT 24
Peak memory 202148 kb
Host smart-7720a5e9-ba14-4ae5-9e3b-23f334e4308a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243106686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3243106686
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.306355891
Short name T483
Test name
Test status
Simulation time 107097905445 ps
CPU time 421.79 seconds
Started May 19 01:35:26 PM PDT 24
Finished May 19 01:42:28 PM PDT 24
Peak memory 202156 kb
Host smart-e92cd955-24c9-4695-a6e1-214799e3abf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306355891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.306355891
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2448751772
Short name T464
Test name
Test status
Simulation time 45787449816 ps
CPU time 105.39 seconds
Started May 19 01:35:26 PM PDT 24
Finished May 19 01:37:11 PM PDT 24
Peak memory 201644 kb
Host smart-a9bec735-72cf-439a-bef4-514039386958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448751772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2448751772
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1143620954
Short name T496
Test name
Test status
Simulation time 4923570927 ps
CPU time 13.36 seconds
Started May 19 01:35:20 PM PDT 24
Finished May 19 01:35:34 PM PDT 24
Peak memory 201656 kb
Host smart-210d087b-4165-42bb-bbc3-27e52d48ab1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143620954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1143620954
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.37771069
Short name T97
Test name
Test status
Simulation time 6125126059 ps
CPU time 2.25 seconds
Started May 19 01:35:16 PM PDT 24
Finished May 19 01:35:19 PM PDT 24
Peak memory 201524 kb
Host smart-bd8bdf4a-686a-4687-b14d-bc5f8df8d7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37771069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.37771069
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1558328527
Short name T143
Test name
Test status
Simulation time 496694007143 ps
CPU time 152.1 seconds
Started May 19 01:35:26 PM PDT 24
Finished May 19 01:37:59 PM PDT 24
Peak memory 201780 kb
Host smart-b19d621b-d888-4e50-a6a1-894251d8a7e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558328527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1558328527
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3742666119
Short name T13
Test name
Test status
Simulation time 23290268729 ps
CPU time 57.63 seconds
Started May 19 01:35:25 PM PDT 24
Finished May 19 01:36:23 PM PDT 24
Peak memory 201880 kb
Host smart-ad1634c7-77ec-4fb5-9b99-b366ca29e384
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742666119 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3742666119
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3442241916
Short name T434
Test name
Test status
Simulation time 288070933 ps
CPU time 0.81 seconds
Started May 19 01:35:36 PM PDT 24
Finished May 19 01:35:37 PM PDT 24
Peak memory 201460 kb
Host smart-375684c4-18e5-4fe8-a913-1282314204a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442241916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3442241916
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2361400860
Short name T472
Test name
Test status
Simulation time 174479182235 ps
CPU time 344.92 seconds
Started May 19 01:35:35 PM PDT 24
Finished May 19 01:41:21 PM PDT 24
Peak memory 201796 kb
Host smart-7d1a8ce3-eb02-4405-87f3-8e6c46fd11e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361400860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2361400860
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3520730017
Short name T361
Test name
Test status
Simulation time 511998789610 ps
CPU time 1059.48 seconds
Started May 19 01:35:35 PM PDT 24
Finished May 19 01:53:15 PM PDT 24
Peak memory 201852 kb
Host smart-aa692c64-8575-4f8e-957b-3cea3d02b675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520730017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3520730017
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.4227091275
Short name T171
Test name
Test status
Simulation time 499544548666 ps
CPU time 275.02 seconds
Started May 19 01:35:31 PM PDT 24
Finished May 19 01:40:07 PM PDT 24
Peak memory 201904 kb
Host smart-43794a13-f66e-4ee6-9276-ab1191f844fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227091275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.4227091275
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.118989353
Short name T409
Test name
Test status
Simulation time 499130810677 ps
CPU time 1041.38 seconds
Started May 19 01:35:31 PM PDT 24
Finished May 19 01:52:52 PM PDT 24
Peak memory 201792 kb
Host smart-65f74d18-85e1-41b8-be6c-a51749bd2a54
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=118989353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.118989353
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2795584173
Short name T482
Test name
Test status
Simulation time 161021149284 ps
CPU time 230.23 seconds
Started May 19 01:35:31 PM PDT 24
Finished May 19 01:39:21 PM PDT 24
Peak memory 201876 kb
Host smart-d6225f24-4603-4177-a10c-62ab076eaf0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795584173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2795584173
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.262255950
Short name T417
Test name
Test status
Simulation time 326574789201 ps
CPU time 230.86 seconds
Started May 19 01:35:32 PM PDT 24
Finished May 19 01:39:23 PM PDT 24
Peak memory 201756 kb
Host smart-6c11c999-8a17-4090-90bb-05c198736701
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=262255950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.262255950
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3945277469
Short name T624
Test name
Test status
Simulation time 170870618759 ps
CPU time 363.12 seconds
Started May 19 01:35:30 PM PDT 24
Finished May 19 01:41:33 PM PDT 24
Peak memory 201892 kb
Host smart-df91bc6e-d98d-419f-9922-ad0c1487f4da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945277469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3945277469
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.29173292
Short name T581
Test name
Test status
Simulation time 586616493451 ps
CPU time 687.72 seconds
Started May 19 01:35:30 PM PDT 24
Finished May 19 01:46:58 PM PDT 24
Peak memory 201768 kb
Host smart-626f74fe-e1bf-40af-a192-482b8a67a0e2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29173292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.a
dc_ctrl_filters_wakeup_fixed.29173292
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.353418960
Short name T11
Test name
Test status
Simulation time 111774910777 ps
CPU time 423.74 seconds
Started May 19 01:35:35 PM PDT 24
Finished May 19 01:42:39 PM PDT 24
Peak memory 202124 kb
Host smart-190ef006-f937-4fb7-bb43-bfe5af02f1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353418960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.353418960
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2947356953
Short name T196
Test name
Test status
Simulation time 36608152571 ps
CPU time 20.59 seconds
Started May 19 01:35:37 PM PDT 24
Finished May 19 01:35:58 PM PDT 24
Peak memory 201840 kb
Host smart-ae3b10d0-b667-414e-9a39-d44e57ed45a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947356953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2947356953
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.763244844
Short name T421
Test name
Test status
Simulation time 5127337428 ps
CPU time 3.06 seconds
Started May 19 01:35:35 PM PDT 24
Finished May 19 01:35:38 PM PDT 24
Peak memory 201912 kb
Host smart-167c11d3-f132-42ad-8aba-2f84bfc06de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763244844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.763244844
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1469285112
Short name T88
Test name
Test status
Simulation time 6028475798 ps
CPU time 16.3 seconds
Started May 19 01:35:24 PM PDT 24
Finished May 19 01:35:41 PM PDT 24
Peak memory 201600 kb
Host smart-212ce883-bf96-4794-91f4-cdfc39c836eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469285112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1469285112
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3809671205
Short name T424
Test name
Test status
Simulation time 50896301587 ps
CPU time 24.4 seconds
Started May 19 01:35:36 PM PDT 24
Finished May 19 01:36:01 PM PDT 24
Peak memory 201836 kb
Host smart-312c12f8-4e62-437d-9097-84e2f4556783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809671205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3809671205
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1218181254
Short name T735
Test name
Test status
Simulation time 161098728133 ps
CPU time 77.75 seconds
Started May 19 01:35:37 PM PDT 24
Finished May 19 01:36:55 PM PDT 24
Peak memory 212476 kb
Host smart-047715e3-7803-4288-9b20-4223085bf0ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218181254 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1218181254
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1457115480
Short name T699
Test name
Test status
Simulation time 497406496 ps
CPU time 1.71 seconds
Started May 19 01:35:44 PM PDT 24
Finished May 19 01:35:46 PM PDT 24
Peak memory 201528 kb
Host smart-ac4ba26b-8859-4b59-b9d9-25b09bd5a912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457115480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1457115480
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1386657759
Short name T765
Test name
Test status
Simulation time 164210087979 ps
CPU time 294.61 seconds
Started May 19 01:35:40 PM PDT 24
Finished May 19 01:40:35 PM PDT 24
Peak memory 201908 kb
Host smart-6d1774e3-b1f7-4dea-9139-8b5ac6a8d411
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386657759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1386657759
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.560464240
Short name T253
Test name
Test status
Simulation time 173766431204 ps
CPU time 135.59 seconds
Started May 19 01:35:41 PM PDT 24
Finished May 19 01:37:57 PM PDT 24
Peak memory 201784 kb
Host smart-7354c460-3360-49f7-a8bf-8676f94fe141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560464240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.560464240
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.576943373
Short name T789
Test name
Test status
Simulation time 165141234598 ps
CPU time 78.5 seconds
Started May 19 01:35:41 PM PDT 24
Finished May 19 01:37:00 PM PDT 24
Peak memory 201852 kb
Host smart-4a5971b1-0eea-47de-a4dd-2f117ffdfdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576943373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.576943373
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2561775748
Short name T383
Test name
Test status
Simulation time 491602784585 ps
CPU time 1051.8 seconds
Started May 19 01:35:41 PM PDT 24
Finished May 19 01:53:13 PM PDT 24
Peak memory 201704 kb
Host smart-1c111978-c5f4-4d8f-926d-87b82d1ddff0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561775748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2561775748
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3641634768
Short name T190
Test name
Test status
Simulation time 492273144241 ps
CPU time 301.49 seconds
Started May 19 01:35:36 PM PDT 24
Finished May 19 01:40:38 PM PDT 24
Peak memory 202104 kb
Host smart-32c26d50-1dcc-4da3-a11b-a5b304fe2387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641634768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3641634768
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3093057929
Short name T572
Test name
Test status
Simulation time 492962400007 ps
CPU time 252.05 seconds
Started May 19 01:35:35 PM PDT 24
Finished May 19 01:39:47 PM PDT 24
Peak memory 201836 kb
Host smart-efd21094-4e48-4dac-ab35-5156cdffe11d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093057929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3093057929
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.604588663
Short name T709
Test name
Test status
Simulation time 623218404433 ps
CPU time 281.46 seconds
Started May 19 01:35:40 PM PDT 24
Finished May 19 01:40:22 PM PDT 24
Peak memory 201800 kb
Host smart-766c0c3f-8b0b-4fe9-aa99-ab5f1a56e120
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604588663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.604588663
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.614638599
Short name T645
Test name
Test status
Simulation time 79360363005 ps
CPU time 451.16 seconds
Started May 19 01:35:40 PM PDT 24
Finished May 19 01:43:12 PM PDT 24
Peak memory 202124 kb
Host smart-75a53ef6-c70e-4203-be89-47b1559a7e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614638599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.614638599
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.709226373
Short name T441
Test name
Test status
Simulation time 47255385616 ps
CPU time 10.12 seconds
Started May 19 01:35:41 PM PDT 24
Finished May 19 01:35:52 PM PDT 24
Peak memory 201588 kb
Host smart-56d62264-8800-44d6-bb6e-79e7a802e206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709226373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.709226373
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.190183716
Short name T593
Test name
Test status
Simulation time 4148747027 ps
CPU time 3.93 seconds
Started May 19 01:35:39 PM PDT 24
Finished May 19 01:35:44 PM PDT 24
Peak memory 201572 kb
Host smart-d21f41a0-bb18-429c-93e4-c3c7537b7d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190183716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.190183716
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3938171514
Short name T185
Test name
Test status
Simulation time 5690799100 ps
CPU time 3.97 seconds
Started May 19 01:35:37 PM PDT 24
Finished May 19 01:35:42 PM PDT 24
Peak memory 201592 kb
Host smart-5fe1cc36-55b6-4182-a129-1219f08d2f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938171514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3938171514
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2630895028
Short name T281
Test name
Test status
Simulation time 383138627945 ps
CPU time 133.26 seconds
Started May 19 01:35:45 PM PDT 24
Finished May 19 01:37:59 PM PDT 24
Peak memory 201832 kb
Host smart-09dfecd6-bd2c-44fc-9f0f-b20b19340a22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630895028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2630895028
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.377030022
Short name T284
Test name
Test status
Simulation time 59255798758 ps
CPU time 26.06 seconds
Started May 19 01:35:47 PM PDT 24
Finished May 19 01:36:13 PM PDT 24
Peak memory 210140 kb
Host smart-2a634084-5f33-4f89-8d52-a343f7227ff8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377030022 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.377030022
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1079101288
Short name T104
Test name
Test status
Simulation time 496262890 ps
CPU time 0.92 seconds
Started May 19 01:35:51 PM PDT 24
Finished May 19 01:35:52 PM PDT 24
Peak memory 201496 kb
Host smart-368a04a8-b0ba-4cf8-8fa2-29e6ee3a13f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079101288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1079101288
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2761593685
Short name T174
Test name
Test status
Simulation time 331677072400 ps
CPU time 398.08 seconds
Started May 19 01:35:45 PM PDT 24
Finished May 19 01:42:24 PM PDT 24
Peak memory 201828 kb
Host smart-4c5accbe-ebf0-4434-a6c2-1c1f15503449
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761593685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2761593685
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.985842250
Short name T707
Test name
Test status
Simulation time 330755556070 ps
CPU time 249.09 seconds
Started May 19 01:35:45 PM PDT 24
Finished May 19 01:39:54 PM PDT 24
Peak memory 201696 kb
Host smart-258208af-0cf4-440d-9baa-bc6281fa424b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985842250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.985842250
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2861462082
Short name T514
Test name
Test status
Simulation time 162967490023 ps
CPU time 381.59 seconds
Started May 19 01:35:46 PM PDT 24
Finished May 19 01:42:08 PM PDT 24
Peak memory 201796 kb
Host smart-d6dc9d6a-e3ce-45e1-939d-a09ba3567ad4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861462082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2861462082
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1090203159
Short name T782
Test name
Test status
Simulation time 338341159792 ps
CPU time 161.32 seconds
Started May 19 01:35:47 PM PDT 24
Finished May 19 01:38:28 PM PDT 24
Peak memory 201704 kb
Host smart-94f8fba1-908c-40f2-8b8a-212683dc2538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090203159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1090203159
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3883622220
Short name T484
Test name
Test status
Simulation time 324681899095 ps
CPU time 162.17 seconds
Started May 19 01:35:44 PM PDT 24
Finished May 19 01:38:27 PM PDT 24
Peak memory 201780 kb
Host smart-3b62e383-78c7-48a8-bb6f-d6a262077b6d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883622220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3883622220
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2456651513
Short name T302
Test name
Test status
Simulation time 540359805002 ps
CPU time 1207.45 seconds
Started May 19 01:35:46 PM PDT 24
Finished May 19 01:55:54 PM PDT 24
Peak memory 201908 kb
Host smart-36b358f6-b5c7-468b-92a3-80312b6c9c5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456651513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2456651513
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2036359962
Short name T474
Test name
Test status
Simulation time 403690339739 ps
CPU time 892.92 seconds
Started May 19 01:35:48 PM PDT 24
Finished May 19 01:50:41 PM PDT 24
Peak memory 202064 kb
Host smart-b3693235-702f-43a6-be21-47f112709ebb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036359962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2036359962
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3910570209
Short name T569
Test name
Test status
Simulation time 75937468392 ps
CPU time 253.47 seconds
Started May 19 01:35:51 PM PDT 24
Finished May 19 01:40:05 PM PDT 24
Peak memory 202156 kb
Host smart-4e9ef221-c3dc-434d-a9c7-270739c9e825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910570209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3910570209
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1667307149
Short name T566
Test name
Test status
Simulation time 23527021702 ps
CPU time 3.5 seconds
Started May 19 01:35:51 PM PDT 24
Finished May 19 01:35:55 PM PDT 24
Peak memory 201600 kb
Host smart-d89277b1-c819-44d0-9178-4709673989f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667307149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1667307149
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3145257475
Short name T209
Test name
Test status
Simulation time 4332694623 ps
CPU time 11.64 seconds
Started May 19 01:35:50 PM PDT 24
Finished May 19 01:36:02 PM PDT 24
Peak memory 201656 kb
Host smart-caf9d43b-f1bd-45ff-b594-6baa9499fce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145257475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3145257475
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3760903558
Short name T492
Test name
Test status
Simulation time 5945745832 ps
CPU time 4.47 seconds
Started May 19 01:35:46 PM PDT 24
Finished May 19 01:35:51 PM PDT 24
Peak memory 201640 kb
Host smart-88523be5-c34f-4ede-938c-7c18467bacc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760903558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3760903558
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.706083457
Short name T75
Test name
Test status
Simulation time 206780901469 ps
CPU time 139.16 seconds
Started May 19 01:35:52 PM PDT 24
Finished May 19 01:38:11 PM PDT 24
Peak memory 210156 kb
Host smart-a8dcc5e5-bb0a-4b40-bd14-b0f452c65385
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706083457 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.706083457
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.4162677411
Short name T442
Test name
Test status
Simulation time 441203155 ps
CPU time 1.72 seconds
Started May 19 01:36:10 PM PDT 24
Finished May 19 01:36:13 PM PDT 24
Peak memory 201500 kb
Host smart-f1d4eacd-e965-4865-8a68-7156f25382a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162677411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.4162677411
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1728827005
Short name T316
Test name
Test status
Simulation time 539422641952 ps
CPU time 337.19 seconds
Started May 19 01:36:05 PM PDT 24
Finished May 19 01:41:43 PM PDT 24
Peak memory 201800 kb
Host smart-aa107f5c-d7a9-4104-95ca-533822b31cce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728827005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1728827005
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3096872505
Short name T693
Test name
Test status
Simulation time 263774430924 ps
CPU time 628.83 seconds
Started May 19 01:36:05 PM PDT 24
Finished May 19 01:46:35 PM PDT 24
Peak memory 201816 kb
Host smart-d58f9d63-d778-4f3e-95b0-e9644cdc680a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096872505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3096872505
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3762614986
Short name T703
Test name
Test status
Simulation time 164267677670 ps
CPU time 108.01 seconds
Started May 19 01:36:02 PM PDT 24
Finished May 19 01:37:50 PM PDT 24
Peak memory 201816 kb
Host smart-a1fd06a9-e3fd-4663-a876-31a1083fe397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762614986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3762614986
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1010630763
Short name T502
Test name
Test status
Simulation time 162820430736 ps
CPU time 372.88 seconds
Started May 19 01:36:01 PM PDT 24
Finished May 19 01:42:14 PM PDT 24
Peak memory 201784 kb
Host smart-a2fcaa57-a043-4469-ac86-8578c5d2aa0e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010630763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1010630763
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3800664332
Short name T792
Test name
Test status
Simulation time 485334595627 ps
CPU time 87 seconds
Started May 19 01:35:56 PM PDT 24
Finished May 19 01:37:23 PM PDT 24
Peak memory 201676 kb
Host smart-58d56c56-192c-411c-8bd3-dc166418c0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800664332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3800664332
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2567939923
Short name T499
Test name
Test status
Simulation time 165982832359 ps
CPU time 102.34 seconds
Started May 19 01:35:55 PM PDT 24
Finished May 19 01:37:38 PM PDT 24
Peak memory 201768 kb
Host smart-76535ccc-c7eb-4286-8745-2ed5561089aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567939923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2567939923
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3986055668
Short name T333
Test name
Test status
Simulation time 537678211271 ps
CPU time 319.41 seconds
Started May 19 01:36:01 PM PDT 24
Finished May 19 01:41:21 PM PDT 24
Peak memory 201872 kb
Host smart-25acbf80-883b-4aca-933d-7568de8c1098
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986055668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3986055668
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3642064555
Short name T495
Test name
Test status
Simulation time 202358798679 ps
CPU time 123.6 seconds
Started May 19 01:36:04 PM PDT 24
Finished May 19 01:38:08 PM PDT 24
Peak memory 201836 kb
Host smart-305c7e25-9276-4dce-adcc-0280511a070c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642064555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.3642064555
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2459411674
Short name T74
Test name
Test status
Simulation time 31417491633 ps
CPU time 5.3 seconds
Started May 19 01:36:09 PM PDT 24
Finished May 19 01:36:15 PM PDT 24
Peak memory 201568 kb
Host smart-0e3dbb09-a269-4479-9e69-f3c23d6490b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459411674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2459411674
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.716473978
Short name T451
Test name
Test status
Simulation time 3227493235 ps
CPU time 6.12 seconds
Started May 19 01:36:04 PM PDT 24
Finished May 19 01:36:11 PM PDT 24
Peak memory 201600 kb
Host smart-f66a5a3d-8e92-4a42-9d9e-d70d16228cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716473978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.716473978
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.39975403
Short name T673
Test name
Test status
Simulation time 6075990308 ps
CPU time 7.4 seconds
Started May 19 01:35:54 PM PDT 24
Finished May 19 01:36:01 PM PDT 24
Peak memory 201648 kb
Host smart-65eb3ca0-c7a7-4cd1-9864-05f199095dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39975403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.39975403
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2810824642
Short name T599
Test name
Test status
Simulation time 102548111564 ps
CPU time 527.25 seconds
Started May 19 01:36:09 PM PDT 24
Finished May 19 01:44:56 PM PDT 24
Peak memory 202104 kb
Host smart-39029c9f-7ee3-43ff-a277-94626280fd44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810824642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2810824642
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2055612719
Short name T399
Test name
Test status
Simulation time 296907899 ps
CPU time 0.95 seconds
Started May 19 01:36:19 PM PDT 24
Finished May 19 01:36:20 PM PDT 24
Peak memory 201480 kb
Host smart-8522794d-31d1-4cda-9f47-31595f9e5c19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055612719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2055612719
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.871683013
Short name T646
Test name
Test status
Simulation time 184729842999 ps
CPU time 448.05 seconds
Started May 19 01:36:20 PM PDT 24
Finished May 19 01:43:49 PM PDT 24
Peak memory 201828 kb
Host smart-ac9c1d6f-0ecc-4057-8d38-0daa9a69adcf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871683013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gati
ng.871683013
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1471014560
Short name T530
Test name
Test status
Simulation time 162440746561 ps
CPU time 398.84 seconds
Started May 19 01:36:19 PM PDT 24
Finished May 19 01:42:58 PM PDT 24
Peak memory 201804 kb
Host smart-f904da8b-8c8b-4bc4-9a20-312fbbe376ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471014560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1471014560
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.758827952
Short name T244
Test name
Test status
Simulation time 163708477873 ps
CPU time 165.9 seconds
Started May 19 01:36:14 PM PDT 24
Finished May 19 01:39:00 PM PDT 24
Peak memory 201780 kb
Host smart-3d1872b7-34b0-4cc2-a281-02f1baa388c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758827952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.758827952
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1542406870
Short name T731
Test name
Test status
Simulation time 166503494342 ps
CPU time 117.49 seconds
Started May 19 01:36:13 PM PDT 24
Finished May 19 01:38:12 PM PDT 24
Peak memory 201796 kb
Host smart-8cd2a153-3529-4d0e-990c-f80b3f8215fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542406870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1542406870
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1294873366
Short name T98
Test name
Test status
Simulation time 321457783901 ps
CPU time 751.3 seconds
Started May 19 01:36:15 PM PDT 24
Finished May 19 01:48:47 PM PDT 24
Peak memory 201848 kb
Host smart-92e0aee2-c023-46d9-ad9b-af013dabe222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294873366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1294873366
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3140076094
Short name T630
Test name
Test status
Simulation time 318740290624 ps
CPU time 321.97 seconds
Started May 19 01:36:14 PM PDT 24
Finished May 19 01:41:36 PM PDT 24
Peak memory 201804 kb
Host smart-318b5666-6ab2-47a2-b1d6-2d5c61bd1872
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140076094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3140076094
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3660077635
Short name T138
Test name
Test status
Simulation time 471380685651 ps
CPU time 178.01 seconds
Started May 19 01:36:15 PM PDT 24
Finished May 19 01:39:13 PM PDT 24
Peak memory 201860 kb
Host smart-13078dfb-c25e-4232-bff8-8538f490c151
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660077635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3660077635
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3585563596
Short name T741
Test name
Test status
Simulation time 192338260997 ps
CPU time 130.38 seconds
Started May 19 01:36:19 PM PDT 24
Finished May 19 01:38:30 PM PDT 24
Peak memory 201768 kb
Host smart-a761a85d-37d4-44be-a2ae-76822b5c1344
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585563596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3585563596
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2054558853
Short name T235
Test name
Test status
Simulation time 90308759836 ps
CPU time 299.41 seconds
Started May 19 01:36:23 PM PDT 24
Finished May 19 01:41:23 PM PDT 24
Peak memory 202104 kb
Host smart-407dc659-1b8f-4d1e-95c1-ff421eb199f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054558853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2054558853
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.201828252
Short name T795
Test name
Test status
Simulation time 29214531205 ps
CPU time 68.41 seconds
Started May 19 01:36:20 PM PDT 24
Finished May 19 01:37:28 PM PDT 24
Peak memory 201908 kb
Host smart-047e6752-c50f-4590-bf30-781848b3197a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201828252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.201828252
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.4263611841
Short name T504
Test name
Test status
Simulation time 3061032010 ps
CPU time 6.87 seconds
Started May 19 01:36:23 PM PDT 24
Finished May 19 01:36:30 PM PDT 24
Peak memory 201564 kb
Host smart-448f0f44-4873-4a53-81d9-a7f0e64ec25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263611841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.4263611841
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1001638249
Short name T396
Test name
Test status
Simulation time 6074873674 ps
CPU time 4.23 seconds
Started May 19 01:36:14 PM PDT 24
Finished May 19 01:36:19 PM PDT 24
Peak memory 201664 kb
Host smart-aade146f-f1b4-4831-9c70-2012ebaa27ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001638249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1001638249
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.226582760
Short name T19
Test name
Test status
Simulation time 387401172982 ps
CPU time 155.68 seconds
Started May 19 01:36:23 PM PDT 24
Finished May 19 01:38:59 PM PDT 24
Peak memory 210484 kb
Host smart-b387f0c7-00b5-4221-8df3-f1c35fe4444e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226582760 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.226582760
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.830812733
Short name T752
Test name
Test status
Simulation time 400389736 ps
CPU time 0.87 seconds
Started May 19 01:36:34 PM PDT 24
Finished May 19 01:36:36 PM PDT 24
Peak memory 201696 kb
Host smart-7e5e53bf-257e-4967-9cfe-0cd2b6f291e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830812733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.830812733
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.4119178089
Short name T156
Test name
Test status
Simulation time 335024910369 ps
CPU time 211.84 seconds
Started May 19 01:36:28 PM PDT 24
Finished May 19 01:40:00 PM PDT 24
Peak memory 201884 kb
Host smart-e6ba70c3-b234-4402-b334-18473155d5d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119178089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.4119178089
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.185565332
Short name T297
Test name
Test status
Simulation time 195400644536 ps
CPU time 118.63 seconds
Started May 19 01:36:28 PM PDT 24
Finished May 19 01:38:27 PM PDT 24
Peak memory 201876 kb
Host smart-3832453c-38e3-465f-9bef-4a3f77a481fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185565332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.185565332
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.437406123
Short name T259
Test name
Test status
Simulation time 498714328572 ps
CPU time 300.5 seconds
Started May 19 01:36:24 PM PDT 24
Finished May 19 01:41:25 PM PDT 24
Peak memory 201840 kb
Host smart-0e03e9d4-43d5-4b4a-a10f-1988311d88fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437406123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.437406123
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2296542704
Short name T372
Test name
Test status
Simulation time 494268084244 ps
CPU time 586.97 seconds
Started May 19 01:36:23 PM PDT 24
Finished May 19 01:46:10 PM PDT 24
Peak memory 201812 kb
Host smart-2dae7852-aa42-43c5-b659-4c388a62427d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296542704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2296542704
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1609882362
Short name T776
Test name
Test status
Simulation time 329312677943 ps
CPU time 166.25 seconds
Started May 19 01:36:23 PM PDT 24
Finished May 19 01:39:10 PM PDT 24
Peak memory 201788 kb
Host smart-77b9180b-b7b5-405e-8f42-592cfa7648ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609882362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1609882362
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1690244734
Short name T4
Test name
Test status
Simulation time 327598469035 ps
CPU time 809.74 seconds
Started May 19 01:36:25 PM PDT 24
Finished May 19 01:49:55 PM PDT 24
Peak memory 201788 kb
Host smart-e7ecf236-cb0c-457e-93e7-4bc3d31b811a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690244734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1690244734
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.3385511374
Short name T176
Test name
Test status
Simulation time 530495513949 ps
CPU time 87.02 seconds
Started May 19 01:36:25 PM PDT 24
Finished May 19 01:37:52 PM PDT 24
Peak memory 201780 kb
Host smart-e42b5d08-d7a5-4e40-a0ca-4c90332502c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385511374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.3385511374
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.599690804
Short name T725
Test name
Test status
Simulation time 200897363475 ps
CPU time 466.84 seconds
Started May 19 01:36:28 PM PDT 24
Finished May 19 01:44:16 PM PDT 24
Peak memory 201820 kb
Host smart-3b0d9cee-1cdc-437f-8064-65be85254c07
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599690804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.599690804
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3037967734
Short name T481
Test name
Test status
Simulation time 66516165517 ps
CPU time 291.71 seconds
Started May 19 01:36:34 PM PDT 24
Finished May 19 01:41:27 PM PDT 24
Peak memory 202112 kb
Host smart-1fa0460f-7a95-4914-ba22-127eab9dfd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037967734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3037967734
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3142377592
Short name T488
Test name
Test status
Simulation time 43102350452 ps
CPU time 26.09 seconds
Started May 19 01:36:29 PM PDT 24
Finished May 19 01:36:55 PM PDT 24
Peak memory 201644 kb
Host smart-a12937c4-e02f-41c0-a734-61fac0ed6b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142377592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3142377592
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3017074444
Short name T476
Test name
Test status
Simulation time 4798801000 ps
CPU time 3.65 seconds
Started May 19 01:36:28 PM PDT 24
Finished May 19 01:36:32 PM PDT 24
Peak memory 201656 kb
Host smart-6aa9cd0c-3c59-4c61-b510-6b21087201c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017074444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3017074444
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1559899631
Short name T460
Test name
Test status
Simulation time 5890168325 ps
CPU time 4.52 seconds
Started May 19 01:36:24 PM PDT 24
Finished May 19 01:36:29 PM PDT 24
Peak memory 201616 kb
Host smart-c2d6f056-a9e3-4274-b33a-3e1c31f9b105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559899631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1559899631
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1017837444
Short name T740
Test name
Test status
Simulation time 335376493890 ps
CPU time 395.19 seconds
Started May 19 01:36:35 PM PDT 24
Finished May 19 01:43:11 PM PDT 24
Peak memory 201904 kb
Host smart-68cf3d9a-d068-4908-ad7c-7eb5f9f52084
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017837444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1017837444
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2570314255
Short name T39
Test name
Test status
Simulation time 23188356573 ps
CPU time 50.5 seconds
Started May 19 01:36:29 PM PDT 24
Finished May 19 01:37:20 PM PDT 24
Peak memory 201928 kb
Host smart-6123a879-0864-461c-9054-a322d0c87ea8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570314255 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2570314255
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2613884486
Short name T63
Test name
Test status
Simulation time 407189543 ps
CPU time 0.83 seconds
Started May 19 01:36:44 PM PDT 24
Finished May 19 01:36:46 PM PDT 24
Peak memory 201540 kb
Host smart-0b61d3e6-8caf-4e44-867a-6033379d17ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613884486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2613884486
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3683561478
Short name T651
Test name
Test status
Simulation time 564962152234 ps
CPU time 1104.26 seconds
Started May 19 01:36:40 PM PDT 24
Finished May 19 01:55:05 PM PDT 24
Peak memory 201904 kb
Host smart-459bf14f-4873-4f16-843f-e750da8cf628
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683561478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3683561478
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2051090655
Short name T729
Test name
Test status
Simulation time 166233183202 ps
CPU time 96.73 seconds
Started May 19 01:36:39 PM PDT 24
Finished May 19 01:38:16 PM PDT 24
Peak memory 201780 kb
Host smart-db7bdf25-6103-49bd-8a72-895da3819b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051090655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2051090655
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.4006353205
Short name T96
Test name
Test status
Simulation time 491230084593 ps
CPU time 597.75 seconds
Started May 19 01:36:40 PM PDT 24
Finished May 19 01:46:38 PM PDT 24
Peak memory 201768 kb
Host smart-f77499b6-5825-43c7-9a52-a64ce7f8117f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006353205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.4006353205
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.475397312
Short name T696
Test name
Test status
Simulation time 323588474209 ps
CPU time 194.12 seconds
Started May 19 01:36:39 PM PDT 24
Finished May 19 01:39:53 PM PDT 24
Peak memory 201808 kb
Host smart-f696f4c9-6795-4eab-9f35-44436e91e4f7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=475397312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.475397312
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1624059666
Short name T274
Test name
Test status
Simulation time 486552748047 ps
CPU time 1242.64 seconds
Started May 19 01:36:35 PM PDT 24
Finished May 19 01:57:18 PM PDT 24
Peak memory 201812 kb
Host smart-9b4be581-3717-4cf8-a181-b24e2d31f80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624059666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1624059666
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2602616942
Short name T544
Test name
Test status
Simulation time 491973874092 ps
CPU time 1128.41 seconds
Started May 19 01:36:34 PM PDT 24
Finished May 19 01:55:24 PM PDT 24
Peak memory 201740 kb
Host smart-7c976da3-c310-440f-b297-9b1a84925b09
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602616942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2602616942
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1905136789
Short name T348
Test name
Test status
Simulation time 360851918348 ps
CPU time 409.15 seconds
Started May 19 01:36:39 PM PDT 24
Finished May 19 01:43:29 PM PDT 24
Peak memory 201780 kb
Host smart-4f35dd71-bd8f-4087-882a-a447ee4708da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905136789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1905136789
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3267331725
Short name T655
Test name
Test status
Simulation time 608354914020 ps
CPU time 1481.25 seconds
Started May 19 01:36:39 PM PDT 24
Finished May 19 02:01:21 PM PDT 24
Peak memory 201760 kb
Host smart-446e7046-a158-414e-94a9-2d1dac340bfd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267331725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3267331725
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1858637678
Short name T778
Test name
Test status
Simulation time 122187626607 ps
CPU time 615.59 seconds
Started May 19 01:36:47 PM PDT 24
Finished May 19 01:47:03 PM PDT 24
Peak memory 202176 kb
Host smart-2521b4f5-d187-44ee-816f-d114efcc3f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858637678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1858637678
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.864420387
Short name T480
Test name
Test status
Simulation time 34476416127 ps
CPU time 19.51 seconds
Started May 19 01:36:44 PM PDT 24
Finished May 19 01:37:04 PM PDT 24
Peak memory 201592 kb
Host smart-7bfcc572-168d-4b4a-ac31-419c43380848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864420387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.864420387
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3747156955
Short name T737
Test name
Test status
Simulation time 4421556046 ps
CPU time 3.49 seconds
Started May 19 01:36:40 PM PDT 24
Finished May 19 01:36:44 PM PDT 24
Peak memory 201616 kb
Host smart-f5135d0b-0984-4c85-a184-ce44ca993775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747156955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3747156955
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.4009297506
Short name T607
Test name
Test status
Simulation time 5790018590 ps
CPU time 13.31 seconds
Started May 19 01:36:34 PM PDT 24
Finished May 19 01:36:48 PM PDT 24
Peak memory 201636 kb
Host smart-1902d493-8ebe-4f79-b79e-fbc0c5422599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009297506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.4009297506
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3075141361
Short name T202
Test name
Test status
Simulation time 199516969919 ps
CPU time 39.32 seconds
Started May 19 01:36:44 PM PDT 24
Finished May 19 01:37:24 PM PDT 24
Peak memory 201772 kb
Host smart-f1065042-6f83-4117-b06b-e0ba40f8b1ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075141361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3075141361
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.831272258
Short name T233
Test name
Test status
Simulation time 705904520593 ps
CPU time 584.98 seconds
Started May 19 01:36:47 PM PDT 24
Finished May 19 01:46:33 PM PDT 24
Peak memory 210408 kb
Host smart-de37c78a-684f-4e15-a221-c5adbf84497d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831272258 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.831272258
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1721151551
Short name T404
Test name
Test status
Simulation time 461298506 ps
CPU time 0.87 seconds
Started May 19 01:33:33 PM PDT 24
Finished May 19 01:33:36 PM PDT 24
Peak memory 201436 kb
Host smart-76f69219-5b7b-4633-982e-3599c0999eb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721151551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1721151551
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1175479278
Short name T674
Test name
Test status
Simulation time 162641470972 ps
CPU time 333.37 seconds
Started May 19 01:33:52 PM PDT 24
Finished May 19 01:39:27 PM PDT 24
Peak memory 201852 kb
Host smart-c658f0de-497a-428c-a2e2-cd350fadfb56
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175479278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1175479278
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2991530014
Short name T635
Test name
Test status
Simulation time 360624477614 ps
CPU time 849.81 seconds
Started May 19 01:33:48 PM PDT 24
Finished May 19 01:47:59 PM PDT 24
Peak memory 201768 kb
Host smart-174b36f6-0335-4423-b412-03b8b2d3bab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991530014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2991530014
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3243757716
Short name T204
Test name
Test status
Simulation time 493553987236 ps
CPU time 320.77 seconds
Started May 19 01:33:44 PM PDT 24
Finished May 19 01:39:06 PM PDT 24
Peak memory 201880 kb
Host smart-314a9789-855f-48ee-8914-c9bda7b2da18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243757716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3243757716
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.90390973
Short name T557
Test name
Test status
Simulation time 320369461406 ps
CPU time 73.94 seconds
Started May 19 01:33:43 PM PDT 24
Finished May 19 01:34:58 PM PDT 24
Peak memory 201772 kb
Host smart-1fefe70c-edb5-4be9-81d5-a9f5ca0b145c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=90390973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt_
fixed.90390973
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2924075142
Short name T773
Test name
Test status
Simulation time 322965303160 ps
CPU time 174.81 seconds
Started May 19 01:33:38 PM PDT 24
Finished May 19 01:36:34 PM PDT 24
Peak memory 201764 kb
Host smart-648dd34d-0bf0-4418-9c24-775983221783
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924075142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2924075142
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3771100471
Short name T471
Test name
Test status
Simulation time 190125082325 ps
CPU time 446.44 seconds
Started May 19 01:33:35 PM PDT 24
Finished May 19 01:41:04 PM PDT 24
Peak memory 201808 kb
Host smart-1badd851-aba7-4a3e-a736-1dd60b3f9cce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771100471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3771100471
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2378594378
Short name T633
Test name
Test status
Simulation time 582719138352 ps
CPU time 374.16 seconds
Started May 19 01:33:34 PM PDT 24
Finished May 19 01:39:51 PM PDT 24
Peak memory 201780 kb
Host smart-eb8cf00a-9cf9-4d26-beaa-1f611ca811ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378594378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2378594378
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.782139470
Short name T44
Test name
Test status
Simulation time 74185007826 ps
CPU time 375.5 seconds
Started May 19 01:33:33 PM PDT 24
Finished May 19 01:39:52 PM PDT 24
Peak memory 202224 kb
Host smart-0ba70f0d-152c-4ebb-914e-fa6e7c762e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782139470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.782139470
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.191065646
Short name T477
Test name
Test status
Simulation time 22456998574 ps
CPU time 26.3 seconds
Started May 19 01:33:38 PM PDT 24
Finished May 19 01:34:06 PM PDT 24
Peak memory 201604 kb
Host smart-03891804-6a72-468a-a924-470da39fea35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191065646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.191065646
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3613433712
Short name T456
Test name
Test status
Simulation time 3065657638 ps
CPU time 7.73 seconds
Started May 19 01:33:33 PM PDT 24
Finished May 19 01:33:43 PM PDT 24
Peak memory 201580 kb
Host smart-ee7ed1e7-a2c7-4f51-b79c-e74b2d3d2a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613433712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3613433712
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1015295007
Short name T70
Test name
Test status
Simulation time 3980292485 ps
CPU time 5.62 seconds
Started May 19 01:33:33 PM PDT 24
Finished May 19 01:33:41 PM PDT 24
Peak memory 217296 kb
Host smart-5b5dc4f9-aa28-4204-9537-e2a95aac548b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015295007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1015295007
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.153283188
Short name T787
Test name
Test status
Simulation time 5905611711 ps
CPU time 15.66 seconds
Started May 19 01:33:57 PM PDT 24
Finished May 19 01:34:14 PM PDT 24
Peak memory 201604 kb
Host smart-74b94387-44d3-41da-9f70-3014270cb94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153283188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.153283188
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2157657638
Short name T720
Test name
Test status
Simulation time 503726867683 ps
CPU time 1233.11 seconds
Started May 19 01:33:44 PM PDT 24
Finished May 19 01:54:18 PM PDT 24
Peak memory 212688 kb
Host smart-5e28032e-1aba-4a60-b56c-13cc418bce48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157657638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2157657638
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.108894121
Short name T758
Test name
Test status
Simulation time 403149177 ps
CPU time 0.86 seconds
Started May 19 01:37:00 PM PDT 24
Finished May 19 01:37:01 PM PDT 24
Peak memory 201532 kb
Host smart-70d6bebb-5bce-4b6d-9df0-c8f8d47840b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108894121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.108894121
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1758021329
Short name T248
Test name
Test status
Simulation time 179134816189 ps
CPU time 78.79 seconds
Started May 19 01:36:55 PM PDT 24
Finished May 19 01:38:14 PM PDT 24
Peak memory 201888 kb
Host smart-9d0ea5ee-6f5c-45c1-b627-f9dc521ab484
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758021329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1758021329
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.4248985235
Short name T255
Test name
Test status
Simulation time 498043772117 ps
CPU time 303.15 seconds
Started May 19 01:36:50 PM PDT 24
Finished May 19 01:41:53 PM PDT 24
Peak memory 201760 kb
Host smart-0d2bfd14-db81-418d-8d69-585ac5624f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248985235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.4248985235
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1516514844
Short name T570
Test name
Test status
Simulation time 323552998111 ps
CPU time 751.85 seconds
Started May 19 01:36:50 PM PDT 24
Finished May 19 01:49:22 PM PDT 24
Peak memory 201800 kb
Host smart-c0612b0b-e2c6-4622-ba72-eea71eb261a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516514844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1516514844
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2775297167
Short name T724
Test name
Test status
Simulation time 328485587215 ps
CPU time 209.22 seconds
Started May 19 01:36:45 PM PDT 24
Finished May 19 01:40:14 PM PDT 24
Peak memory 201848 kb
Host smart-60634045-594a-4999-a5ea-a805a12f9115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775297167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2775297167
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.756645536
Short name T384
Test name
Test status
Simulation time 162738926409 ps
CPU time 208.9 seconds
Started May 19 01:36:49 PM PDT 24
Finished May 19 01:40:18 PM PDT 24
Peak memory 201752 kb
Host smart-ff90b48e-9e9e-4094-965b-d76cbbdf226e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=756645536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.756645536
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3860708826
Short name T301
Test name
Test status
Simulation time 514265398079 ps
CPU time 1152.11 seconds
Started May 19 01:36:54 PM PDT 24
Finished May 19 01:56:07 PM PDT 24
Peak memory 201864 kb
Host smart-70f2bcb0-22ee-49fb-939a-90a308a4c872
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860708826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3860708826
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2394387528
Short name T437
Test name
Test status
Simulation time 204283852931 ps
CPU time 234.85 seconds
Started May 19 01:36:55 PM PDT 24
Finished May 19 01:40:51 PM PDT 24
Peak memory 201828 kb
Host smart-16a60110-2fa6-433e-ac0d-fa0b9a2656df
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394387528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2394387528
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2461856468
Short name T727
Test name
Test status
Simulation time 134281384005 ps
CPU time 444.22 seconds
Started May 19 01:36:58 PM PDT 24
Finished May 19 01:44:23 PM PDT 24
Peak memory 202188 kb
Host smart-cb093da1-f6d0-49c1-bf94-0b419c1a24f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461856468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2461856468
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.4267723
Short name T509
Test name
Test status
Simulation time 22764327209 ps
CPU time 9.11 seconds
Started May 19 01:36:58 PM PDT 24
Finished May 19 01:37:08 PM PDT 24
Peak memory 201640 kb
Host smart-4187b6af-8bc2-4ab5-bca7-46e1435a5bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.4267723
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2861963230
Short name T199
Test name
Test status
Simulation time 3705115939 ps
CPU time 9.82 seconds
Started May 19 01:37:04 PM PDT 24
Finished May 19 01:37:14 PM PDT 24
Peak memory 201572 kb
Host smart-9215fa90-1fb6-421e-a28f-8b96050f7b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861963230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2861963230
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.4066798541
Short name T80
Test name
Test status
Simulation time 5980988459 ps
CPU time 7.72 seconds
Started May 19 01:36:46 PM PDT 24
Finished May 19 01:36:54 PM PDT 24
Peak memory 201632 kb
Host smart-79a9ec57-3954-47a2-8c98-83b92822f27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066798541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.4066798541
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2033002083
Short name T596
Test name
Test status
Simulation time 30021013521 ps
CPU time 65.97 seconds
Started May 19 01:36:59 PM PDT 24
Finished May 19 01:38:05 PM PDT 24
Peak memory 201616 kb
Host smart-1d691eb9-e780-4fb6-b5ad-c11122cdab15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033002083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2033002083
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.936629223
Short name T457
Test name
Test status
Simulation time 517216451 ps
CPU time 0.85 seconds
Started May 19 01:37:18 PM PDT 24
Finished May 19 01:37:19 PM PDT 24
Peak memory 201512 kb
Host smart-d2b28d99-4786-41da-8d74-95a7f4eac2e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936629223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.936629223
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1422122614
Short name T352
Test name
Test status
Simulation time 327118841942 ps
CPU time 763.14 seconds
Started May 19 01:37:06 PM PDT 24
Finished May 19 01:49:49 PM PDT 24
Peak memory 201868 kb
Host smart-834e9f10-6fc0-438c-ace8-ac6168c39a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422122614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1422122614
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.645560827
Short name T416
Test name
Test status
Simulation time 327002741960 ps
CPU time 81.64 seconds
Started May 19 01:37:03 PM PDT 24
Finished May 19 01:38:25 PM PDT 24
Peak memory 201820 kb
Host smart-7f1a79ac-de56-42be-9f12-2b5977ca59df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=645560827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrup
t_fixed.645560827
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1937715692
Short name T728
Test name
Test status
Simulation time 488093944124 ps
CPU time 595.82 seconds
Started May 19 01:37:07 PM PDT 24
Finished May 19 01:47:03 PM PDT 24
Peak memory 201792 kb
Host smart-7760c428-4d90-4fcf-a273-17fa424bac3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937715692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1937715692
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2475785889
Short name T527
Test name
Test status
Simulation time 484969828075 ps
CPU time 302.35 seconds
Started May 19 01:37:08 PM PDT 24
Finished May 19 01:42:11 PM PDT 24
Peak memory 201788 kb
Host smart-ff1608a8-8ba6-4db3-b9c0-75d8d9d2e480
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475785889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2475785889
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.626867756
Short name T708
Test name
Test status
Simulation time 554664560652 ps
CPU time 1333.15 seconds
Started May 19 01:37:10 PM PDT 24
Finished May 19 01:59:24 PM PDT 24
Peak memory 201884 kb
Host smart-0877601f-f2a0-42c4-9990-c9a8e9ad8310
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626867756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.626867756
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1078838734
Short name T371
Test name
Test status
Simulation time 383164284728 ps
CPU time 491.51 seconds
Started May 19 01:37:10 PM PDT 24
Finished May 19 01:45:22 PM PDT 24
Peak memory 201828 kb
Host smart-8556b90e-7795-441e-9c7a-4d23877fe81a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078838734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1078838734
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3871070385
Short name T393
Test name
Test status
Simulation time 26420208779 ps
CPU time 28.67 seconds
Started May 19 01:37:10 PM PDT 24
Finished May 19 01:37:39 PM PDT 24
Peak memory 201592 kb
Host smart-9bba99ee-cc37-421b-8e95-75471f8af393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871070385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3871070385
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3463846219
Short name T564
Test name
Test status
Simulation time 4958962068 ps
CPU time 7.13 seconds
Started May 19 01:37:10 PM PDT 24
Finished May 19 01:37:18 PM PDT 24
Peak memory 201816 kb
Host smart-94c8780d-9cf8-4966-8478-f5444606f4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463846219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3463846219
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1091792974
Short name T609
Test name
Test status
Simulation time 5685579129 ps
CPU time 13.29 seconds
Started May 19 01:37:02 PM PDT 24
Finished May 19 01:37:16 PM PDT 24
Peak memory 201652 kb
Host smart-12bfd834-e892-4b02-8bea-979f101fbc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091792974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1091792974
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2905002544
Short name T239
Test name
Test status
Simulation time 338414465017 ps
CPU time 1173.44 seconds
Started May 19 01:37:15 PM PDT 24
Finished May 19 01:56:50 PM PDT 24
Peak memory 210312 kb
Host smart-50e9d752-aad4-4997-b9ee-3bad99c1cca9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905002544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2905002544
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.31381494
Short name T298
Test name
Test status
Simulation time 45664821915 ps
CPU time 126.68 seconds
Started May 19 01:37:14 PM PDT 24
Finished May 19 01:39:21 PM PDT 24
Peak memory 210384 kb
Host smart-04ec4ffa-3eb3-4375-a695-b0088a74af86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31381494 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.31381494
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1615408842
Short name T166
Test name
Test status
Simulation time 522794811 ps
CPU time 0.88 seconds
Started May 19 01:37:24 PM PDT 24
Finished May 19 01:37:26 PM PDT 24
Peak memory 201524 kb
Host smart-fc92b113-dbe9-4862-84a3-1bc381de602c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615408842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1615408842
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1323695802
Short name T212
Test name
Test status
Simulation time 337302658329 ps
CPU time 776.34 seconds
Started May 19 01:37:20 PM PDT 24
Finished May 19 01:50:17 PM PDT 24
Peak memory 201892 kb
Host smart-4aa6ca14-dfb0-4c08-8591-89dc079a29df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323695802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1323695802
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1605610683
Short name T623
Test name
Test status
Simulation time 501908583490 ps
CPU time 556.74 seconds
Started May 19 01:37:19 PM PDT 24
Finished May 19 01:46:36 PM PDT 24
Peak memory 201784 kb
Host smart-9e9f46b8-ee69-489c-984b-2583bf2dd19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605610683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1605610683
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1268779363
Short name T307
Test name
Test status
Simulation time 499019537337 ps
CPU time 372.27 seconds
Started May 19 01:37:20 PM PDT 24
Finished May 19 01:43:32 PM PDT 24
Peak memory 201836 kb
Host smart-3045bfd5-2b40-43f1-880f-02ca9278a626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268779363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1268779363
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.564381583
Short name T403
Test name
Test status
Simulation time 170687168545 ps
CPU time 351.79 seconds
Started May 19 01:37:21 PM PDT 24
Finished May 19 01:43:13 PM PDT 24
Peak memory 201800 kb
Host smart-a5e8b5c9-98e4-4ad2-bbdb-7f9604cf2232
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=564381583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.564381583
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2428828216
Short name T449
Test name
Test status
Simulation time 493090149835 ps
CPU time 1093.83 seconds
Started May 19 01:37:16 PM PDT 24
Finished May 19 01:55:30 PM PDT 24
Peak memory 202104 kb
Host smart-67369638-ff7c-469a-a2c1-42f3185e232c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428828216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2428828216
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.1965169295
Short name T465
Test name
Test status
Simulation time 323422040701 ps
CPU time 777.21 seconds
Started May 19 01:37:23 PM PDT 24
Finished May 19 01:50:21 PM PDT 24
Peak memory 201784 kb
Host smart-c2fa55c9-01ce-42aa-98de-d052ac9e509b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965169295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.1965169295
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3150544068
Short name T687
Test name
Test status
Simulation time 202163533153 ps
CPU time 116.83 seconds
Started May 19 01:37:24 PM PDT 24
Finished May 19 01:39:21 PM PDT 24
Peak memory 201804 kb
Host smart-43557b0e-89cc-4636-8e8a-dd460936585e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150544068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3150544068
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1048616866
Short name T791
Test name
Test status
Simulation time 108295762970 ps
CPU time 457.17 seconds
Started May 19 01:37:25 PM PDT 24
Finished May 19 01:45:02 PM PDT 24
Peak memory 202208 kb
Host smart-b571b77a-10d9-44d4-898b-3fe86c68abae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048616866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1048616866
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3810372215
Short name T753
Test name
Test status
Simulation time 35461353009 ps
CPU time 77.38 seconds
Started May 19 01:37:25 PM PDT 24
Finished May 19 01:38:43 PM PDT 24
Peak memory 201632 kb
Host smart-2522df36-c45c-4898-b24d-92b798f8f365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810372215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3810372215
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.42349230
Short name T603
Test name
Test status
Simulation time 4987426298 ps
CPU time 12.93 seconds
Started May 19 01:37:23 PM PDT 24
Finished May 19 01:37:37 PM PDT 24
Peak memory 201620 kb
Host smart-20c938c0-a5d2-4bc1-a1bd-b4306bd0ef3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42349230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.42349230
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1462787232
Short name T389
Test name
Test status
Simulation time 5930941821 ps
CPU time 8.39 seconds
Started May 19 01:37:15 PM PDT 24
Finished May 19 01:37:24 PM PDT 24
Peak memory 201644 kb
Host smart-ccc48fe1-ae36-4955-884c-1c6faa6ae2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462787232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1462787232
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1747246668
Short name T33
Test name
Test status
Simulation time 143520928034 ps
CPU time 559.83 seconds
Started May 19 01:37:24 PM PDT 24
Finished May 19 01:46:44 PM PDT 24
Peak memory 202100 kb
Host smart-e6542b1f-f652-4090-8a39-df19d27e9214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747246668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1747246668
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1581147747
Short name T216
Test name
Test status
Simulation time 253696256623 ps
CPU time 119.22 seconds
Started May 19 01:37:25 PM PDT 24
Finished May 19 01:39:25 PM PDT 24
Peak memory 210124 kb
Host smart-85f709eb-715f-48f2-b1cb-a2b40d8fd7ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581147747 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1581147747
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1190837884
Short name T510
Test name
Test status
Simulation time 523293983 ps
CPU time 1.84 seconds
Started May 19 01:37:34 PM PDT 24
Finished May 19 01:37:37 PM PDT 24
Peak memory 201544 kb
Host smart-917be4d6-0767-4f3e-af85-2674473cbe96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190837884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1190837884
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2521372345
Short name T130
Test name
Test status
Simulation time 332671740004 ps
CPU time 800.54 seconds
Started May 19 01:37:31 PM PDT 24
Finished May 19 01:50:52 PM PDT 24
Peak memory 201764 kb
Host smart-cf06953e-05ea-479f-88ee-4a9919a5aeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521372345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2521372345
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3300034290
Short name T585
Test name
Test status
Simulation time 169298406699 ps
CPU time 75.94 seconds
Started May 19 01:37:28 PM PDT 24
Finished May 19 01:38:44 PM PDT 24
Peak memory 201784 kb
Host smart-cf44c149-6d98-4f6c-9bf6-926637059025
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300034290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.3300034290
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2139874589
Short name T485
Test name
Test status
Simulation time 326662390109 ps
CPU time 173.55 seconds
Started May 19 01:37:32 PM PDT 24
Finished May 19 01:40:26 PM PDT 24
Peak memory 201740 kb
Host smart-af493179-d8b1-4ea2-93a6-01ab0461ee12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139874589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2139874589
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2102969926
Short name T463
Test name
Test status
Simulation time 326028072580 ps
CPU time 179.17 seconds
Started May 19 01:37:29 PM PDT 24
Finished May 19 01:40:28 PM PDT 24
Peak memory 201796 kb
Host smart-b2004674-19b2-45fa-987e-29d24e52e927
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102969926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2102969926
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.4050968004
Short name T266
Test name
Test status
Simulation time 538535337842 ps
CPU time 1333.04 seconds
Started May 19 01:37:30 PM PDT 24
Finished May 19 01:59:43 PM PDT 24
Peak memory 201920 kb
Host smart-0508df6d-eaf4-41eb-9562-c2ae96c61c93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050968004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.4050968004
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2334350150
Short name T560
Test name
Test status
Simulation time 417315096475 ps
CPU time 275.46 seconds
Started May 19 01:37:29 PM PDT 24
Finished May 19 01:42:05 PM PDT 24
Peak memory 201804 kb
Host smart-27870473-34fe-4cff-bd48-5eb4502f5bbd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334350150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2334350150
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2907284912
Short name T439
Test name
Test status
Simulation time 73609280826 ps
CPU time 374.64 seconds
Started May 19 01:37:33 PM PDT 24
Finished May 19 01:43:49 PM PDT 24
Peak memory 202128 kb
Host smart-c9a7d08a-bf27-425f-bbed-5d56244a3b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907284912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2907284912
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1465148096
Short name T87
Test name
Test status
Simulation time 35576967485 ps
CPU time 10.16 seconds
Started May 19 01:37:36 PM PDT 24
Finished May 19 01:37:47 PM PDT 24
Peak memory 201640 kb
Host smart-b3e0a25b-6270-4dc3-a8de-3b6e0322be43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465148096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1465148096
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.551613827
Short name T200
Test name
Test status
Simulation time 3324945638 ps
CPU time 8.89 seconds
Started May 19 01:37:34 PM PDT 24
Finished May 19 01:37:43 PM PDT 24
Peak memory 201556 kb
Host smart-3adee9ee-3387-4914-b0ef-bf6c469bc232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551613827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.551613827
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1721819081
Short name T734
Test name
Test status
Simulation time 5648229415 ps
CPU time 13.17 seconds
Started May 19 01:37:26 PM PDT 24
Finished May 19 01:37:39 PM PDT 24
Peak memory 201636 kb
Host smart-0f0b48bd-6978-48e9-ba80-f07394718140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721819081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1721819081
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.445488326
Short name T232
Test name
Test status
Simulation time 160591191149 ps
CPU time 349.26 seconds
Started May 19 01:37:34 PM PDT 24
Finished May 19 01:43:24 PM PDT 24
Peak memory 202356 kb
Host smart-db9c1399-2b07-4491-a1e4-577bd38d177d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445488326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
445488326
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1119339389
Short name T15
Test name
Test status
Simulation time 21418548714 ps
CPU time 54.99 seconds
Started May 19 01:37:34 PM PDT 24
Finished May 19 01:38:30 PM PDT 24
Peak memory 210332 kb
Host smart-e234322d-308d-4bd3-a76c-a04125b143dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119339389 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1119339389
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.782013889
Short name T378
Test name
Test status
Simulation time 542959820 ps
CPU time 0.78 seconds
Started May 19 01:37:49 PM PDT 24
Finished May 19 01:37:50 PM PDT 24
Peak memory 201532 kb
Host smart-5c5d52e1-60e5-4d20-8971-b3b2119cc342
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782013889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.782013889
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1807959541
Short name T666
Test name
Test status
Simulation time 370318623635 ps
CPU time 815.83 seconds
Started May 19 01:37:45 PM PDT 24
Finished May 19 01:51:22 PM PDT 24
Peak memory 201780 kb
Host smart-020d4ab5-624d-4f7a-9d89-2c1e4237edf7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807959541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1807959541
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2770474576
Short name T344
Test name
Test status
Simulation time 174299686845 ps
CPU time 86.65 seconds
Started May 19 01:37:49 PM PDT 24
Finished May 19 01:39:16 PM PDT 24
Peak memory 201816 kb
Host smart-a9e1821e-2180-48e6-8586-7f8daf6e5ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770474576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2770474576
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.793424953
Short name T578
Test name
Test status
Simulation time 490316729555 ps
CPU time 325.86 seconds
Started May 19 01:37:41 PM PDT 24
Finished May 19 01:43:07 PM PDT 24
Peak memory 201892 kb
Host smart-dfd3414b-bc93-4fe6-b4c3-765068b3a724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793424953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.793424953
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1259772894
Short name T619
Test name
Test status
Simulation time 329827066348 ps
CPU time 195.66 seconds
Started May 19 01:37:45 PM PDT 24
Finished May 19 01:41:01 PM PDT 24
Peak memory 201768 kb
Host smart-9dd0ecbe-2fb1-483d-b2ce-46e7e02484cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259772894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1259772894
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1292960165
Short name T191
Test name
Test status
Simulation time 323872878068 ps
CPU time 197.04 seconds
Started May 19 01:37:38 PM PDT 24
Finished May 19 01:40:56 PM PDT 24
Peak memory 201764 kb
Host smart-f7d3f44b-247d-425e-afb2-79f17f6f497a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292960165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1292960165
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.1436900904
Short name T84
Test name
Test status
Simulation time 495389255689 ps
CPU time 416.32 seconds
Started May 19 01:37:39 PM PDT 24
Finished May 19 01:44:36 PM PDT 24
Peak memory 201792 kb
Host smart-2ec830d8-aa8c-4d70-8d57-0a8ffeb76ee6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436900904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.1436900904
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2359326144
Short name T180
Test name
Test status
Simulation time 584113700786 ps
CPU time 329.1 seconds
Started May 19 01:37:50 PM PDT 24
Finished May 19 01:43:19 PM PDT 24
Peak memory 201840 kb
Host smart-0c7cb802-049e-4664-8f7d-aad16da9edef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359326144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2359326144
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.537485138
Short name T431
Test name
Test status
Simulation time 588876826926 ps
CPU time 1362.39 seconds
Started May 19 01:37:45 PM PDT 24
Finished May 19 02:00:28 PM PDT 24
Peak memory 202080 kb
Host smart-e90c8598-69ee-426e-b94e-00dd6869217a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537485138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.537485138
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1950752715
Short name T237
Test name
Test status
Simulation time 113304589481 ps
CPU time 599.38 seconds
Started May 19 01:37:50 PM PDT 24
Finished May 19 01:47:50 PM PDT 24
Peak memory 202012 kb
Host smart-6b3a8628-54ec-444e-8571-64e637cebd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950752715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1950752715
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1596207409
Short name T610
Test name
Test status
Simulation time 26483129852 ps
CPU time 15.08 seconds
Started May 19 01:37:48 PM PDT 24
Finished May 19 01:38:04 PM PDT 24
Peak memory 201636 kb
Host smart-1f6fe21c-eb14-47c0-88dc-056c3b597948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596207409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1596207409
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3352587104
Short name T194
Test name
Test status
Simulation time 3221084047 ps
CPU time 4.38 seconds
Started May 19 01:37:50 PM PDT 24
Finished May 19 01:37:55 PM PDT 24
Peak memory 201584 kb
Host smart-a33dffd4-11da-4a8f-81ab-4dbe34757d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352587104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3352587104
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.416689269
Short name T634
Test name
Test status
Simulation time 6076905555 ps
CPU time 6.45 seconds
Started May 19 01:37:34 PM PDT 24
Finished May 19 01:37:42 PM PDT 24
Peak memory 201604 kb
Host smart-b37edc1c-3532-48df-b94a-6edd16e71839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416689269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.416689269
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.4151604224
Short name T28
Test name
Test status
Simulation time 172940516142 ps
CPU time 208.59 seconds
Started May 19 01:37:49 PM PDT 24
Finished May 19 01:41:18 PM PDT 24
Peak memory 201824 kb
Host smart-94cc7d32-eb01-4412-aff8-4224c1c5b30d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151604224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.4151604224
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3466858293
Short name T755
Test name
Test status
Simulation time 459807335 ps
CPU time 0.88 seconds
Started May 19 01:38:16 PM PDT 24
Finished May 19 01:38:17 PM PDT 24
Peak memory 201544 kb
Host smart-a6a410ba-12b0-43c3-9f9b-fe0662c19b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466858293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3466858293
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.972386284
Short name T579
Test name
Test status
Simulation time 172523782936 ps
CPU time 397.15 seconds
Started May 19 01:38:00 PM PDT 24
Finished May 19 01:44:37 PM PDT 24
Peak memory 201904 kb
Host smart-806652f7-6eb3-41bc-a7bb-ec203af4a45a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972386284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.972386284
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3138882418
Short name T312
Test name
Test status
Simulation time 528944275336 ps
CPU time 297.12 seconds
Started May 19 01:38:00 PM PDT 24
Finished May 19 01:42:57 PM PDT 24
Peak memory 201808 kb
Host smart-cdd60edf-abb7-41c7-a785-9a2b556e33b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138882418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3138882418
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2249590157
Short name T691
Test name
Test status
Simulation time 161642560042 ps
CPU time 42.55 seconds
Started May 19 01:37:54 PM PDT 24
Finished May 19 01:38:37 PM PDT 24
Peak memory 202020 kb
Host smart-ef014e38-df91-4ca0-bfdf-bc9e9651a72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249590157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2249590157
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3310998813
Short name T387
Test name
Test status
Simulation time 495923022530 ps
CPU time 172.35 seconds
Started May 19 01:37:53 PM PDT 24
Finished May 19 01:40:46 PM PDT 24
Peak memory 201748 kb
Host smart-dc2abb28-20ef-4e9c-bf84-a9e466f29f2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310998813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3310998813
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.4062120754
Short name T304
Test name
Test status
Simulation time 327943058515 ps
CPU time 725.05 seconds
Started May 19 01:37:48 PM PDT 24
Finished May 19 01:49:54 PM PDT 24
Peak memory 201676 kb
Host smart-841831f6-8f09-44c8-9261-fb523e17479a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062120754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.4062120754
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.727986896
Short name T559
Test name
Test status
Simulation time 490689459577 ps
CPU time 1065.83 seconds
Started May 19 01:37:54 PM PDT 24
Finished May 19 01:55:40 PM PDT 24
Peak memory 201828 kb
Host smart-a3862eec-4965-4438-8ec8-ed79056e2a12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=727986896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.727986896
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.4109188462
Short name T571
Test name
Test status
Simulation time 360262248371 ps
CPU time 872.31 seconds
Started May 19 01:38:00 PM PDT 24
Finished May 19 01:52:34 PM PDT 24
Peak memory 201916 kb
Host smart-6bc08b51-3642-49f3-a550-7574a6bc65e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109188462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.4109188462
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1156205123
Short name T186
Test name
Test status
Simulation time 387186628884 ps
CPU time 110.79 seconds
Started May 19 01:38:00 PM PDT 24
Finished May 19 01:39:52 PM PDT 24
Peak memory 201764 kb
Host smart-ec1df901-c0d8-4de6-9ce5-5e0aaeed260c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156205123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1156205123
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2114834735
Short name T231
Test name
Test status
Simulation time 97429055576 ps
CPU time 404.49 seconds
Started May 19 01:38:05 PM PDT 24
Finished May 19 01:44:49 PM PDT 24
Peak memory 202192 kb
Host smart-85729b21-09a3-4c00-bacf-4bb5a7df6948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114834735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2114834735
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2683478049
Short name T652
Test name
Test status
Simulation time 38550538405 ps
CPU time 46.55 seconds
Started May 19 01:38:00 PM PDT 24
Finished May 19 01:38:47 PM PDT 24
Peak memory 201580 kb
Host smart-ee97f342-085a-4c2d-981d-55ec2dfb54f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683478049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2683478049
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2441848433
Short name T537
Test name
Test status
Simulation time 3858979713 ps
CPU time 5.28 seconds
Started May 19 01:38:00 PM PDT 24
Finished May 19 01:38:06 PM PDT 24
Peak memory 201540 kb
Host smart-e6c8c409-fdbb-4c07-8dab-75a756856ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441848433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2441848433
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2096568836
Short name T625
Test name
Test status
Simulation time 5849444233 ps
CPU time 2.73 seconds
Started May 19 01:37:51 PM PDT 24
Finished May 19 01:37:54 PM PDT 24
Peak memory 201652 kb
Host smart-6bcce7fc-e55c-4b52-94d3-7e875a69a22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096568836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2096568836
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.164121445
Short name T692
Test name
Test status
Simulation time 128886865118 ps
CPU time 424.42 seconds
Started May 19 01:38:05 PM PDT 24
Finished May 19 01:45:10 PM PDT 24
Peak memory 211504 kb
Host smart-39ec52a6-7627-41df-8161-b3e078b9864b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164121445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.
164121445
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.829097864
Short name T762
Test name
Test status
Simulation time 365239530 ps
CPU time 0.75 seconds
Started May 19 01:38:15 PM PDT 24
Finished May 19 01:38:16 PM PDT 24
Peak memory 201508 kb
Host smart-73bb7378-cbf7-42d0-bbf4-19b4aa954b6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829097864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.829097864
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1995527566
Short name T279
Test name
Test status
Simulation time 569696474303 ps
CPU time 1375.89 seconds
Started May 19 01:38:11 PM PDT 24
Finished May 19 02:01:08 PM PDT 24
Peak memory 201816 kb
Host smart-aa4b8099-4dd8-4c3a-a8dc-1a6ef93afed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995527566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1995527566
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3725818333
Short name T467
Test name
Test status
Simulation time 164034601434 ps
CPU time 413.58 seconds
Started May 19 01:38:10 PM PDT 24
Finished May 19 01:45:04 PM PDT 24
Peak memory 201836 kb
Host smart-16ca3ebf-016e-4111-8cfe-1ba915567c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725818333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3725818333
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.4083968799
Short name T459
Test name
Test status
Simulation time 491399856697 ps
CPU time 1146.47 seconds
Started May 19 01:38:15 PM PDT 24
Finished May 19 01:57:22 PM PDT 24
Peak memory 201760 kb
Host smart-68588997-cf88-4143-a8ef-69c2bb51bec0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083968799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.4083968799
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2462026059
Short name T179
Test name
Test status
Simulation time 327618757662 ps
CPU time 786.71 seconds
Started May 19 01:38:14 PM PDT 24
Finished May 19 01:51:21 PM PDT 24
Peak memory 201796 kb
Host smart-ee32f788-6a5f-496e-b672-d5e24d9fc5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462026059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2462026059
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2626466349
Short name T413
Test name
Test status
Simulation time 488494347644 ps
CPU time 1090.08 seconds
Started May 19 01:38:14 PM PDT 24
Finished May 19 01:56:24 PM PDT 24
Peak memory 201860 kb
Host smart-60d94bca-8591-4df8-a10a-7a8dba55bfcb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626466349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2626466349
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3735928249
Short name T322
Test name
Test status
Simulation time 379535437788 ps
CPU time 436.24 seconds
Started May 19 01:38:14 PM PDT 24
Finished May 19 01:45:31 PM PDT 24
Peak memory 201900 kb
Host smart-6a935720-2f13-4f82-be12-57748b3c64f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735928249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3735928249
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1258636209
Short name T664
Test name
Test status
Simulation time 199407134674 ps
CPU time 95.64 seconds
Started May 19 01:38:09 PM PDT 24
Finished May 19 01:39:45 PM PDT 24
Peak memory 201840 kb
Host smart-26e1b5fd-ae05-4007-a45d-7953ebdaef79
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258636209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1258636209
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2478549651
Short name T100
Test name
Test status
Simulation time 124385850146 ps
CPU time 412.88 seconds
Started May 19 01:38:16 PM PDT 24
Finished May 19 01:45:10 PM PDT 24
Peak memory 202144 kb
Host smart-36b79436-10c3-454a-b525-efbb3b4308b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478549651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2478549651
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3622472653
Short name T712
Test name
Test status
Simulation time 28137276698 ps
CPU time 11.87 seconds
Started May 19 01:38:10 PM PDT 24
Finished May 19 01:38:22 PM PDT 24
Peak memory 201880 kb
Host smart-3e72347d-ab31-470e-b040-0c1f2d043f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622472653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3622472653
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2106049506
Short name T391
Test name
Test status
Simulation time 3225344410 ps
CPU time 7.75 seconds
Started May 19 01:38:12 PM PDT 24
Finished May 19 01:38:20 PM PDT 24
Peak memory 201592 kb
Host smart-2a11834a-c9ea-4e5a-8212-0b2b3d400546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106049506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2106049506
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2716387752
Short name T411
Test name
Test status
Simulation time 6104240292 ps
CPU time 1.88 seconds
Started May 19 01:38:11 PM PDT 24
Finished May 19 01:38:14 PM PDT 24
Peak memory 201644 kb
Host smart-701aad62-5f5b-4517-83f7-dd30383cdb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716387752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2716387752
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.620861348
Short name T169
Test name
Test status
Simulation time 172329363022 ps
CPU time 371.04 seconds
Started May 19 01:38:15 PM PDT 24
Finished May 19 01:44:26 PM PDT 24
Peak memory 201900 kb
Host smart-f4b474b9-f41b-4c97-8b91-2166a4d34e6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620861348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
620861348
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1571300213
Short name T612
Test name
Test status
Simulation time 406579857895 ps
CPU time 343.14 seconds
Started May 19 01:38:18 PM PDT 24
Finished May 19 01:44:01 PM PDT 24
Peak memory 210436 kb
Host smart-e50a18e6-63b7-4b16-b85a-c9e85cd052ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571300213 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1571300213
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.62479930
Short name T493
Test name
Test status
Simulation time 299591698 ps
CPU time 1.28 seconds
Started May 19 01:38:34 PM PDT 24
Finished May 19 01:38:35 PM PDT 24
Peak memory 201476 kb
Host smart-60bc46ce-d31d-4afc-b5f4-d7d12c7e26d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62479930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.62479930
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2400911699
Short name T107
Test name
Test status
Simulation time 383097761265 ps
CPU time 956.89 seconds
Started May 19 01:38:27 PM PDT 24
Finished May 19 01:54:25 PM PDT 24
Peak memory 201900 kb
Host smart-7c86393c-8d2e-459e-bc8d-f019b03d0fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400911699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2400911699
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1478064814
Short name T355
Test name
Test status
Simulation time 165639134752 ps
CPU time 354.71 seconds
Started May 19 01:38:19 PM PDT 24
Finished May 19 01:44:14 PM PDT 24
Peak memory 201800 kb
Host smart-bb2f3ebd-d5d8-403e-aa69-9363db9bcb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478064814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1478064814
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2800617985
Short name T433
Test name
Test status
Simulation time 162895385983 ps
CPU time 107.71 seconds
Started May 19 01:38:23 PM PDT 24
Finished May 19 01:40:11 PM PDT 24
Peak memory 201824 kb
Host smart-c54f4006-16af-4462-9f1d-a3b210e60ebc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800617985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2800617985
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1880675139
Short name T177
Test name
Test status
Simulation time 493378226488 ps
CPU time 295.72 seconds
Started May 19 01:38:23 PM PDT 24
Finished May 19 01:43:19 PM PDT 24
Peak memory 201880 kb
Host smart-7bf423a9-542a-4b3c-8f0f-b7d76404833d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880675139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1880675139
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.35262624
Short name T565
Test name
Test status
Simulation time 325368988674 ps
CPU time 405.45 seconds
Started May 19 01:38:19 PM PDT 24
Finished May 19 01:45:05 PM PDT 24
Peak memory 201764 kb
Host smart-6167b4f5-4aa1-4416-9793-dc16e7077ebf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=35262624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixed
.35262624
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.250785137
Short name T288
Test name
Test status
Simulation time 363661484989 ps
CPU time 398.43 seconds
Started May 19 01:38:25 PM PDT 24
Finished May 19 01:45:04 PM PDT 24
Peak memory 201920 kb
Host smart-74654cf1-ac39-4679-908d-6430742ceef4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250785137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.250785137
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.429538602
Short name T436
Test name
Test status
Simulation time 198447547738 ps
CPU time 80.28 seconds
Started May 19 01:38:26 PM PDT 24
Finished May 19 01:39:48 PM PDT 24
Peak memory 201836 kb
Host smart-59f5593b-13b0-4fb5-84fe-c2b297463426
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429538602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.429538602
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1890372042
Short name T41
Test name
Test status
Simulation time 101221293379 ps
CPU time 378.29 seconds
Started May 19 01:38:30 PM PDT 24
Finished May 19 01:44:49 PM PDT 24
Peak memory 202204 kb
Host smart-ed2e4c26-7b63-4547-9539-da73c762cdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890372042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1890372042
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2616765817
Short name T381
Test name
Test status
Simulation time 41353868997 ps
CPU time 27.4 seconds
Started May 19 01:38:26 PM PDT 24
Finished May 19 01:38:55 PM PDT 24
Peak memory 201628 kb
Host smart-93f7a7c9-0d82-4223-9802-0720c5b82fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616765817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2616765817
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2917782262
Short name T478
Test name
Test status
Simulation time 4136452994 ps
CPU time 3.64 seconds
Started May 19 01:38:24 PM PDT 24
Finished May 19 01:38:28 PM PDT 24
Peak memory 201576 kb
Host smart-5dabba02-408c-4134-9dc3-f4bc90bdd0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917782262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2917782262
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.4190185416
Short name T72
Test name
Test status
Simulation time 5685231477 ps
CPU time 7.28 seconds
Started May 19 01:38:16 PM PDT 24
Finished May 19 01:38:23 PM PDT 24
Peak memory 201604 kb
Host smart-8eccafd5-a7e8-485a-8b98-5e4466fdd811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190185416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.4190185416
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.697630867
Short name T341
Test name
Test status
Simulation time 542211185702 ps
CPU time 324.08 seconds
Started May 19 01:38:28 PM PDT 24
Finished May 19 01:43:53 PM PDT 24
Peak memory 201820 kb
Host smart-0a374f27-6bfb-4b7f-be29-f41154dc2892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697630867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
697630867
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1837008788
Short name T89
Test name
Test status
Simulation time 59911017441 ps
CPU time 119.29 seconds
Started May 19 01:38:29 PM PDT 24
Finished May 19 01:40:29 PM PDT 24
Peak memory 217748 kb
Host smart-d3fc3dc3-1fcc-44c8-9be7-aec8f6e2f22d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837008788 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1837008788
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3303930765
Short name T747
Test name
Test status
Simulation time 452396579 ps
CPU time 1.69 seconds
Started May 19 01:38:45 PM PDT 24
Finished May 19 01:38:47 PM PDT 24
Peak memory 201516 kb
Host smart-d37a1bce-2565-4f46-b57c-0df213af8a5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303930765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3303930765
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3491825022
Short name T774
Test name
Test status
Simulation time 161100279381 ps
CPU time 101.64 seconds
Started May 19 01:38:38 PM PDT 24
Finished May 19 01:40:20 PM PDT 24
Peak memory 201872 kb
Host smart-17e14bb4-e375-4d29-a44b-86b020f943ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491825022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3491825022
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.497634039
Short name T285
Test name
Test status
Simulation time 170771065169 ps
CPU time 377.57 seconds
Started May 19 01:38:41 PM PDT 24
Finished May 19 01:44:59 PM PDT 24
Peak memory 201784 kb
Host smart-3f0fb963-5388-4232-9d4c-ea9abc9facf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497634039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.497634039
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2812533113
Short name T161
Test name
Test status
Simulation time 492277592921 ps
CPU time 1230.33 seconds
Started May 19 01:38:39 PM PDT 24
Finished May 19 01:59:10 PM PDT 24
Peak memory 201824 kb
Host smart-d3b06bff-c41b-40c5-881e-b09134288ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812533113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2812533113
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2494625597
Short name T473
Test name
Test status
Simulation time 496494996895 ps
CPU time 578.28 seconds
Started May 19 01:38:39 PM PDT 24
Finished May 19 01:48:18 PM PDT 24
Peak memory 201804 kb
Host smart-55d599e3-023f-46be-b262-09db84937ff5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494625597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.2494625597
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2622618656
Short name T350
Test name
Test status
Simulation time 162942375048 ps
CPU time 118.88 seconds
Started May 19 01:38:35 PM PDT 24
Finished May 19 01:40:34 PM PDT 24
Peak memory 201760 kb
Host smart-40b0b301-789b-4842-85c6-d57d0cc50f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622618656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2622618656
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2454483585
Short name T680
Test name
Test status
Simulation time 323682615456 ps
CPU time 749.33 seconds
Started May 19 01:38:34 PM PDT 24
Finished May 19 01:51:04 PM PDT 24
Peak memory 201804 kb
Host smart-39595a34-7b54-40f9-8c93-af5fdf46d7bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454483585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2454483585
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2346113676
Short name T515
Test name
Test status
Simulation time 512738114620 ps
CPU time 1252.68 seconds
Started May 19 01:38:40 PM PDT 24
Finished May 19 01:59:33 PM PDT 24
Peak memory 201796 kb
Host smart-cef58161-83fb-4236-b119-d758423c10e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346113676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2346113676
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2744761722
Short name T25
Test name
Test status
Simulation time 402438170251 ps
CPU time 514.86 seconds
Started May 19 01:38:39 PM PDT 24
Finished May 19 01:47:15 PM PDT 24
Peak memory 201792 kb
Host smart-f59fa5cc-909f-4f79-977d-a9460f63499f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744761722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2744761722
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1469062958
Short name T228
Test name
Test status
Simulation time 122072194018 ps
CPU time 477.14 seconds
Started May 19 01:38:40 PM PDT 24
Finished May 19 01:46:38 PM PDT 24
Peak memory 202124 kb
Host smart-fb587d7b-cefd-490e-b85d-c34ef6b74907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469062958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1469062958
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1113595013
Short name T208
Test name
Test status
Simulation time 22091102723 ps
CPU time 14.39 seconds
Started May 19 01:38:41 PM PDT 24
Finished May 19 01:38:56 PM PDT 24
Peak memory 201592 kb
Host smart-f94bb581-c978-4acb-9fce-e1ae38fe15ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113595013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1113595013
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1154809139
Short name T458
Test name
Test status
Simulation time 4915867616 ps
CPU time 6.54 seconds
Started May 19 01:38:40 PM PDT 24
Finished May 19 01:38:46 PM PDT 24
Peak memory 201544 kb
Host smart-a9181725-51d9-44f6-8d54-ebffe4080432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154809139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1154809139
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3631689266
Short name T30
Test name
Test status
Simulation time 5800327039 ps
CPU time 3.78 seconds
Started May 19 01:38:35 PM PDT 24
Finished May 19 01:38:39 PM PDT 24
Peak memory 201596 kb
Host smart-ff756889-0926-45b5-92bc-a8f3429e60f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631689266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3631689266
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1474465173
Short name T653
Test name
Test status
Simulation time 186318569836 ps
CPU time 107.47 seconds
Started May 19 01:38:45 PM PDT 24
Finished May 19 01:40:33 PM PDT 24
Peak memory 211116 kb
Host smart-9ab7f4db-08ca-4f47-b9d4-4885d599a813
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474465173 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1474465173
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.838215623
Short name T671
Test name
Test status
Simulation time 335553404 ps
CPU time 1.37 seconds
Started May 19 01:38:54 PM PDT 24
Finished May 19 01:38:55 PM PDT 24
Peak memory 201476 kb
Host smart-e6f43066-9fe7-4429-b615-18c6aa3b35e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838215623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.838215623
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2231272238
Short name T356
Test name
Test status
Simulation time 512025291053 ps
CPU time 222.34 seconds
Started May 19 01:38:48 PM PDT 24
Finished May 19 01:42:30 PM PDT 24
Peak memory 201788 kb
Host smart-b24fb3cc-c865-40ec-a8e8-1951814a09a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231272238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2231272238
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1402540959
Short name T99
Test name
Test status
Simulation time 166270339976 ps
CPU time 371.71 seconds
Started May 19 01:38:48 PM PDT 24
Finished May 19 01:45:00 PM PDT 24
Peak memory 201820 kb
Host smart-37ff8336-975d-44a5-9a4b-396e443642da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402540959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1402540959
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1950521266
Short name T706
Test name
Test status
Simulation time 161561425509 ps
CPU time 378.89 seconds
Started May 19 01:38:44 PM PDT 24
Finished May 19 01:45:03 PM PDT 24
Peak memory 201840 kb
Host smart-d97b7428-fd74-450e-a102-9e18463c8758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950521266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1950521266
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3651360905
Short name T71
Test name
Test status
Simulation time 159775000252 ps
CPU time 376.29 seconds
Started May 19 01:38:45 PM PDT 24
Finished May 19 01:45:02 PM PDT 24
Peak memory 201828 kb
Host smart-9b9e69e3-f319-4780-9543-4bcea1d19db0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651360905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3651360905
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3589972843
Short name T726
Test name
Test status
Simulation time 497854480239 ps
CPU time 624.16 seconds
Started May 19 01:38:43 PM PDT 24
Finished May 19 01:49:08 PM PDT 24
Peak memory 202040 kb
Host smart-74d82029-e98c-41fa-9bce-57970427a6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589972843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3589972843
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.4145497552
Short name T168
Test name
Test status
Simulation time 158355424669 ps
CPU time 352.13 seconds
Started May 19 01:38:45 PM PDT 24
Finished May 19 01:44:38 PM PDT 24
Peak memory 201804 kb
Host smart-d6e1b5b0-122f-4953-b8d4-8af8835ca890
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145497552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.4145497552
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.986743639
Short name T158
Test name
Test status
Simulation time 529947650071 ps
CPU time 596.48 seconds
Started May 19 01:38:45 PM PDT 24
Finished May 19 01:48:42 PM PDT 24
Peak memory 201788 kb
Host smart-116906fb-be25-4c52-b115-e9bad26fac86
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986743639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.986743639
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2137727954
Short name T370
Test name
Test status
Simulation time 610398088954 ps
CPU time 292.45 seconds
Started May 19 01:38:49 PM PDT 24
Finished May 19 01:43:42 PM PDT 24
Peak memory 201772 kb
Host smart-d476fa7a-a978-417f-9ebd-0fa885c1efa1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137727954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2137727954
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3316195390
Short name T226
Test name
Test status
Simulation time 103435757857 ps
CPU time 325.83 seconds
Started May 19 01:38:49 PM PDT 24
Finished May 19 01:44:15 PM PDT 24
Peak memory 202184 kb
Host smart-8d1655f3-ae2c-4afb-9434-377994714639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316195390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3316195390
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2723018242
Short name T494
Test name
Test status
Simulation time 22876629373 ps
CPU time 9.7 seconds
Started May 19 01:38:48 PM PDT 24
Finished May 19 01:38:58 PM PDT 24
Peak memory 201660 kb
Host smart-f6132d7a-1448-492f-92c9-4539d0d00c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723018242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2723018242
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2793237793
Short name T415
Test name
Test status
Simulation time 5601221564 ps
CPU time 4.97 seconds
Started May 19 01:38:48 PM PDT 24
Finished May 19 01:38:53 PM PDT 24
Peak memory 201596 kb
Host smart-0850a58a-03bd-4cd6-b6ca-19d8b8508b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793237793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2793237793
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3490082514
Short name T520
Test name
Test status
Simulation time 5596243294 ps
CPU time 6.5 seconds
Started May 19 01:38:44 PM PDT 24
Finished May 19 01:38:51 PM PDT 24
Peak memory 201652 kb
Host smart-87c85a70-869e-40e4-a2c0-2c76262acaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490082514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3490082514
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.3478425717
Short name T568
Test name
Test status
Simulation time 180070574291 ps
CPU time 645.82 seconds
Started May 19 01:38:54 PM PDT 24
Finished May 19 01:49:41 PM PDT 24
Peak memory 202168 kb
Host smart-86e12ff2-c176-499a-963e-ac225e628d05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478425717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.3478425717
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2407211496
Short name T552
Test name
Test status
Simulation time 517989402 ps
CPU time 1.89 seconds
Started May 19 01:33:48 PM PDT 24
Finished May 19 01:33:51 PM PDT 24
Peak memory 201428 kb
Host smart-328461cb-24d1-4cdb-b74c-3da66eccd27f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407211496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2407211496
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3110138797
Short name T147
Test name
Test status
Simulation time 398634864178 ps
CPU time 288.4 seconds
Started May 19 01:33:39 PM PDT 24
Finished May 19 01:38:29 PM PDT 24
Peak memory 201912 kb
Host smart-170530ff-1457-46ef-bc2b-1860ec7d3c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110138797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3110138797
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1173114184
Short name T160
Test name
Test status
Simulation time 482018894031 ps
CPU time 573.77 seconds
Started May 19 01:33:34 PM PDT 24
Finished May 19 01:43:11 PM PDT 24
Peak memory 201940 kb
Host smart-a91a4a16-8aea-42b7-a1a2-6c7555628a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173114184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1173114184
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.435753192
Short name T533
Test name
Test status
Simulation time 494482515969 ps
CPU time 956.44 seconds
Started May 19 01:33:44 PM PDT 24
Finished May 19 01:49:42 PM PDT 24
Peak memory 201780 kb
Host smart-6183ea1e-baab-46c3-b6fc-36d8dfcc9765
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=435753192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt
_fixed.435753192
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3857895457
Short name T605
Test name
Test status
Simulation time 165266139726 ps
CPU time 50.28 seconds
Started May 19 01:33:54 PM PDT 24
Finished May 19 01:34:45 PM PDT 24
Peak memory 201756 kb
Host smart-623ef351-f608-4d76-8906-c4f047ecaa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857895457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3857895457
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2707618656
Short name T602
Test name
Test status
Simulation time 490257622078 ps
CPU time 1156.48 seconds
Started May 19 01:33:34 PM PDT 24
Finished May 19 01:52:53 PM PDT 24
Peak memory 201832 kb
Host smart-86b54160-2f62-418d-9666-de5eb4e14703
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707618656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2707618656
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1082224503
Short name T732
Test name
Test status
Simulation time 204956886631 ps
CPU time 121.77 seconds
Started May 19 01:33:53 PM PDT 24
Finished May 19 01:35:56 PM PDT 24
Peak memory 201808 kb
Host smart-0f667b1c-96e8-4be5-a47e-c9109d0cccd8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082224503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1082224503
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3386524652
Short name T47
Test name
Test status
Simulation time 73267618274 ps
CPU time 383.22 seconds
Started May 19 01:33:39 PM PDT 24
Finished May 19 01:40:03 PM PDT 24
Peak memory 202092 kb
Host smart-772274c6-956c-493b-b506-385315a6722d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386524652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3386524652
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.782069112
Short name T769
Test name
Test status
Simulation time 34811669530 ps
CPU time 22.98 seconds
Started May 19 01:33:38 PM PDT 24
Finished May 19 01:34:02 PM PDT 24
Peak memory 201592 kb
Host smart-cbbf335b-0020-4101-a37e-eef1cc9b290c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782069112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.782069112
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2349657291
Short name T615
Test name
Test status
Simulation time 3451570821 ps
CPU time 8.39 seconds
Started May 19 01:33:51 PM PDT 24
Finished May 19 01:34:01 PM PDT 24
Peak memory 201608 kb
Host smart-de4f4716-d416-4984-b2e1-11a9fe8b3bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349657291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2349657291
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.681995605
Short name T626
Test name
Test status
Simulation time 5698604010 ps
CPU time 14.99 seconds
Started May 19 01:33:38 PM PDT 24
Finished May 19 01:33:54 PM PDT 24
Peak memory 201596 kb
Host smart-294cce04-2b78-437e-af9e-818fc1b3bf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681995605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.681995605
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3729875587
Short name T339
Test name
Test status
Simulation time 391952642237 ps
CPU time 193.32 seconds
Started May 19 01:33:42 PM PDT 24
Finished May 19 01:36:57 PM PDT 24
Peak memory 201708 kb
Host smart-9db542b2-2103-4f02-8868-cc1a262e239f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729875587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3729875587
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.594262071
Short name T406
Test name
Test status
Simulation time 493038880 ps
CPU time 1.8 seconds
Started May 19 01:33:42 PM PDT 24
Finished May 19 01:33:45 PM PDT 24
Peak memory 201408 kb
Host smart-7687a730-539c-4d16-af97-8d6d3c24cdd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594262071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.594262071
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1581090369
Short name T736
Test name
Test status
Simulation time 371829140270 ps
CPU time 61.24 seconds
Started May 19 01:34:01 PM PDT 24
Finished May 19 01:35:04 PM PDT 24
Peak memory 201804 kb
Host smart-18f5d0a2-fd43-4f66-bbea-98299d05b1ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581090369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1581090369
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1357745143
Short name T539
Test name
Test status
Simulation time 333970369864 ps
CPU time 777.78 seconds
Started May 19 01:34:08 PM PDT 24
Finished May 19 01:47:08 PM PDT 24
Peak memory 201804 kb
Host smart-21c694ee-a925-481f-9257-7add37c54880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357745143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1357745143
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1638344198
Short name T92
Test name
Test status
Simulation time 499384939031 ps
CPU time 1122.53 seconds
Started May 19 01:33:42 PM PDT 24
Finished May 19 01:52:26 PM PDT 24
Peak memory 201724 kb
Host smart-00e6409d-8ebb-41b3-82e0-3549d5a99751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638344198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1638344198
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.4022192065
Short name T547
Test name
Test status
Simulation time 490062771884 ps
CPU time 1116.81 seconds
Started May 19 01:33:39 PM PDT 24
Finished May 19 01:52:17 PM PDT 24
Peak memory 201772 kb
Host smart-c38b7b47-77b3-48ad-96c9-fad704eccf7c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022192065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.4022192065
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2173700101
Short name T206
Test name
Test status
Simulation time 487170817657 ps
CPU time 126.58 seconds
Started May 19 01:33:56 PM PDT 24
Finished May 19 01:36:03 PM PDT 24
Peak memory 201788 kb
Host smart-7cef7ccb-408e-4101-827e-faab847c59cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173700101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2173700101
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.4095517378
Short name T704
Test name
Test status
Simulation time 493680474590 ps
CPU time 255.1 seconds
Started May 19 01:33:57 PM PDT 24
Finished May 19 01:38:13 PM PDT 24
Peak memory 201772 kb
Host smart-7f410c68-ade8-439b-b9c5-0bcd87d35c56
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095517378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.4095517378
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2696566913
Short name T745
Test name
Test status
Simulation time 566388373654 ps
CPU time 681.17 seconds
Started May 19 01:33:41 PM PDT 24
Finished May 19 01:45:04 PM PDT 24
Peak memory 201828 kb
Host smart-fa282e1f-94fb-4db7-a186-457a4faac2d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696566913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2696566913
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.241287044
Short name T218
Test name
Test status
Simulation time 204672120926 ps
CPU time 250.81 seconds
Started May 19 01:34:00 PM PDT 24
Finished May 19 01:38:11 PM PDT 24
Peak memory 201776 kb
Host smart-3ada1888-c2e3-4a2d-8748-d5c5026e8fa1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241287044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.241287044
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3556050911
Short name T621
Test name
Test status
Simulation time 70074824270 ps
CPU time 362.05 seconds
Started May 19 01:33:54 PM PDT 24
Finished May 19 01:39:57 PM PDT 24
Peak memory 202104 kb
Host smart-e554651a-2b75-4606-a308-f0408804a589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556050911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3556050911
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2401699320
Short name T392
Test name
Test status
Simulation time 40710460415 ps
CPU time 44.95 seconds
Started May 19 01:33:41 PM PDT 24
Finished May 19 01:34:27 PM PDT 24
Peak memory 201544 kb
Host smart-dc043e1b-3cf5-4b93-9475-0c4cb21a8ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401699320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2401699320
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1665181061
Short name T2
Test name
Test status
Simulation time 5006017509 ps
CPU time 13.27 seconds
Started May 19 01:33:59 PM PDT 24
Finished May 19 01:34:13 PM PDT 24
Peak memory 201632 kb
Host smart-d8d13840-9369-407d-86d6-49571e96eea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665181061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1665181061
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.22656149
Short name T500
Test name
Test status
Simulation time 6032379501 ps
CPU time 15.61 seconds
Started May 19 01:33:42 PM PDT 24
Finished May 19 01:33:59 PM PDT 24
Peak memory 201640 kb
Host smart-72c81239-cf91-4216-9fff-ab288e9c0351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22656149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.22656149
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.2618407913
Short name T796
Test name
Test status
Simulation time 28040977873 ps
CPU time 67.34 seconds
Started May 19 01:33:54 PM PDT 24
Finished May 19 01:35:03 PM PDT 24
Peak memory 201588 kb
Host smart-c289a443-bb75-462c-93c0-19e7e378ed23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618407913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
2618407913
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.8121256
Short name T58
Test name
Test status
Simulation time 30825982787 ps
CPU time 19.81 seconds
Started May 19 01:33:54 PM PDT 24
Finished May 19 01:34:15 PM PDT 24
Peak memory 201900 kb
Host smart-161bc4fb-8113-4b84-a42b-898aa8bcca09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8121256 -assert nopost
proc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.8121256
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3703654571
Short name T91
Test name
Test status
Simulation time 343752156 ps
CPU time 0.86 seconds
Started May 19 01:33:46 PM PDT 24
Finished May 19 01:33:47 PM PDT 24
Peak memory 201516 kb
Host smart-407435ee-bde3-4722-b77c-ab70fc2a4dd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703654571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3703654571
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.4108203389
Short name T262
Test name
Test status
Simulation time 325671909805 ps
CPU time 179.09 seconds
Started May 19 01:33:41 PM PDT 24
Finished May 19 01:36:41 PM PDT 24
Peak memory 201820 kb
Host smart-f17d2268-255f-42a7-a601-692597d4033b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108203389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.4108203389
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3927556401
Short name T329
Test name
Test status
Simulation time 505415432062 ps
CPU time 295.53 seconds
Started May 19 01:33:48 PM PDT 24
Finished May 19 01:38:44 PM PDT 24
Peak memory 201776 kb
Host smart-72371b49-2407-4f07-b889-83990686e3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927556401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3927556401
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2794256226
Short name T662
Test name
Test status
Simulation time 331436596269 ps
CPU time 204.29 seconds
Started May 19 01:33:53 PM PDT 24
Finished May 19 01:37:19 PM PDT 24
Peak memory 201816 kb
Host smart-443ec3b9-50e4-4984-8ea3-e419cf29d242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794256226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2794256226
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1454357504
Short name T550
Test name
Test status
Simulation time 495016911135 ps
CPU time 175.5 seconds
Started May 19 01:33:41 PM PDT 24
Finished May 19 01:36:38 PM PDT 24
Peak memory 201804 kb
Host smart-708cbeb8-5cfc-4fce-9bbb-3c9485f85a80
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454357504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1454357504
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2842998729
Short name T590
Test name
Test status
Simulation time 324185261751 ps
CPU time 189.55 seconds
Started May 19 01:34:01 PM PDT 24
Finished May 19 01:37:13 PM PDT 24
Peak memory 201864 kb
Host smart-6329381c-6f6b-4a3c-b8b1-c45bbf561d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842998729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2842998729
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.283337008
Short name T592
Test name
Test status
Simulation time 323091593553 ps
CPU time 193.09 seconds
Started May 19 01:33:51 PM PDT 24
Finished May 19 01:37:06 PM PDT 24
Peak memory 201768 kb
Host smart-4b676575-5b56-4e31-a25c-97839da47fa9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=283337008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.283337008
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3086750961
Short name T217
Test name
Test status
Simulation time 359851832937 ps
CPU time 192.8 seconds
Started May 19 01:33:50 PM PDT 24
Finished May 19 01:37:04 PM PDT 24
Peak memory 201816 kb
Host smart-19f6098b-f867-4fc8-8540-0111cabad7dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086750961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3086750961
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2150900015
Short name T410
Test name
Test status
Simulation time 205879616983 ps
CPU time 463.19 seconds
Started May 19 01:34:13 PM PDT 24
Finished May 19 01:41:58 PM PDT 24
Peak memory 201800 kb
Host smart-412a3f9e-2d1a-4593-ad20-661f2b6ac4cd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150900015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2150900015
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3804106675
Short name T595
Test name
Test status
Simulation time 138378119996 ps
CPU time 656.37 seconds
Started May 19 01:33:54 PM PDT 24
Finished May 19 01:44:52 PM PDT 24
Peak memory 202108 kb
Host smart-7bbfc1dd-7ae7-40a3-bc87-b46c84231b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804106675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3804106675
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3132539084
Short name T447
Test name
Test status
Simulation time 30359521400 ps
CPU time 72.44 seconds
Started May 19 01:33:52 PM PDT 24
Finished May 19 01:35:10 PM PDT 24
Peak memory 201660 kb
Host smart-d52bf2b0-8424-4e9c-bb25-cfee8d3779b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132539084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3132539084
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.818377746
Short name T95
Test name
Test status
Simulation time 2765621026 ps
CPU time 7.44 seconds
Started May 19 01:34:11 PM PDT 24
Finished May 19 01:34:19 PM PDT 24
Peak memory 201556 kb
Host smart-39dd6d3f-8c0f-4f7e-b511-0ec25d6048f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818377746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.818377746
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1297654833
Short name T167
Test name
Test status
Simulation time 5850730146 ps
CPU time 3.96 seconds
Started May 19 01:33:56 PM PDT 24
Finished May 19 01:34:01 PM PDT 24
Peak memory 201644 kb
Host smart-3c38bb72-ffd4-46d1-adaf-13217473d0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297654833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1297654833
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2898001244
Short name T658
Test name
Test status
Simulation time 234729523325 ps
CPU time 552.91 seconds
Started May 19 01:34:03 PM PDT 24
Finished May 19 01:43:18 PM PDT 24
Peak memory 201816 kb
Host smart-6868e9f2-24bc-4635-a7e1-757cd6622728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898001244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2898001244
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.4251124814
Short name T419
Test name
Test status
Simulation time 417866300 ps
CPU time 1.15 seconds
Started May 19 01:33:48 PM PDT 24
Finished May 19 01:33:50 PM PDT 24
Peak memory 201496 kb
Host smart-99a666bb-082f-4a8e-9cd2-c80f1301b6a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251124814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.4251124814
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2362929967
Short name T580
Test name
Test status
Simulation time 337023432478 ps
CPU time 696.29 seconds
Started May 19 01:33:53 PM PDT 24
Finished May 19 01:45:31 PM PDT 24
Peak memory 201848 kb
Host smart-554f79cf-882e-4bb0-adf3-8390ae3739ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362929967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2362929967
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1787390233
Short name T282
Test name
Test status
Simulation time 516927863769 ps
CPU time 656.91 seconds
Started May 19 01:34:02 PM PDT 24
Finished May 19 01:45:01 PM PDT 24
Peak memory 201832 kb
Host smart-6d737ebc-e786-463b-9152-682901f230d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787390233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1787390233
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1416014237
Short name T175
Test name
Test status
Simulation time 491617685951 ps
CPU time 149.73 seconds
Started May 19 01:33:48 PM PDT 24
Finished May 19 01:36:18 PM PDT 24
Peak memory 201812 kb
Host smart-e0bc9f1f-407c-4640-98f9-bc78607a7416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416014237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1416014237
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2469492156
Short name T163
Test name
Test status
Simulation time 167456427538 ps
CPU time 386.6 seconds
Started May 19 01:33:52 PM PDT 24
Finished May 19 01:40:21 PM PDT 24
Peak memory 201764 kb
Host smart-7b7abbe2-c11d-44df-a9bd-2ac6741fa3b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469492156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2469492156
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2577810118
Short name T182
Test name
Test status
Simulation time 499737188878 ps
CPU time 1102.84 seconds
Started May 19 01:33:56 PM PDT 24
Finished May 19 01:52:20 PM PDT 24
Peak memory 202104 kb
Host smart-b5b02387-f494-4f33-8f46-8e0d8733f365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577810118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2577810118
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.131594384
Short name T642
Test name
Test status
Simulation time 329848410086 ps
CPU time 687.18 seconds
Started May 19 01:33:51 PM PDT 24
Finished May 19 01:45:19 PM PDT 24
Peak memory 201824 kb
Host smart-8a5db2a9-15f4-444d-86bd-c0304653c620
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=131594384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.131594384
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.1694080014
Short name T667
Test name
Test status
Simulation time 174893634837 ps
CPU time 106.01 seconds
Started May 19 01:33:52 PM PDT 24
Finished May 19 01:35:39 PM PDT 24
Peak memory 201880 kb
Host smart-3e3deda0-e4fb-4b32-83e6-ffd32e82b917
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694080014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.1694080014
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.4146984597
Short name T613
Test name
Test status
Simulation time 209311121394 ps
CPU time 101.73 seconds
Started May 19 01:34:03 PM PDT 24
Finished May 19 01:35:47 PM PDT 24
Peak memory 201788 kb
Host smart-f9161ecb-292b-487d-8127-aa56f01aee76
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146984597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.4146984597
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1881345946
Short name T636
Test name
Test status
Simulation time 104168850308 ps
CPU time 409.37 seconds
Started May 19 01:33:49 PM PDT 24
Finished May 19 01:40:39 PM PDT 24
Peak memory 202180 kb
Host smart-e084dba6-6299-4870-90be-0b6c5889bf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881345946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1881345946
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3388262169
Short name T86
Test name
Test status
Simulation time 39259014527 ps
CPU time 8.3 seconds
Started May 19 01:33:43 PM PDT 24
Finished May 19 01:33:52 PM PDT 24
Peak memory 201864 kb
Host smart-503fdfcc-372c-4515-8496-2dc14f0355b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388262169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3388262169
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3765268968
Short name T647
Test name
Test status
Simulation time 2649351508 ps
CPU time 6.66 seconds
Started May 19 01:33:51 PM PDT 24
Finished May 19 01:33:58 PM PDT 24
Peak memory 201584 kb
Host smart-ca167972-35e6-4b8b-a38b-0dd5ee6d26db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765268968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3765268968
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3301999394
Short name T682
Test name
Test status
Simulation time 5950823339 ps
CPU time 10.24 seconds
Started May 19 01:33:43 PM PDT 24
Finished May 19 01:33:54 PM PDT 24
Peak memory 201624 kb
Host smart-1ec4b5e6-2a8f-426d-8559-88ea9908df45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301999394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3301999394
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1190430675
Short name T426
Test name
Test status
Simulation time 43313130224 ps
CPU time 98.16 seconds
Started May 19 01:33:51 PM PDT 24
Finished May 19 01:35:31 PM PDT 24
Peak memory 201604 kb
Host smart-40ebf5f7-f8f2-41c9-8977-082afacb1c6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190430675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1190430675
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.269080324
Short name T201
Test name
Test status
Simulation time 520340364 ps
CPU time 0.88 seconds
Started May 19 01:33:55 PM PDT 24
Finished May 19 01:33:57 PM PDT 24
Peak memory 201476 kb
Host smart-4fb68a40-80e3-47fc-b437-793d02af8a9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269080324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.269080324
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2816980230
Short name T296
Test name
Test status
Simulation time 508339746428 ps
CPU time 556.7 seconds
Started May 19 01:33:48 PM PDT 24
Finished May 19 01:43:06 PM PDT 24
Peak memory 201852 kb
Host smart-7a6a3cf7-75ad-49b3-814a-d587edc4ce0f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816980230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2816980230
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1330804936
Short name T353
Test name
Test status
Simulation time 166200543242 ps
CPU time 221.07 seconds
Started May 19 01:33:46 PM PDT 24
Finished May 19 01:37:28 PM PDT 24
Peak memory 201812 kb
Host smart-09b12b6e-da9e-42ff-ac92-075da157d9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330804936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1330804936
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.841743105
Short name T73
Test name
Test status
Simulation time 330534731158 ps
CPU time 392.94 seconds
Started May 19 01:33:47 PM PDT 24
Finished May 19 01:40:21 PM PDT 24
Peak memory 201796 kb
Host smart-83baaaa2-d347-4df7-86e1-8fb0274a3427
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=841743105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.841743105
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1002104803
Short name T681
Test name
Test status
Simulation time 332905719861 ps
CPU time 394.71 seconds
Started May 19 01:33:51 PM PDT 24
Finished May 19 01:40:27 PM PDT 24
Peak memory 201816 kb
Host smart-933ac76b-9ae1-4dcd-8518-5078e22eea1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002104803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1002104803
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2689704186
Short name T489
Test name
Test status
Simulation time 487768141146 ps
CPU time 279.63 seconds
Started May 19 01:33:57 PM PDT 24
Finished May 19 01:38:38 PM PDT 24
Peak memory 201796 kb
Host smart-5ef7e32b-3ae1-4b16-88eb-7deeecdc5d2f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689704186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2689704186
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1276407596
Short name T402
Test name
Test status
Simulation time 595699361098 ps
CPU time 735.26 seconds
Started May 19 01:33:41 PM PDT 24
Finished May 19 01:45:57 PM PDT 24
Peak memory 201976 kb
Host smart-04d4d9a3-2e5e-4e00-8e41-70cd70de0fda
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276407596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1276407596
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.635587128
Short name T659
Test name
Test status
Simulation time 32475074923 ps
CPU time 72.83 seconds
Started May 19 01:34:01 PM PDT 24
Finished May 19 01:35:15 PM PDT 24
Peak memory 201616 kb
Host smart-312a1fb0-49c1-4fcb-b16c-a22c5d120b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635587128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.635587128
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3091153039
Short name T698
Test name
Test status
Simulation time 5221375003 ps
CPU time 13.31 seconds
Started May 19 01:33:57 PM PDT 24
Finished May 19 01:34:11 PM PDT 24
Peak memory 201628 kb
Host smart-9bdb59de-434b-4534-9b1f-7d7ab7013188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091153039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3091153039
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3781159896
Short name T717
Test name
Test status
Simulation time 5866981659 ps
CPU time 13.51 seconds
Started May 19 01:34:03 PM PDT 24
Finished May 19 01:34:18 PM PDT 24
Peak memory 201656 kb
Host smart-f90e45d1-102c-4871-8cc1-b0e88f5a9c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781159896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3781159896
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2909465848
Short name T345
Test name
Test status
Simulation time 327345675450 ps
CPU time 393.16 seconds
Started May 19 01:33:46 PM PDT 24
Finished May 19 01:40:20 PM PDT 24
Peak memory 201820 kb
Host smart-516ed4e9-ecfb-4ea5-98cd-66b75cfc37b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909465848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2909465848
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3871430636
Short name T275
Test name
Test status
Simulation time 309434956852 ps
CPU time 189.39 seconds
Started May 19 01:33:43 PM PDT 24
Finished May 19 01:36:53 PM PDT 24
Peak memory 210432 kb
Host smart-0bdb3bf5-6e87-4b37-af95-f5b08605396e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871430636 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3871430636
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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