Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7110	1			T2	86		T6	42		T7	20
testmodes[AdcCtrlTestmodeNormal]	5492	1			T1	2		T2	5		T3	3
testmodes[AdcCtrlTestmodeLowpower]	5842	1			T2	13		T5	1		T6	36
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3874	1			T2	81		T6	19		T7	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1755	1			T2	3		T6	10		T9	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1384	1			T2	1		T6	12		T14	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1749	1			T2	3		T6	16		T9	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1978	1			T1	1		T2	2		T3	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1411	1			T6	9		T12	1		T61	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1377	1			T2	2		T6	7		T44	25
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1421	1			T6	15		T14	1		T36	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2797	1			T2	11		T6	14		T10	1