Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26640

1

T1

2

T2

108

T3

21

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22870

1

T1

1

T2

104

T3

4

auto[ADC_CTRL_FILTER_COND_OUT]

3770

1

T1

1

T2

4

T3

17

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20460

1

T1

2

T2

108

T3

17

auto[1]

6180

1

T3

4

T5

13

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22640

1

T1

2

T2

105

T3

3

auto[1]

4000

1

T2

3

T3

18

T12

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	403	1			T6	1		T44	1		T45	1
values[0]	50	1			T147	1		T103	1		T227	1
values[1]	720	1			T1	1		T61	37		T152	1
values[2]	2722	1			T5	13		T10	32		T11	44
values[3]	838	1			T13	5		T36	4		T47	1
values[4]	730	1			T12	2		T13	17		T14	27
values[5]	595	1			T3	1		T15	9		T42	1
values[6]	668	1			T12	28		T36	11		T47	4
values[7]	644	1			T1	1		T3	3		T43	1
values[8]	934	1			T2	4		T3	17		T13	10
values[9]	1245	1			T62	16		T42	2		T47	8
minimum	17091	1			T2	104		T6	113		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	813	1			T1	1		T61	37		T152	2
values[1]	2894	1			T5	13		T10	32		T11	44
values[2]	779	1			T12	2		T13	22		T152	1
values[3]	728	1			T14	27		T15	9		T62	12
values[4]	565	1			T3	1		T36	11		T42	1
values[5]	635	1			T3	3		T12	28		T47	4
values[6]	812	1			T1	1		T13	10		T43	1
values[7]	803	1			T2	4		T3	17		T61	24
values[8]	836	1			T42	2		T47	8		T117	5
values[9]	253	1			T62	16		T150	5		T143	25
minimum	17522	1			T2	104		T6	114		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

4196

1

T2

1

T5

12

T10

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	1		T61	6		T152	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T61	14		T152	1		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1455	1			T5	13		T10	32		T11	44
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T43	1		T47	1		T73	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T13	22		T38	1		T146	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	1		T152	1		T36	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T62	12		T144	1		T148	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T14	16		T15	1		T143	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	1		T228	8		T54	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T36	1		T42	1		T143	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T3	1		T47	4		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T12	14		T144	1		T37	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T13	10		T43	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	1		T73	1		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T51	18		T229	4		T38	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	3		T3	1		T61	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T47	8		T99	1		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T42	2		T117	2		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T143	13		T230	11		T231	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T62	16		T150	1		T155	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T2	102		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T162	4		T232	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T61	6		T145	11		T179	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T61	11		T144	12		T116	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	922	1			T153	8		T49	6		T37	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T73	7		T117	12		T233	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T38	9		T161	2		T110	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	1		T108	2		T102	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T144	12		T234	8		T32	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	11		T15	8		T173	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T54	2		T59	1		T60	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T36	10		T143	17		T117	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T3	2		T149	6		T54	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	14		T144	12		T37	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T235	5		T234	7		T197	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T73	1		T236	7		T237	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T51	15		T229	4		T38	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	1		T3	16		T61	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T238	5		T57	1		T239	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T117	3		T55	4		T235	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T143	12		T231	11		T240	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T150	4		T155	15		T241	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	2		T37	3		T51	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T162	3		T232	10		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	403	1			T6	1		T44	1		T45	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T147	1		T242	16		T187	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T103	1		T227	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	1		T61	6		T188	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T61	14		T152	1		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1435	1			T5	13		T10	32		T11	44
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T43	1		T73	7		T233	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T13	5		T38	1		T161	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T36	4		T47	1		T117	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T13	17		T62	12		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T12	1		T14	16		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	1		T228	8		T54	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T15	1		T42	1		T143	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T47	4		T149	1		T116	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	14		T36	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	1		T43	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	1		T120	10		T179	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T13	10		T51	18		T38	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T2	3		T3	1		T61	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	440	1			T47	8		T143	13		T229	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T62	16		T42	2		T150	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16960	1			T2	102		T6	113		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T242	13		T243	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T61	6		T145	11		T179	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T61	11		T144	12		T116	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	934	1			T153	8		T49	6		T37	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T73	7		T233	4		T208	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T38	9		T161	2		T110	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T117	12		T108	2		T102	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T144	12		T234	8		T244	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	1		T14	11		T173	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T54	2		T59	1		T60	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T15	8		T143	17		T117	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T149	6		T109	8		T245	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	14		T36	10		T144	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	2		T54	2		T235	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T156	10		T237	14		T241	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T51	15		T38	16		T246	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	1		T3	16		T61	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T143	12		T229	4		T208	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T150	4		T117	3		T235	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	2		T37	3		T51	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T1	1		T61	7		T152	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T61	12		T152	1		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T5	1		T10	2		T11	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T43	1		T47	1		T73	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	2		T38	10		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	2		T152	1		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T62	1		T144	13		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T14	13		T15	9		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T3	1		T228	1		T54	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T36	11		T42	1		T143	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T3	3		T47	1		T149	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	15		T144	13		T37	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T13	1		T43	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	1		T73	2		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T51	23		T229	5		T38	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	3		T3	17		T61	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T47	1		T99	1		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T42	2		T117	4		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T143	13		T230	1		T231	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T62	1		T150	5		T155	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17494	1			T2	104		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T162	4		T232	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T61	5		T188	19		T145	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T61	13		T145	11		T174	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1142	1			T5	12		T10	30		T11	41
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T73	6		T117	14		T233	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	20		T146	4		T161	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T36	3		T108	20		T39	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T62	11		T148	12		T234	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	14		T143	7		T188	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T228	7		T54	4		T59	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T143	12		T117	12		T58	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T47	3		T109	8		T245	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	13		T37	13		T120	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	9		T235	9		T234	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T154	3		T237	15		T241	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T51	10		T229	3		T38	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	1		T61	12		T38	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T47	7		T245	11		T247	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T117	1		T55	4		T237	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T143	12		T230	10		T231	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T62	15		T155	13		T241	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T162	3		T232	10		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	403	1			T6	1		T44	1		T45	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T147	1		T242	14		T187	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T103	1		T227	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	1		T61	7		T188	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T61	12		T152	1		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T5	1		T10	2		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T43	1		T73	8		T233	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	1		T38	10		T161	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T36	1		T47	1		T117	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	1		T62	1		T144	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	2		T14	13		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T3	1		T228	1		T54	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T15	9		T42	1		T143	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T47	1		T149	7		T116	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T12	15		T36	11		T144	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	3		T43	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	1		T120	1		T179	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	1		T51	23		T38	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T2	3		T3	17		T61	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	396	1			T47	1		T143	13		T229	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T62	1		T42	2		T150	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17091	1			T2	104		T6	113		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T242	15		T243	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T61	5		T188	19		T145	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T61	13		T145	11		T162	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1118	1			T5	12		T10	30		T11	41
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T73	6		T233	4		T148	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T13	4		T161	13		T110	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T36	3		T117	14		T108	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	16		T62	11		T146	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	14		T188	11		T173	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T228	7		T54	4		T59	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T143	19		T117	12		T58	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T47	3		T109	8		T245	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	13		T37	13		T148	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T235	9		T197	14		T248	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T120	9		T179	4		T154	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	9		T51	10		T38	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T2	1		T61	12		T38	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T47	7		T143	12		T229	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T62	15		T117	1		T155	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

auto[0]

4196

1

T2

1

T5

12

T10

30

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26640

1

T1

2

T2

108

T3

21

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20811

1

T1

2

T2

108

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

5829

1

T3

18

T5

13

T10

32

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20520

1

T1

1

T2

108

T6

114

auto[1]

6120

1

T1

1

T3

21

T5

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22640

1

T1

2

T2

105

T3

3

auto[1]

4000

1

T2

3

T3

18

T12

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	312	1			T14	25		T61	25		T188	20
values[0]	1	1			T249	1		-	-		-	-
values[1]	726	1			T13	10		T43	1		T47	1
values[2]	742	1			T12	2		T13	17		T15	9
values[3]	700	1			T36	11		T42	1		T47	8
values[4]	510	1			T152	1		T42	1		T144	13
values[5]	879	1			T3	17		T42	1		T43	2
values[6]	717	1			T3	3		T61	24		T116	2
values[7]	764	1			T61	12		T152	1		T36	4
values[8]	790	1			T1	1		T12	28		T13	5
values[9]	3005	1			T1	1		T2	4		T3	1
minimum	17494	1			T2	104		T6	114		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	688	1			T13	10		T43	1		T47	1
values[1]	2872	1			T5	13		T10	32		T11	44
values[2]	644	1			T36	11		T47	8		T143	30
values[3]	670	1			T3	17		T152	1		T42	1
values[4]	908	1			T3	3		T42	1		T43	2
values[5]	607	1			T61	36		T116	2		T117	22
values[6]	888	1			T152	1		T36	4		T73	16
values[7]	688	1			T1	1		T2	4		T12	28
values[8]	695	1			T1	1		T3	1		T14	2
values[9]	252	1			T14	25		T147	1		T108	23
minimum	17728	1			T2	104		T6	114		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

4196

1

T2

1

T5

12

T10

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	10		T43	1		T47	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T51	18		T38	1		T233	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T13	17		T15	1		T42	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1539	1			T5	13		T10	32		T11	44
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T36	1		T143	13		T145	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T47	8		T116	1		T38	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T152	1		T144	1		T37	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	1		T42	1		T233	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T3	1		T42	1		T43	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T37	1		T117	15		T146	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T61	6		T38	15		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T61	13		T116	1		T117	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T152	1		T36	4		T73	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T150	1		T143	8		T161	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	1		T2	3		T12	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	5		T152	1		T229	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	1		T14	2		T62	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	1		T61	14		T188	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T147	1		T196	1		T250	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T14	14		T108	21		T99	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17423	1			T2	102		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T188	12		T155	14		T39	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T144	12		T145	8		T154	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T51	15		T38	9		T55	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T15	8		T149	6		T37	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1002	1			T12	1		T153	8		T49	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T36	10		T143	17		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T38	10		T109	8		T232	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T144	12		T37	14		T179	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	16		T233	4		T107	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	2		T144	12		T234	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T37	4		T117	12		T56	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T61	6		T38	16		T54	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T61	11		T116	1		T117	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T73	8		T246	5		T54	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T150	4		T161	2		T235	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T2	1		T12	14		T57	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T229	4		T208	7		T235	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T143	12		T117	3		T162	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T61	11		T208	5		T238	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T196	9		T251	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T14	11		T108	2		T252	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	2		T37	3		T51	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T155	15		T39	3		T204	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T147	1		T246	1		T55	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T14	14		T61	14		T188	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T249	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	10		T43	1		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T51	18		T188	12		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T13	17		T15	1		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	1		T47	4		T228	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T36	1		T42	1		T143	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T47	8		T116	1		T38	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T152	1		T144	1		T37	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T42	1		T233	5		T107	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T42	1		T43	2		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T3	1		T37	1		T117	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	1		T38	15		T234	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T61	13		T116	1		T146	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T61	6		T152	1		T36	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T150	1		T143	8		T117	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T1	1		T12	14		T62	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	5		T152	1		T229	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	1		T2	3		T14	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1576	1			T3	1		T5	13		T10	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T2	102		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T246	4		T107	15		T239	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T14	11		T61	11		T208	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T144	12		T145	8		T53	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T51	15		T38	9		T55	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	8		T149	6		T37	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	1		T97	11		T102	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T36	10		T143	17		T145	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T38	10		T109	8		T232	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T144	12		T37	14		T179	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T233	4		T107	15		T238	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T144	12		T246	8		T234	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	16		T37	4		T117	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	2		T38	16		T234	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T61	11		T116	1		T173	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T61	6		T73	1		T246	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T150	4		T117	9		T253	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	14		T73	7		T237	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T229	4		T208	7		T161	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T2	1		T143	12		T117	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1063	1			T153	8		T49	6		T254	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	2		T37	3		T51	1