Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26640

1

T1

2

T2

108

T3

21

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23343

1

T1

1

T2

108

T3

4

auto[ADC_CTRL_FILTER_COND_OUT]

3297

1

T1

1

T3

17

T12

30

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20836

1

T1

1

T2

104

T3

3

auto[1]

5804

1

T1

1

T2

4

T3

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22640

1

T1

2

T2

105

T3

3

auto[1]

4000

1

T2

3

T3

18

T12

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	22	1			T145	21		T315	1		-	-
values[0]	113	1			T160	1		T190	1		T256	28
values[1]	572	1			T12	28		T152	1		T43	1
values[2]	631	1			T3	1		T13	5		T15	9
values[3]	530	1			T1	1		T42	1		T117	27
values[4]	2710	1			T5	13		T10	32		T11	44
values[5]	918	1			T1	1		T3	3		T14	25
values[6]	893	1			T61	37		T62	16		T43	1
values[7]	665	1			T42	1		T47	4		T117	5
values[8]	887	1			T12	2		T13	10		T62	12
values[9]	1205	1			T2	4		T3	17		T14	2
minimum	17494	1			T2	104		T6	114		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	747	1			T3	1		T12	28		T152	1
values[1]	598	1			T1	1		T13	5		T61	24
values[2]	615	1			T15	9		T42	1		T43	1
values[3]	2889	1			T3	3		T5	13		T10	32
values[4]	769	1			T1	1		T13	17		T61	37
values[5]	902	1			T62	16		T43	1		T143	55
values[6]	686	1			T62	12		T42	1		T47	4
values[7]	759	1			T3	17		T12	2		T13	10
values[8]	811	1			T2	4		T73	2		T143	8
values[9]	335	1			T14	2		T36	11		T232	21
minimum	17529	1			T2	104		T6	114		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

4196

1

T2

1

T5

12

T10

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	1		T47	8		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	14		T152	1		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	5		T162	4		T156	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	1		T61	13		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T43	1		T146	13		T161	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T15	1		T42	1		T116	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1566	1			T3	1		T5	13		T10	32
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T37	14		T233	5		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T1	1		T61	20		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T13	17		T152	1		T36	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T143	26		T37	1		T120	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T62	16		T43	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T42	1		T47	4		T53	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T62	12		T54	1		T235	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T152	1		T73	7		T51	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T3	1		T12	1		T13	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T2	3		T143	8		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T73	1		T145	10		T179	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T14	2		T36	1		T232	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T203	13		T60	1		T295	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17373	1			T2	102		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T290	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T149	6		T150	4		T110	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	14		T38	9		T52	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T162	3		T156	10		T56	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T61	11		T144	12		T117	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T161	2		T236	7		T237	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T15	8		T38	26		T238	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1042	1			T3	2		T14	11		T153	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T37	14		T233	4		T107	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T61	17		T144	12		T253	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T54	4		T155	15		T97	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T143	29		T37	6		T54	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T173	1		T234	7		T155	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T53	1		T174	12		T107	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T54	2		T235	9		T236	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T73	7		T51	15		T117	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	16		T12	1		T108	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	1		T37	4		T116	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T73	1		T145	11		T173	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T36	10		T232	10		T156	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T295	3		T192	14		T261	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T2	2		T37	3		T51	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T315	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T145	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T316	14		T317	10		T23	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T160	1		T190	1		T256	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T47	8		T150	1		T179	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	14		T152	1		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	1		T13	5		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T15	1		T61	13		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T117	15		T156	9		T56	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T1	1		T42	1		T38	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1482	1			T5	13		T10	32		T11	44
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	17		T116	1		T38	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T1	1		T3	1		T14	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T152	1		T36	4		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T61	20		T143	26		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T62	16		T43	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T42	1		T47	4		T117	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T234	9		T155	13		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T152	1		T51	18		T208	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	1		T13	10		T62	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T2	3		T14	2		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T3	1		T42	1		T188	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T2	102		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T145	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T316	9		T317	9		T23	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T256	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T150	4		T179	11		T110	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	14		T38	9		T52	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T149	6		T162	3		T167	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	8		T61	11		T144	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T117	12		T156	10		T56	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T38	16		T246	4		T238	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	957	1			T153	8		T49	6		T254	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T38	10		T233	4		T107	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	2		T14	11		T144	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T37	14		T155	15		T39	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T61	17		T143	29		T37	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T173	1		T54	4		T97	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T117	3		T53	1		T54	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T234	7		T155	13		T236	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T51	15		T208	5		T246	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	1		T73	1		T173	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T2	1		T36	10		T73	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	16		T154	2		T55	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	2		T37	3		T51	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	1		T47	1		T149	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T12	15		T152	1		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	1		T162	4		T156	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	1		T61	12		T144	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T43	1		T146	1		T161	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T15	9		T42	1		T116	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T3	3		T5	1		T10	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T37	15		T233	5		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	1		T61	19		T144	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	1		T152	1		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T143	31		T37	7		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T62	1		T43	1		T173	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T42	1		T47	1		T53	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T62	1		T54	3		T235	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T152	1		T73	8		T51	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	17		T12	2		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T2	3		T143	1		T37	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T73	2		T145	12		T179	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T14	1		T36	11		T232	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T203	1		T60	1		T295	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17506	1			T2	104		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T290	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T47	7		T108	12		T110	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	13		T52	3		T154	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	4		T162	3		T156	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T61	12		T117	12		T104	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T146	12		T161	13		T237	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T38	25		T276	7		T257	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T5	12		T10	30		T11	41
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T37	13		T233	4		T107	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T61	18		T228	7		T148	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	16		T36	3		T155	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T143	24		T120	9		T146	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T62	15		T234	8		T155	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T47	3		T174	5		T107	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T62	11		T245	3		T318	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T73	6		T51	10		T117	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	9		T188	19		T108	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	1		T143	7		T228	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T145	9		T179	4		T173	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T14	1		T232	10		T252	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T203	12		T295	4		T257	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T179	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T290	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T315	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T145	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T316	10		T317	10		T23	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T160	1		T190	1		T256	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T47	1		T150	5		T179	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	15		T152	1		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	1		T13	1		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T15	9		T61	12		T144	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T117	13		T156	11		T56	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	1		T42	1		T38	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T5	1		T10	2		T11	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	1		T116	1		T38	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T1	1		T3	3		T14	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T152	1		T36	1		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T61	19		T143	31		T37	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T62	1		T43	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T42	1		T47	1		T117	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T234	8		T155	14		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T152	1		T51	23		T208	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T12	2		T13	1		T62	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	431	1			T2	3		T14	1		T36	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T3	17		T42	1		T188	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17494	1			T2	104		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T145	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T316	13		T317	9		T23	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T256	15		T290	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T47	7		T179	9		T108	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	13		T52	3		T154	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T13	4		T162	3		T248	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T61	12		T117	12		T104	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T117	14		T156	8		T203	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T38	14		T257	5		T319	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1166	1			T5	12		T10	30		T11	41
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	16		T38	11		T233	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T14	13		T229	3		T145	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T36	3		T37	13		T155	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T61	18		T143	24		T120	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T62	15		T260	14		T230	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T47	3		T117	1		T54	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T234	8		T155	12		T245	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T51	10		T208	7		T109	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	9		T62	11		T173	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T2	1		T14	1		T73	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T188	19		T179	4		T154	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

auto[0]

4196

1

T2

1

T5

12

T10

30