Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26640

1

T1

2

T2

108

T3

21

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23024

1

T2

104

T3

1

T5

13

auto[ADC_CTRL_FILTER_COND_OUT]

3616

1

T1

2

T2

4

T3

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20758

1

T1

1

T2

104

T3

1

auto[1]

5882

1

T1

1

T2

4

T3

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22640

1

T1

2

T2

105

T3

3

auto[1]

4000

1

T2

3

T3

18

T12

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	174	1			T73	2		T253	17		T99	1
values[0]	34	1			T181	18		T273	16		-	-
values[1]	743	1			T13	22		T152	1		T42	1
values[2]	564	1			T3	3		T42	1		T144	13
values[3]	656	1			T12	2		T61	25		T152	1
values[4]	690	1			T12	28		T15	9		T62	12
values[5]	2928	1			T5	13		T10	32		T11	44
values[6]	802	1			T3	17		T13	10		T14	25
values[7]	718	1			T2	4		T61	12		T43	1
values[8]	839	1			T1	1		T36	11		T73	14
values[9]	998	1			T1	1		T3	1		T14	2
minimum	17494	1			T2	104		T6	114		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	723	1			T13	22		T42	1		T149	7
values[1]	560	1			T3	3		T12	2		T42	1
values[2]	703	1			T15	9		T61	25		T152	1
values[3]	2778	1			T5	13		T10	32		T11	44
values[4]	931	1			T13	10		T14	25		T62	16
values[5]	764	1			T3	17		T61	24		T43	1
values[6]	712	1			T2	4		T61	12		T117	5
values[7]	825	1			T1	1		T36	11		T73	14
values[8]	780	1			T1	1		T3	1		T14	2
values[9]	188	1			T228	8		T173	20		T108	23
minimum	17676	1			T2	104		T6	114		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

4196

1

T2

1

T5

12

T10

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T13	5		T149	1		T116	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	17		T42	1		T188	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	1		T42	1		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T3	1		T160	2		T235	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T152	1		T229	4		T53	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T15	1		T61	14		T143	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1522	1			T5	13		T10	32		T11	44
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	14		T62	12		T36	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T116	1		T117	13		T154	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T13	10		T14	14		T62	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T43	1		T47	12		T37	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T3	1		T61	13		T188	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T117	2		T52	6		T179	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	3		T61	6		T145	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T144	1		T155	13		T97	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	1		T36	1		T73	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	1		T73	1		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	1		T14	2		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T104	3		T105	11		T288	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T228	8		T173	9		T108	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17414	1			T2	102		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T143	13		T246	1		T250	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T149	6		T116	1		T38	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T58	1		T222	15		T211	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T12	1		T144	12		T161	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T3	2		T235	9		T97	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T229	4		T53	1		T109	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T15	8		T61	11		T143	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	944	1			T153	8		T49	6		T254	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T12	14		T37	14		T237	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T117	9		T174	12		T156	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T14	11		T54	2		T155	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T37	10		T233	4		T246	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	16		T61	11		T38	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T117	3		T52	1		T179	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	1		T61	6		T145	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T144	12		T155	13		T97	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T36	10		T73	7		T150	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T73	1		T144	12		T51	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T117	12		T38	10		T253	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T105	6		T288	9		T279	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T173	11		T108	2		T235	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	2		T37	3		T51	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T143	12		T246	5		T320	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T73	1		T104	3		T105	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T253	9		T99	1		T236	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T181	18		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T273	16		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T13	5		T152	1		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	17		T42	1		T143	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T42	1		T144	1		T146	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T3	1		T160	2		T235	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	1		T152	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T61	14		T143	13		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T152	1		T43	1		T229	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	14		T15	1		T62	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1503	1			T5	13		T10	32		T11	44
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T62	16		T47	1		T120	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T47	12		T37	2		T116	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T3	1		T13	10		T14	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T43	1		T117	2		T52	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	3		T61	6		T146	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T234	19		T97	1		T239	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	1		T36	1		T73	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T3	1		T144	2		T143	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T1	1		T14	2		T42	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T2	102		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T73	1		T105	6		T180	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T253	8		T236	11		T60	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T149	6		T116	1		T38	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T143	12		T246	5		T58	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T144	12		T161	2		T162	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T3	2		T235	9		T97	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T12	1		T53	1		T109	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T61	11		T143	17		T173	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T229	4		T208	5		T256	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	14		T15	8		T37	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T153	8		T49	6		T117	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T232	10		T241	15		T276	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T37	10		T233	4		T174	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T3	16		T14	11		T61	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T117	3		T52	1		T179	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	1		T61	6		T208	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T234	19		T97	11		T239	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T36	10		T73	7		T150	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T144	24		T51	15		T154	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T117	12		T38	10		T173	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	2		T37	3		T51	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	1		T149	7		T116	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	1		T42	1		T188	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	2		T42	1		T144	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	3		T160	2		T235	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T152	1		T229	5		T53	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T15	9		T61	12		T143	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T5	1		T10	2		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	15		T62	1		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T116	1		T117	10		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T13	1		T14	12		T62	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T43	1		T47	2		T37	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T3	17		T61	12		T188	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T117	4		T52	4		T179	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T2	3		T61	7		T145	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T144	13		T155	14		T97	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	1		T36	11		T73	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T3	1		T73	2		T144	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T1	1		T14	1		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T104	1		T105	13		T288	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T228	1		T173	12		T108	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17548	1			T2	104		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T143	13		T246	6		T250	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	4		T245	11		T262	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	16		T188	11		T58	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T146	4		T148	10		T161	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T203	12		T204	2		T321	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T229	3		T109	8		T278	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T61	13		T143	12		T191	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1198	1			T5	12		T10	30		T11	41
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	13		T62	11		T36	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T117	12		T154	3		T174	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T13	9		T14	13		T62	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T47	10		T233	4		T148	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T61	12		T188	19		T38	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T117	1		T52	3		T179	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	1		T61	5		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T155	12		T237	15		T241	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T73	6		T145	9		T252	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T143	7		T51	10		T148	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	1		T117	14		T38	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T104	2		T105	4		T279	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T228	7		T173	8		T108	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T55	4		T59	2		T322	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T143	12		T250	8		T320	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T73	2		T104	1		T105	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T253	9		T99	1		T236	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T181	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T273	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T13	1		T152	1		T149	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	1		T42	1		T143	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T42	1		T144	13		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T3	3		T160	2		T235	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	2		T152	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T61	12		T143	18		T173	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T152	1		T43	1		T229	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	15		T15	9		T62	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T5	1		T10	2		T11	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T62	1		T47	1		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T47	2		T37	12		T116	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T3	17		T13	1		T14	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T43	1		T117	4		T52	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	3		T61	7		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T234	21		T97	12		T239	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T1	1		T36	11		T73	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T3	1		T144	26		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T1	1		T14	1		T42	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17494	1			T2	104		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T104	2		T105	4		T169	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T253	8		T269	4		T323	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T181	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T273	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	4		T55	4		T59	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	16		T143	12		T188	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T146	4		T148	10		T161	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T203	12		T250	11		T312	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T109	8		T278	17		T260	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T61	13		T143	12		T259	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T229	3		T208	7		T248	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	13		T62	11		T36	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1179	1			T5	12		T10	30		T11	41
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T62	15		T120	9		T232	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T47	10		T233	4		T148	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	9		T14	13		T61	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T117	1		T52	3		T179	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T2	1		T61	5		T146	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T234	17		T241	12		T277	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T73	6		T145	20		T252	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T143	7		T51	10		T148	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	1		T117	14		T38	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

auto[0]

4196

1

T2

1

T5

12

T10

30