Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26640

1

T1

2

T2

108

T3

21

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23014

1

T2

104

T3

17

T5

13

auto[ADC_CTRL_FILTER_COND_OUT]

3626

1

T1

2

T2

4

T3

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20819

1

T1

1

T2

104

T3

1

auto[1]

5821

1

T1

1

T2

4

T3

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22640

1

T1

2

T2

105

T3

3

auto[1]

4000

1

T2

3

T3

18

T12

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	369	1			T3	21		T152	1		T47	8
values[0]	9	1			T160	1		T309	7		T34	1
values[1]	636	1			T42	1		T117	5		T188	12
values[2]	536	1			T12	2		T43	1		T144	13
values[3]	694	1			T1	1		T2	4		T14	2
values[4]	612	1			T152	1		T36	11		T43	1
values[5]	795	1			T37	7		T116	1		T117	27
values[6]	609	1			T13	10		T152	1		T36	4
values[7]	765	1			T13	5		T61	37		T47	1
values[8]	770	1			T13	17		T62	28		T144	26
values[9]	3351	1			T1	1		T5	13		T10	32
minimum	17494	1			T2	104		T6	114		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	590	1			T12	2		T188	12		T148	3
values[1]	552	1			T1	1		T42	1		T43	1
values[2]	741	1			T2	4		T14	2		T36	11
values[3]	655	1			T152	1		T43	1		T51	33
values[4]	744	1			T42	1		T37	7		T117	27
values[5]	646	1			T13	10		T61	37		T152	1
values[6]	3015	1			T5	13		T10	32		T11	44
values[7]	730	1			T61	24		T62	12		T144	13
values[8]	1170	1			T1	1		T12	28		T14	25
values[9]	149	1			T3	21		T53	3		T58	6
minimum	17648	1			T2	104		T6	114		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

4196

1

T2

1

T5

12

T10

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	1		T246	1		T54	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T188	12		T148	3		T271	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T42	1		T43	1		T146	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	1		T144	1		T173	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	2		T36	1		T73	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T2	3		T117	13		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T152	1		T116	1		T120	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T43	1		T51	18		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T37	1		T108	13		T234	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T42	1		T117	15		T233	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	10		T61	6		T36	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T61	14		T152	1		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1553	1			T5	13		T10	32		T11	44
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T13	17		T62	16		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T62	12		T144	1		T143	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T61	13		T233	1		T232	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T14	14		T15	1		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T1	1		T12	14		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T3	1		T53	2		T58	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T3	2		T311	20		T324	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17418	1			T2	102		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T38	13		T246	1		T21	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	1		T246	4		T56	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T155	15		T237	8		T247	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T162	3		T107	15		T236	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T144	12		T173	11		T55	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T36	10		T73	7		T229	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	1		T117	9		T38	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T234	8		T156	10		T97	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T51	15		T196	9		T169	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T37	6		T234	7		T241	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T117	12		T233	4		T179	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T61	6		T38	16		T54	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T61	11		T149	6		T191	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1067	1			T153	8		T49	6		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T144	12		T37	4		T161	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T144	12		T116	1		T208	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T61	11		T232	10		T238	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T14	11		T15	8		T73	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T12	14		T150	4		T143	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T3	16		T53	1		T58	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T3	2		T311	16		T324	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	2		T37	3		T51	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T38	19		T246	5		T21	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T3	1		T145	12		T208	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T3	2		T152	1		T47	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T160	1		T309	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T34	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T42	1		T117	2		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T188	12		T38	13		T148	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T12	1		T43	1		T146	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T144	1		T173	9		T55	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	2		T73	7		T154	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	1		T2	3		T117	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T152	1		T36	1		T120	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T43	1		T51	18		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T37	1		T116	1		T108	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T117	15		T147	1		T235	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	10		T36	4		T38	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T152	1		T42	1		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	5		T61	6		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T61	14		T146	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T62	12		T144	1		T143	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	17		T62	16		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1583	1			T5	13		T10	32		T11	44
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	408	1			T1	1		T12	14		T61	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T2	102		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	16		T145	8		T208	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T3	2		T109	8		T197	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T309	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T117	3		T246	4		T235	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T38	19		T246	5		T237	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T12	1		T162	3		T325	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T144	12		T173	11		T55	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T73	7		T107	15		T110	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T2	1		T117	9		T38	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T36	10		T229	4		T54	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T51	15		T196	9		T241	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T37	6		T97	2		T276	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T117	12		T235	8		T253	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T38	16		T234	7		T196	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T149	6		T233	4		T179	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T61	6		T143	12		T174	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T61	11		T156	10		T245	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T144	12		T116	1		T246	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T144	12		T37	4		T161	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1061	1			T14	11		T15	8		T153	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T12	14		T61	11		T150	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	2		T37	3		T51	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	2		T246	5		T54	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T188	1		T148	1		T271	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T42	1		T43	1		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T1	1		T144	13		T173	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	1		T36	11		T73	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	3		T117	10		T38	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T152	1		T116	1		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T43	1		T51	23		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T37	7		T108	1		T234	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T42	1		T117	13		T233	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T13	1		T61	7		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T61	12		T152	1		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1396	1			T5	1		T10	2		T11	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	1		T62	1		T144	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T62	1		T144	13		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T61	12		T233	1		T232	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T14	12		T15	9		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T1	1		T12	15		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T3	17		T53	3		T58	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T3	4		T311	17		T324	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17526	1			T2	104		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T38	21		T246	6		T21	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T104	2		T275	4		T77	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T188	11		T148	2		T155	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T146	12		T162	3		T154	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T173	8		T55	4		T252	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T14	1		T73	6		T229	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	1		T117	12		T228	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T120	9		T148	12		T234	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T51	10		T169	8		T257	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T108	12		T234	8		T241	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T117	14		T233	4		T179	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	9		T61	5		T36	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T61	13		T228	14		T146	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T5	12		T10	30		T11	41
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	16		T62	15		T161	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T62	11		T143	7		T208	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T61	12		T232	10		T252	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T14	13		T145	20		T208	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T12	13		T47	10		T143	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T58	1		T273	15		T243	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T311	19		T308	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T117	1		T235	9		T309	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T38	11		T21	2		T285	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T3	17		T145	9		T208	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T3	4		T152	1		T47	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T160	1		T309	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T34	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T42	1		T117	4		T246	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T188	1		T38	21		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T12	2		T43	1		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T144	13		T173	12		T55	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T14	1		T73	8		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	1		T2	3		T117	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T152	1		T36	11		T120	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T43	1		T51	23		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T37	7		T116	1		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T117	13		T147	1		T235	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T13	1		T36	1		T38	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T152	1		T42	1		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	1		T61	7		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T61	12		T146	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T62	1		T144	13		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	1		T62	1		T144	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1405	1			T5	1		T10	2		T11	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	357	1			T1	1		T12	15		T61	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17494	1			T2	104		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T145	11		T208	7		T278	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T47	7		T109	8		T197	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T309	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T117	1		T235	9		T104	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T188	11		T38	11		T148	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T146	12		T162	3		T203	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T173	8		T55	4		T155	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	1		T73	6		T154	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	1		T117	12		T228	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T120	9		T229	3		T148	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T51	10		T241	14		T277	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T108	12		T276	14		T259	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T117	14		T235	12		T253	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	9		T36	3		T38	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T228	14		T146	4		T233	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	4		T61	5		T143	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T61	13		T156	8		T245	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T62	11		T143	7		T234	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	16		T62	15		T161	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T5	12		T10	30		T11	41
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T12	13		T61	12		T47	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

auto[0]

4196

1

T2

1

T5

12

T10

30