Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26640

1

T1

2

T2

108

T3

21

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23062

1

T1

2

T2

108

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3578

1

T3

20

T12

30

T14

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20407

1

T2

104

T3

18

T6

114

auto[1]

6233

1

T1

2

T2

4

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22640

1

T1

2

T2

105

T3

3

auto[1]

4000

1

T2

3

T3

18

T12

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	350	1			T3	1		T144	13		T143	30
values[0]	37	1			T37	7		T151	1		T54	3
values[1]	643	1			T1	1		T61	24		T62	12
values[2]	670	1			T2	4		T14	2		T62	16
values[3]	560	1			T12	2		T47	9		T37	5
values[4]	811	1			T42	1		T73	2		T51	33
values[5]	2810	1			T1	1		T3	20		T5	13
values[6]	741	1			T13	17		T152	1		T42	1
values[7]	748	1			T13	5		T15	9		T143	25
values[8]	799	1			T13	10		T61	25		T150	5
values[9]	977	1			T14	25		T152	1		T36	11
minimum	17494	1			T2	104		T6	114		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	759	1			T14	2		T61	24		T62	28
values[1]	548	1			T2	4		T47	9		T149	7
values[2]	620	1			T12	2		T233	9		T162	7
values[3]	2911	1			T3	3		T5	13		T10	32
values[4]	728	1			T1	1		T3	17		T61	12
values[5]	741	1			T13	22		T15	9		T43	1
values[6]	712	1			T13	10		T47	4		T150	5
values[7]	910	1			T61	25		T36	11		T117	27
values[8]	883	1			T14	25		T144	13		T143	30
values[9]	155	1			T3	1		T152	1		T228	8
minimum	17673	1			T1	1		T2	104		T6	114

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

4196

1

T2

1

T5

12

T10

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T61	13		T62	16		T152	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	2		T62	12		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	3		T47	9		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T149	1		T144	1		T116	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T233	5		T162	4		T154	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	1		T109	9		T234	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1548	1			T5	13		T10	32		T11	44
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	1		T12	14		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	1		T36	4		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	1		T61	6		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T13	22		T15	1		T73	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T43	1		T37	14		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T13	10		T47	4		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T150	1		T143	13		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T117	15		T145	12		T146	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T61	14		T36	1		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	14		T117	15		T188	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T144	1		T143	13		T116	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T3	1		T152	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T228	8		T156	1		T104	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17402	1			T1	1		T2	102		T6	114
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T54	1		T55	1		T268	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T61	11		T54	2		T235	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T144	12		T156	10		T245	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	1		T37	4		T38	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T149	6		T144	12		T154	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T233	4		T162	3		T107	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	1		T109	8		T234	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T153	8		T49	6		T254	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	2		T12	14		T73	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T229	4		T155	13		T197	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	16		T61	6		T53	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T15	8		T73	7		T52	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T37	14		T179	11		T264	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T38	9		T208	5		T238	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T150	4		T143	12		T174	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T117	12		T145	8		T107	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T61	11		T36	10		T38	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T14	11		T117	12		T173	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T144	12		T143	17		T116	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T102	4		T265	1		T326	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T156	10		T248	10		T318	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T2	2		T37	9		T51	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T54	2		T268	9		T327	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T3	1		T147	1		T102	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T144	1		T143	13		T228	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T37	1		T151	1		T324	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T54	1		T195	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	1		T61	13		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T62	12		T144	1		T53	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T2	3		T62	16		T38	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	2		T149	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T47	9		T37	1		T162	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T12	1		T234	9		T238	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T188	20		T233	5		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T42	1		T73	1		T51	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1497	1			T1	1		T5	13		T10	32
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	2		T12	14		T61	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T13	17		T47	4		T73	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T152	1		T42	1		T43	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T13	5		T15	1		T117	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T143	13		T37	14		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T13	10		T117	13		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T61	14		T150	1		T148	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T14	14		T152	1		T117	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T36	1		T116	1		T120	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T2	102		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T102	4		T239	2		T265	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T144	12		T143	17		T173	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T37	6		T324	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T54	2		T195	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T61	11		T246	5		T110	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T144	12		T245	9		T268	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T2	1		T38	10		T246	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T149	6		T144	12		T154	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T37	4		T162	3		T107	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T12	1		T234	7		T238	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T233	4		T108	2		T237	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T73	1		T51	15		T145	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T153	8		T49	6		T229	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	18		T12	14		T61	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T73	7		T52	1		T161	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T179	11		T264	14		T321	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T15	8		T117	3		T38	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T143	12		T37	14		T174	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T117	9		T145	8		T238	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T61	11		T150	4		T236	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	11		T117	12		T173	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T36	10		T116	1		T38	25
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	2		T37	3		T51	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T61	12		T62	1		T152	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T14	1		T62	1		T144	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	3		T47	2		T37	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T149	7		T144	13		T116	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T233	5		T162	4		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	2		T109	9		T234	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T5	1		T10	2		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	3		T12	15		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	1		T36	1		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	17		T61	7		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	2		T15	9		T73	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T43	1		T37	15		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	1		T47	1		T38	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T150	5		T143	13		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T117	14		T145	9		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T61	12		T36	11		T38	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T14	12		T117	13		T188	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T144	13		T143	18		T116	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T3	1		T152	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T228	1		T156	11		T104	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17532	1			T1	1		T2	104		T6	114
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T54	3		T55	1		T268	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T61	12		T62	15		T179	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	1		T62	11		T156	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T2	1		T47	7		T38	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T154	7		T253	8		T234	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T233	4		T162	3		T154	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T109	8		T234	8		T197	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T5	12		T10	30		T11	41
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	13		T143	7		T51	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T36	3		T229	3		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T61	5		T155	13		T105	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	20		T73	6		T228	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T37	13		T179	9		T264	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	9		T47	3		T208	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T143	12		T174	5		T232	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T117	13		T145	11		T146	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T61	13		T148	2		T108	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T14	13		T117	14		T188	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T143	12		T120	9		T38	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T257	5		T326	13		T303	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T228	7		T104	2		T248	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T146	12		T110	7		T277	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T268	7		T242	15		T328	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T3	1		T147	1		T102	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T144	13		T143	18		T228	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T37	7		T151	1		T324	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T54	3		T195	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	1		T61	12		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T62	1		T144	13		T53	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	3		T62	1		T38	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	1		T149	7		T144	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T47	2		T37	5		T162	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T12	2		T234	8		T238	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T188	1		T233	5		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T42	1		T73	2		T51	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T1	1		T5	1		T10	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	20		T12	15		T61	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	1		T47	1		T73	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T152	1		T42	1		T43	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	1		T15	9		T117	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T143	13		T37	15		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T13	1		T117	10		T145	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T61	12		T150	5		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T14	12		T152	1		T117	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T36	11		T116	2		T120	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17494	1			T2	104		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T249	1		T182	10		T326	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T143	12		T228	7		T39	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T195	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T61	12		T146	12		T110	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T62	11		T245	7		T268	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T2	1		T62	15		T38	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T14	1		T154	7		T253	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T47	7		T162	3		T154	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T234	8		T241	14		T269	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T188	19		T233	4		T108	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T51	10		T145	9		T109	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1177	1			T5	12		T10	30		T11	41
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T12	13		T61	5		T143	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	16		T47	3		T73	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T179	9		T264	15		T318	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T13	4		T117	1		T208	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T143	12		T37	13		T174	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	9		T117	12		T145	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T61	13		T148	2		T241	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	13		T117	14		T188	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T120	9		T38	14		T148	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

auto[0]

4196

1

T2

1

T5

12

T10

30