Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26640

1

T1

2

T2

108

T3

21

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23322

1

T1

1

T2

108

T3

4

auto[ADC_CTRL_FILTER_COND_OUT]

3318

1

T1

1

T3

17

T12

30

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20858

1

T1

1

T2

104

T3

3

auto[1]

5782

1

T1

1

T2

4

T3

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22640

1

T1

2

T2

105

T3

3

auto[1]

4000

1

T2

3

T3

18

T12

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	229	1			T2	4		T14	2		T37	5
values[0]	42	1			T160	1		T190	1		T317	19
values[1]	630	1			T12	28		T152	1		T43	1
values[2]	654	1			T1	1		T3	1		T13	5
values[3]	587	1			T15	9		T42	1		T117	27
values[4]	2686	1			T5	13		T10	32		T11	44
values[5]	909	1			T1	1		T3	3		T14	25
values[6]	889	1			T61	37		T62	16		T43	1
values[7]	678	1			T42	1		T47	4		T117	5
values[8]	750	1			T13	10		T62	12		T152	1
values[9]	1092	1			T3	17		T12	2		T36	11
minimum	17494	1			T2	104		T6	114		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	494	1			T3	1		T12	28		T152	1
values[1]	658	1			T1	1		T13	5		T61	24
values[2]	624	1			T15	9		T42	1		T43	1
values[3]	2774	1			T3	3		T5	13		T10	32
values[4]	999	1			T1	1		T61	37		T62	16
values[5]	819	1			T43	1		T143	55		T37	7
values[6]	629	1			T62	12		T42	1		T117	5
values[7]	765	1			T3	17		T13	10		T152	1
values[8]	968	1			T2	4		T12	2		T73	2
values[9]	161	1			T14	2		T36	11		T252	13
minimum	17749	1			T2	104		T6	114		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

4196

1

T2

1

T5

12

T10

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T3	1		T47	8		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	14		T152	1		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	5		T162	4		T156	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	1		T61	13		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T43	1		T117	15		T146	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T15	1		T42	1		T116	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1504	1			T3	1		T5	13		T10	32
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	17		T37	14		T233	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T1	1		T61	20		T144	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T62	16		T152	1		T36	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T143	26		T37	1		T120	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T43	1		T173	1		T234	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T42	1		T117	2		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T62	12		T54	1		T235	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T152	1		T47	4		T73	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T3	1		T13	10		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T2	3		T143	8		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T12	1		T73	1		T145	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T14	2		T36	1		T252	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T192	9		T329	1		T193	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17457	1			T2	102		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T43	1		T160	1		T52	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T149	6		T150	4		T110	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	14		T38	9		T237	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T162	3		T156	10		T56	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T61	11		T144	12		T117	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T117	12		T161	2		T236	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T15	8		T38	26		T238	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T3	2		T14	11		T153	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T37	14		T233	4		T107	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T61	17		T144	24		T145	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T54	4		T155	15		T97	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T143	29		T37	6		T174	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T173	1		T234	7		T155	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T117	3		T53	1		T54	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T54	2		T235	9		T236	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T73	7		T51	15		T208	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	16		T173	11		T108	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T2	1		T37	4		T116	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	1		T73	1		T145	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T36	10		T252	11		T185	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T192	14		T329	11		T330	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T2	2		T37	3		T51	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T52	1		T268	9		T292	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T2	3		T14	2		T37	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T145	10		T55	7		T248	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T317	10		T331	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T160	1		T190	1		T290	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T47	8		T149	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	14		T152	1		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	1		T13	5		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	1		T61	13		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T117	15		T161	14		T156	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T15	1		T42	1		T38	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1462	1			T5	13		T10	32		T11	44
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	17		T116	1		T38	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T1	1		T3	1		T14	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T152	1		T36	4		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T61	20		T143	26		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T62	16		T43	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T42	1		T47	4		T117	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T235	1		T234	9		T155	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T152	1		T51	18		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	10		T62	12		T173	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T36	1		T73	7		T143	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T3	1		T12	1		T42	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T2	102		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T2	1		T37	4		T59	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T145	11		T55	4		T248	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T317	9		T331	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T149	6		T150	4		T179	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	14		T38	9		T52	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T162	3		T180	2		T167	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T61	11		T144	12		T117	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T117	12		T161	2		T156	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T15	8		T38	16		T246	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	972	1			T153	8		T49	6		T144	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T38	10		T233	4		T107	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	2		T14	11		T144	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T37	14		T155	15		T39	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T61	17		T143	29		T37	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T173	1		T54	4		T97	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T117	3		T53	1		T54	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T235	9		T234	7		T155	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T51	15		T208	5		T246	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T173	11		T54	2		T264	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T36	10		T73	7		T116	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	16		T12	1		T73	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	2		T37	3		T51	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T3	1		T47	1		T149	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	15		T152	1		T38	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	1		T162	4		T156	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	1		T61	12		T144	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T43	1		T117	13		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T15	9		T42	1		T116	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1307	1			T3	3		T5	1		T10	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	1		T37	15		T233	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T1	1		T61	19		T144	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T62	1		T152	1		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T143	31		T37	7		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T43	1		T173	2		T234	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T42	1		T117	4		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T62	1		T54	3		T235	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T152	1		T47	1		T73	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	17		T13	1		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T2	3		T143	1		T37	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	2		T73	2		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T14	1		T36	11		T252	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T192	15		T329	12		T193	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17585	1			T2	104		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T43	1		T160	1		T52	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T47	7		T108	12		T110	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	13		T154	3		T237	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	4		T162	3		T156	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T61	12		T117	12		T104	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T117	14		T146	12		T161	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T38	25		T257	5		T319	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1179	1			T5	12		T10	30		T11	41
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T13	16		T37	13		T233	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T61	18		T145	11		T228	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T62	15		T36	3		T155	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T143	24		T120	9		T146	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T234	8		T155	12		T259	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T117	1		T54	4		T245	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T62	11		T245	3		T318	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T47	3		T73	6		T51	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	9		T188	19		T173	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	1		T143	7		T228	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T145	9		T179	4		T154	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T14	1		T252	1		T185	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T192	8		T330	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T179	9		T197	11		T105	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T52	3		T268	7		T311	19

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T2	3		T14	1		T37	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T145	12		T55	7		T248	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T317	10		T331	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T160	1		T190	1		T290	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T47	1		T149	7		T150	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	15		T152	1		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	1		T13	1		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	1		T61	12		T144	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T117	13		T161	3		T156	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T15	9		T42	1		T38	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1293	1			T5	1		T10	2		T11	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T13	1		T116	1		T38	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T1	1		T3	3		T14	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T152	1		T36	1		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T61	19		T143	31		T37	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T62	1		T43	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T42	1		T47	1		T117	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T235	10		T234	8		T155	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T152	1		T51	23		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T13	1		T62	1		T173	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	389	1			T36	11		T73	8		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	17		T12	2		T42	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17494	1			T2	104		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T2	1		T14	1		T228	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T145	9		T55	4		T248	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T317	9		T331	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T290	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T47	7		T179	9		T108	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	13		T52	3		T154	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	4		T162	3		T248	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T61	12		T117	12		T104	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T117	14		T161	13		T156	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T38	14		T257	5		T319	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1141	1			T5	12		T10	30		T11	41
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	16		T38	11		T233	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T14	13		T145	11		T228	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T36	3		T37	13		T155	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T61	18		T143	24		T120	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T62	15		T260	14		T319	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T47	3		T117	1		T54	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T234	8		T155	12		T245	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T51	10		T208	7		T109	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T13	9		T62	11		T173	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T73	6		T143	7		T208	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T188	19		T179	4		T154	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

auto[0]

4196

1

T2

1

T5

12

T10

30