Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26640

1

T1

2

T2

108

T3

21

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23005

1

T1

1

T2

108

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3635

1

T1

1

T3

3

T12

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20538

1

T1

1

T2

104

T3

4

auto[1]

6102

1

T1

1

T2

4

T3

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22640

1

T1

2

T2

105

T3

3

auto[1]

4000

1

T2

3

T3

18

T12

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	44	1			T208	15		T32	12		T285	17
values[0]	173	1			T51	33		T241	24		T310	27
values[1]	724	1			T62	16		T152	2		T144	13
values[2]	661	1			T13	10		T43	1		T143	33
values[3]	679	1			T36	4		T43	2		T73	14
values[4]	614	1			T1	1		T3	17		T61	25
values[5]	568	1			T3	1		T13	5		T61	24
values[6]	724	1			T1	1		T2	4		T61	12
values[7]	808	1			T13	17		T14	25		T15	9
values[8]	2866	1			T5	13		T10	32		T11	44
values[9]	1285	1			T3	3		T12	2		T14	2
minimum	17494	1			T2	104		T6	114		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1029	1			T13	10		T152	1		T43	1
values[1]	754	1			T62	16		T152	1		T73	14
values[2]	629	1			T62	12		T36	4		T43	1
values[3]	453	1			T1	1		T3	17		T13	5
values[4]	750	1			T3	1		T61	24		T144	13
values[5]	669	1			T2	4		T61	12		T42	1
values[6]	3020	1			T1	1		T5	13		T10	32
values[7]	629	1			T12	28		T152	1		T37	7
values[8]	923	1			T3	3		T12	2		T14	2
values[9]	257	1			T47	4		T144	13		T160	1
minimum	17527	1			T2	104		T6	114		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

4196

1

T2

1

T5

12

T10

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T117	2		T228	15		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T13	10		T152	1		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T152	1		T73	7		T143	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T62	16		T143	8		T117	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T62	12		T110	8		T235	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T36	4		T43	1		T145	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	1		T61	14		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T1	1		T13	5		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	1		T144	1		T229	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T61	13		T179	10		T107	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T2	3		T61	6		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T37	14		T246	1		T252	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1563	1			T1	1		T5	13		T10	32
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T15	1		T42	1		T47	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T145	12		T154	4		T107	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	14		T152	1		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T12	1		T42	1		T73	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T3	1		T14	2		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T160	1		T104	3		T248	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T47	4		T144	1		T97	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17364	1			T2	102		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T116	1		T185	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T117	3		T173	1		T54	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T144	12		T51	15		T208	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T73	7		T143	12		T174	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T117	12		T38	16		T54	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T110	4		T235	9		T197	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T145	11		T53	1		T266	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T3	16		T61	11		T37	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T150	4		T52	1		T156	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T144	12		T229	4		T233	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T61	11		T179	11		T107	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T2	1		T61	6		T196	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T37	14		T246	5		T252	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	947	1			T14	11		T153	8		T49	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T15	8		T149	6		T117	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T145	8		T107	15		T252	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	14		T37	6		T38	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	1		T73	1		T54	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T3	2		T36	10		T143	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T248	7		T322	3		T285	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T144	12		T97	11		T302	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	2		T37	3		T51	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T116	1		T185	14		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T285	8		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T208	8		T32	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T241	13		T310	13		T332	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T51	18		T231	10		T333	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T152	1		T117	2		T228	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T62	16		T152	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T143	13		T148	13		T174	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T13	10		T43	1		T143	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T73	7		T160	1		T109	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T36	4		T43	2		T117	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	1		T61	14		T62	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T1	1		T47	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	1		T144	1		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	5		T61	13		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	1		T2	3		T61	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T37	14		T108	13		T57	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T13	17		T14	14		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T15	1		T42	1		T47	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1566	1			T5	13		T10	32		T11	44
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	14		T160	1		T148	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T12	1		T42	1		T73	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	396	1			T3	1		T14	2		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T2	102		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T285	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T208	7		T32	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T241	11		T310	14		T332	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T51	15		T231	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T117	3		T173	1		T155	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T144	12		T116	1		T208	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T143	12		T174	12		T54	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T38	16		T246	8		T54	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T73	7		T109	8		T110	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T117	12		T145	11		T53	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	16		T61	11		T245	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T156	10		T238	2		T191	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T144	12		T37	4		T229	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T61	11		T150	4		T52	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T2	1		T61	6		T196	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T37	14		T57	1		T239	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T14	11		T107	15		T108	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T15	8		T149	6		T117	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	991	1			T153	8		T49	6		T145	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	14		T162	3		T154	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	1		T73	1		T54	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T3	2		T36	10		T144	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	2		T37	3		T51	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T117	4		T228	1		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T13	1		T152	1		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T152	1		T73	8		T143	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T62	1		T143	1		T117	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T62	1		T110	5		T235	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T36	1		T43	1		T145	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	17		T61	12		T37	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T1	1		T13	1		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	1		T144	13		T229	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T61	12		T179	12		T107	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	3		T61	7		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T37	15		T246	6		T252	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T1	1		T5	1		T10	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T15	9		T42	1		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T145	9		T154	1		T107	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	15		T152	1		T37	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	2		T42	1		T73	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T3	3		T14	1		T36	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T160	1		T104	1		T248	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T47	1		T144	13		T97	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17495	1			T2	104		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T116	2		T185	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T117	1		T228	14		T148	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T13	9		T51	10		T146	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T73	6		T143	12		T148	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T62	15		T143	7		T117	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T62	11		T110	7		T197	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T36	3		T145	9		T284	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T61	13		T245	3		T198	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T13	4		T52	3		T59	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T229	3		T188	11		T233	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T61	12		T179	9		T107	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	1		T61	5		T203	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T37	13		T252	2		T334	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T5	12		T10	30		T11	41
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T47	7		T117	12		T148	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T145	11		T154	3		T107	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T12	13		T38	11		T162	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T188	19		T228	7		T146	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	1		T143	12		T208	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T104	2		T248	7		T322	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T47	3		T302	13		T304	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T185	15		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T285	10		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T208	8		T32	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T241	12		T310	15		T332	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T51	23		T231	12		T333	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T152	1		T117	4		T228	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T62	1		T152	1		T144	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T143	13		T148	1		T174	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	1		T43	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T73	8		T160	1		T109	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T36	1		T43	2		T117	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	17		T61	12		T62	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T1	1		T47	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	1		T144	13		T37	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	1		T61	12		T150	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T1	1		T2	3		T61	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T37	15		T108	1		T57	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	1		T14	12		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T15	9		T42	1		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T5	1		T10	2		T11	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	15		T160	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T12	2		T42	1		T73	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	429	1			T3	3		T14	1		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17494	1			T2	104		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T285	7		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T208	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T241	12		T310	12		T332	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T51	10		T231	9		T333	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T117	1		T228	14		T148	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T62	15		T146	4		T208	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T143	12		T148	12		T174	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	9		T143	7		T38	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T73	6		T109	8		T110	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T36	3		T117	14		T145	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T61	13		T62	11		T188	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T191	11		T284	14		T166	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T229	3		T233	4		T161	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T13	4		T61	12		T52	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	1		T61	5		T203	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T37	13		T108	12		T39	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	16		T14	13		T107	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T47	7		T117	12		T179	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T5	12		T10	30		T11	41
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T12	13		T148	2		T162	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T188	19		T228	7		T146	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T14	1		T47	3		T143	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

auto[0]

4196

1

T2

1

T5

12

T10

30