Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26640

1

T1

2

T2

108

T3

21

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22930

1

T1

2

T2

104

T3

4

auto[ADC_CTRL_FILTER_COND_OUT]

3710

1

T2

4

T3

17

T13

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20340

1

T1

1

T2

108

T3

4

auto[1]

6300

1

T1

1

T3

17

T5

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22640

1

T1

2

T2

105

T3

3

auto[1]

4000

1

T2

3

T3

18

T12

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	289	1			T37	5		T52	7		T57	6
values[0]	41	1			T54	8		T176	8		T184	25
values[1]	683	1			T13	17		T62	16		T42	1
values[2]	2920	1			T1	1		T2	4		T5	13
values[3]	705	1			T3	17		T13	10		T14	2
values[4]	699	1			T12	2		T43	1		T143	25
values[5]	550	1			T12	28		T14	25		T15	9
values[6]	595	1			T3	4		T62	12		T42	1
values[7]	607	1			T61	24		T37	7		T120	10
values[8]	980	1			T13	5		T61	25		T36	15
values[9]	1077	1			T1	1		T152	1		T117	22
minimum	17494	1			T2	104		T6	114		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	655	1			T1	1		T13	17		T62	16
values[1]	2894	1			T2	4		T5	13		T10	32
values[2]	736	1			T3	17		T143	25		T116	2
values[3]	615	1			T12	2		T61	12		T43	2
values[4]	548	1			T12	28		T14	25		T15	9
values[5]	745	1			T3	4		T42	1		T43	1
values[6]	522	1			T61	24		T120	10		T38	10
values[7]	1030	1			T13	5		T61	25		T36	15
values[8]	930	1			T1	1		T152	1		T229	8
values[9]	178	1			T37	5		T235	15		T39	4
minimum	17787	1			T2	104		T6	114		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

4196

1

T2

1

T5

12

T10

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	1		T62	16		T42	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T13	17		T73	7		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1480	1			T5	13		T10	32		T11	44
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	3		T13	10		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T116	1		T38	15		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T3	1		T143	13		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	1		T61	6		T43	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T145	12		T151	1		T234	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	14		T14	14		T62	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T15	1		T47	8		T188	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	2		T43	1		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T42	1		T144	1		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T160	1		T108	13		T271	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T61	13		T120	10		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T13	5		T36	5		T47	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T61	14		T144	1		T116	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	1		T152	1		T229	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T52	6		T53	2		T162	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T39	1		T168	9		T335	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T37	1		T235	10		T301	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17420	1			T2	102		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T149	1		T143	13		T161	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T108	2		T110	4		T278	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T73	7		T144	12		T234	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T153	8		T49	6		T51	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	1		T73	1		T117	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T116	1		T38	16		T208	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	16		T143	12		T38	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	1		T61	6		T233	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T145	8		T234	11		T97	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T12	14		T14	11		T117	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T15	8		T266	13		T252	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	2		T37	6		T154	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T144	12		T208	7		T53	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T222	15		T105	6		T177	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T61	11		T38	9		T173	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T36	10		T37	14		T107	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T61	11		T144	12		T117	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T229	4		T107	15		T57	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T52	1		T162	3		T246	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T39	3		T335	9		T192	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T37	4		T235	5		T336	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	2		T150	4		T37	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T149	6		T143	17		T161	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T57	5		T191	12		T281	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T37	1		T52	6		T197	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T184	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T54	6		T176	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T62	16		T42	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T13	17		T149	1		T73	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1501	1			T1	1		T5	13		T10	32
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	3		T152	1		T73	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T14	2		T116	1		T38	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	1		T13	10		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	1		T43	1		T233	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T143	13		T145	12		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	14		T14	14		T61	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T15	1		T47	8		T188	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	2		T62	12		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T42	1		T144	1		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T37	1		T188	12		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T61	13		T120	10		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T13	5		T36	5		T47	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T61	14		T144	1		T116	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T1	1		T152	1		T229	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T117	13		T162	4		T246	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T2	102		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T57	1		T191	12		T77	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T37	4		T52	1		T197	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T184	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T54	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T150	4		T108	2		T110	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T149	6		T73	7		T143	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	996	1			T153	8		T49	6		T51	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	1		T73	1		T144	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T116	1		T38	16		T208	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	16		T38	9		T246	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	1		T233	4		T173	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T143	12		T145	8		T234	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	14		T14	11		T61	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T15	8		T266	13		T252	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	2		T145	11		T154	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T144	12		T208	7		T53	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T37	6		T222	15		T105	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T61	11		T38	9		T56	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T36	10		T37	14		T107	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T61	11		T144	12		T179	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T229	4		T107	15		T59	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T117	9		T162	3		T246	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	2		T37	3		T51	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T1	1		T62	1		T42	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	1		T73	8		T144	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T5	1		T10	2		T11	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T2	3		T13	1		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T116	2		T38	17		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	17		T143	13		T38	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	2		T61	7		T43	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T145	9		T151	1		T234	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	15		T14	12		T62	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T15	9		T47	1		T188	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	4		T43	1		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T42	1		T144	13		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T160	1		T108	1		T271	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T61	12		T120	1		T38	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T13	1		T36	12		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T61	12		T144	13		T116	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	1		T152	1		T229	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T52	4		T53	2		T162	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T39	4		T168	1		T335	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T37	5		T235	6		T301	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17526	1			T2	104		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T149	7		T143	18		T161	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T62	15		T148	10		T108	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	16		T73	6		T148	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1152	1			T5	12		T10	30		T11	41
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	1		T13	9		T117	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T38	14		T208	7		T173	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T143	12		T268	7		T259	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T61	5		T233	4		T156	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T145	11		T234	8		T198	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T12	13		T14	13		T62	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T47	7		T188	19		T252	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T188	11		T154	7		T260	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T148	2		T208	7		T253	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T108	12		T104	2		T105	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T61	12		T120	9		T146	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T13	4		T36	3		T47	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T61	13		T117	12		T179	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T229	3		T107	8		T57	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T52	3		T162	3		T174	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T168	8		T335	15		T192	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T235	9		T337	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T250	11		T181	17		T182	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T143	12		T161	13		T54	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T57	5		T191	13		T281	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T37	5		T52	4		T197	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T184	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T54	4		T176	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T62	1		T42	1		T150	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T13	1		T149	7		T73	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T1	1		T5	1		T10	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T2	3		T152	1		T73	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	1		T116	2		T38	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T3	17		T13	1		T38	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	2		T43	1		T233	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T143	13		T145	9		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	15		T14	12		T61	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T15	9		T47	1		T188	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	4		T62	1		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T42	1		T144	13		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T37	7		T188	1		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T61	12		T120	1		T38	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T13	1		T36	12		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T61	12		T144	13		T116	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	1		T152	1		T229	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T117	10		T162	4		T246	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17494	1			T2	104		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T57	1		T191	11		T281	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T52	3		T197	11		T250	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T184	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T54	4		T176	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T62	15		T148	10		T108	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T13	16		T73	6		T143	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1173	1			T5	12		T10	30		T11	41
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	1		T117	14		T228	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T14	1		T38	14		T208	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T13	9		T245	7		T259	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T233	4		T173	8		T58	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T143	12		T145	11		T234	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T12	13		T14	13		T61	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T47	7		T188	19		T252	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T62	11		T145	9		T154	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T148	2		T208	7		T253	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T188	11		T108	12		T104	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T61	12		T120	9		T146	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T13	4		T36	3		T47	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T61	13		T179	9		T234	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T229	3		T107	8		T59	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T117	12		T162	3		T174	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

auto[0]

4196

1

T2

1

T5

12

T10

30