Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	1		T43	1		T47	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T51	23		T38	10		T233	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	1		T15	9		T42	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1324	1			T5	1		T10	2		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T36	11		T143	18		T145	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T47	1		T116	1		T38	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T152	1		T144	13		T37	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	17		T42	1		T233	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T3	3		T42	1		T43	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T37	5		T117	13		T146	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T61	7		T38	17		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T61	12		T116	2		T117	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T152	1		T36	1		T73	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T150	5		T143	1		T161	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	1		T2	3		T12	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T13	1		T152	1		T229	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	1		T14	1		T62	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	1		T61	12		T188	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T147	1		T196	10		T250	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T14	12		T108	3		T99	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17541	1			T2	104		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T188	1		T155	16		T39	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	9		T145	11		T146	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T51	10		T55	4		T234	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	16		T228	7		T52	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1217	1			T5	12		T10	30		T11	41
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T143	12		T145	9		T154	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T47	7		T38	11		T109	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T37	13		T179	9		T155	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T233	4		T107	8		T248	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T234	16		T255	10		T256	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T117	14		T146	4		T203	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T61	5		T38	14		T156	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T61	12		T117	12		T253	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T36	3		T73	6		T148	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T143	7		T161	13		T235	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T2	1		T12	13		T62	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	4		T229	3		T208	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T14	1		T62	11		T143	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T61	13		T188	19		T148	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T250	8		T257	5		T258	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T14	13		T108	20		T252	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T259	9		T260	13		T261	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T188	11		T155	13		T204	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T147	1		T246	5		T55	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T14	12		T61	12		T188	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T249	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	1		T43	1		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T51	23		T188	1		T38	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T13	1		T15	9		T149	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	2		T47	1		T228	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T36	11		T42	1		T143	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T47	1		T116	1		T38	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T152	1		T144	13		T37	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T42	1		T233	5		T107	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T42	1		T43	2		T144	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	17		T37	5		T117	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	3		T38	17		T234	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T61	12		T116	2		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T61	7		T152	1		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T150	5		T143	1		T117	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T1	1		T12	15		T62	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	1		T152	1		T229	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	1		T2	3		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1401	1			T3	1		T5	1		T10	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17494	1			T2	104		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T107	14		T182	9		T258	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T14	13		T61	13		T188	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T13	9		T145	11		T146	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T51	10		T188	11		T55	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	16		T228	7		T154	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T47	3		T228	14		T262	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T143	12		T145	9		T52	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T47	7		T38	11		T109	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T37	13		T179	9		T245	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T233	4		T107	8		T178	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T234	8		T155	12		T58	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T117	14		T203	12		T248	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T38	14		T234	8		T105	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T61	12		T146	4		T241	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T61	5		T36	3		T148	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T143	7		T117	12		T253	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	13		T62	15		T73	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	4		T229	3		T148	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	1		T14	1		T62	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1238	1			T5	12		T10	30		T11	41

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

auto[0]

4196

1

T2

1

T5

12

T10

30