Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26640

1

T1

2

T2

108

T3

21

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22838

1

T2

104

T3

1

T5

13

auto[ADC_CTRL_FILTER_COND_OUT]

3802

1

T1

2

T2

4

T3

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20882

1

T1

1

T2

104

T3

1

auto[1]

5758

1

T1

1

T2

4

T3

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22640

1

T1

2

T2

105

T3

3

auto[1]

4000

1

T2

3

T3

18

T12

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	35	1			T253	17		T103	1		T105	17
values[0]	59	1			T177	11		T270	1		T181	18
values[1]	682	1			T13	22		T152	1		T42	1
values[2]	640	1			T3	3		T42	1		T144	13
values[3]	627	1			T12	2		T61	25		T152	1
values[4]	618	1			T12	28		T15	9		T62	12
values[5]	3023	1			T5	13		T10	32		T11	44
values[6]	816	1			T3	17		T13	10		T14	25
values[7]	671	1			T2	4		T61	12		T43	1
values[8]	859	1			T36	11		T73	14		T117	27
values[9]	1116	1			T1	2		T3	1		T14	2
minimum	17494	1			T2	104		T6	114		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	908	1			T13	22		T152	1		T42	1
values[1]	529	1			T3	3		T12	2		T42	1
values[2]	671	1			T15	9		T61	25		T152	1
values[3]	2808	1			T5	13		T10	32		T11	44
values[4]	953	1			T13	10		T14	25		T62	16
values[5]	784	1			T3	17		T61	24		T43	1
values[6]	646	1			T2	4		T61	12		T150	5
values[7]	865	1			T1	1		T36	11		T73	14
values[8]	797	1			T1	1		T3	1		T14	2
values[9]	184	1			T228	8		T173	20		T235	21
minimum	17495	1			T2	104		T6	114		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

4196

1

T2

1

T5

12

T10

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T13	5		T149	1		T116	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T13	17		T152	1		T42	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	1		T144	1		T146	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T3	1		T42	1		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T15	1		T152	1		T143	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T61	14		T233	1		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1486	1			T5	13		T10	32		T11	44
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T12	14		T62	12		T36	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T47	4		T116	1		T117	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T13	10		T14	14		T62	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T43	1		T47	8		T37	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T3	1		T61	13		T188	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T150	1		T117	2		T52	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T2	3		T61	6		T145	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T234	10		T155	13		T99	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	1		T36	1		T73	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	1		T73	1		T144	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	1		T14	2		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T271	1		T245	8		T32	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T228	8		T173	9		T235	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T2	102		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T272	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T149	6		T116	1		T38	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T143	12		T246	5		T58	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T12	1		T144	12		T161	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T3	2		T54	4		T235	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T15	8		T143	17		T229	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T61	11		T173	1		T109	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	927	1			T153	8		T49	6		T254	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	14		T37	14		T208	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T117	9		T174	12		T155	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T14	11		T54	2		T232	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T37	10		T233	4		T246	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	16		T61	11		T38	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T150	4		T117	3		T52	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	1		T61	6		T145	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T234	8		T155	13		T237	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T36	10		T73	7		T145	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T73	1		T144	24		T51	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T117	12		T38	10		T108	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T245	9		T32	9		T267	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T173	11		T235	8		T259	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	2		T37	3		T51	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T105	11		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T253	9		T103	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T177	1		T270	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T181	18		T273	16		T274	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T13	5		T149	1		T116	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	17		T152	1		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T144	1		T38	1		T146	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	1		T42	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T12	1		T152	1		T143	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T61	14		T173	1		T109	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T15	1		T152	1		T229	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	14		T62	12		T36	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1561	1			T5	13		T10	32		T11	44
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T62	16		T47	1		T120	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T47	12		T37	2		T116	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T3	1		T13	10		T14	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T43	1		T150	1		T117	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	3		T61	6		T146	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T234	9		T57	4		T241	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T36	1		T73	7		T117	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T3	1		T73	1		T144	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T1	2		T14	2		T42	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T2	102		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T105	6		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T253	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T177	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T149	6		T116	1		T55	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T143	12		T246	5		T58	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T144	12		T38	9		T161	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T3	2		T54	4		T235	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T12	1		T143	17		T53	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T61	11		T173	1		T109	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T15	8		T229	4		T275	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	14		T37	14		T237	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T153	8		T49	6		T117	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T208	5		T232	10		T276	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T37	10		T233	4		T174	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T3	16		T14	11		T61	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T150	4		T117	3		T52	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	1		T61	6		T208	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T234	11		T57	1		T241	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T36	10		T73	7		T117	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T73	1		T144	24		T51	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T38	10		T173	11		T108	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	2		T37	3		T51	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T13	1		T149	7		T116	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	1		T152	1		T42	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	2		T144	13		T146	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	3		T42	1		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	9		T152	1		T143	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T61	12		T233	1		T173	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1243	1			T5	1		T10	2		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	15		T62	1		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T47	1		T116	1		T117	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T13	1		T14	12		T62	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T43	1		T47	1		T37	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T3	17		T61	12		T188	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T150	5		T117	4		T52	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	3		T61	7		T145	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T234	9		T155	14		T99	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T1	1		T36	11		T73	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	1		T73	2		T144	26
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T1	1		T14	1		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T271	1		T245	10		T32	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T228	1		T173	12		T235	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17494	1			T2	104		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T272	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	4		T55	4		T59	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	16		T143	12		T188	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T146	4		T148	10		T161	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T203	12		T197	11		T277	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T143	12		T229	3		T278	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T61	13		T109	8		T191	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1170	1			T5	12		T10	30		T11	41
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	13		T62	11		T36	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T47	3		T117	12		T154	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T13	9		T14	13		T62	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T47	7		T233	4		T148	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T61	12		T188	19		T38	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T117	1		T52	3		T179	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	1		T61	5		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T234	9		T155	12		T237	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T73	6		T145	9		T252	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T143	7		T51	10		T154	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	1		T117	14		T38	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T245	7		T32	2		T279	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T228	7		T173	8		T235	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T105	13		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T253	9		T103	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T177	11		T270	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T181	1		T273	1		T274	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	1		T149	7		T116	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	1		T152	1		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T144	13		T38	10		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	3		T42	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	2		T152	1		T143	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T61	12		T173	2		T109	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	9		T152	1		T229	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	15		T62	1		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T5	1		T10	2		T11	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T62	1		T47	1		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T47	2		T37	12		T116	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T3	17		T13	1		T14	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T43	1		T150	5		T117	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	3		T61	7		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T234	12		T57	5		T241	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T36	11		T73	8		T117	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T3	1		T73	2		T144	26
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T1	2		T14	1		T42	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17494	1			T2	104		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T105	4		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T253	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T181	17		T273	15		T280	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	4		T55	4		T59	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	16		T143	12		T188	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T146	4		T148	10		T161	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T203	12		T197	11		T277	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T143	12		T278	17		T281	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T61	13		T109	8		T259	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T229	3		T248	8		T275	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	13		T62	11		T36	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T5	12		T10	30		T11	41
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T62	15		T120	9		T188	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T47	10		T233	4		T148	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	9		T14	13		T61	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T117	1		T52	3		T179	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	1		T61	5		T146	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T234	8		T241	12		T277	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T73	6		T117	14		T145	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T143	7		T51	10		T154	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	1		T38	11		T228	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

auto[0]

4196

1

T2

1

T5

12

T10

30