Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26640

1

T1

2

T2

108

T3

21

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20827

1

T1

2

T2

108

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

5813

1

T3

18

T5

13

T10

32

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20531

1

T1

1

T2

108

T6

114

auto[1]

6109

1

T1

1

T3

21

T5

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22640

1

T1

2

T2

105

T3

3

auto[1]

4000

1

T2

3

T3

18

T12

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	42	1			T188	20		T99	1		T278	1
values[0]	48	1			T55	11		T245	7		T260	14
values[1]	711	1			T13	10		T43	1		T47	1
values[2]	657	1			T12	2		T13	17		T15	9
values[3]	733	1			T152	1		T36	11		T42	1
values[4]	637	1			T3	17		T42	1		T144	13
values[5]	757	1			T42	1		T43	2		T144	13
values[6]	734	1			T3	3		T61	24		T38	31
values[7]	778	1			T12	28		T61	12		T36	4
values[8]	784	1			T1	1		T2	4		T13	5
values[9]	3265	1			T1	1		T3	1		T5	13
minimum	17494	1			T2	104		T6	114		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	911	1			T12	2		T13	10		T43	1
values[1]	2893	1			T5	13		T10	32		T11	44
values[2]	645	1			T13	17		T36	11		T47	8
values[3]	645	1			T3	17		T152	1		T42	1
values[4]	869	1			T3	3		T61	24		T42	1
values[5]	638	1			T61	12		T143	8		T116	2
values[6]	900	1			T152	1		T36	4		T73	16
values[7]	652	1			T1	2		T2	4		T12	28
values[8]	677	1			T3	1		T14	27		T61	25
values[9]	305	1			T208	13		T179	5		T108	23
minimum	17505	1			T2	104		T6	114		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

4196

1

T2

1

T5

12

T10

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	10		T43	1		T47	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T12	1		T51	18		T188	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T15	1		T42	1		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1526	1			T5	13		T10	32		T11	44
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T13	17		T36	1		T143	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T47	8		T116	1		T38	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T152	1		T144	1		T37	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	1		T42	1		T233	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	1		T42	1		T43	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T61	13		T37	1		T117	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T61	6		T116	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T143	8		T117	13		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T152	1		T36	4		T73	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T150	1		T161	14		T235	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	2		T2	3		T12	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	5		T152	1		T229	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T14	2		T62	12		T143	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	1		T14	14		T61	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T179	5		T196	1		T197	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T208	8		T108	21		T99	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17373	1			T2	102		T6	114		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T144	12		T145	8		T53	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T12	1		T51	15		T38	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T15	8		T149	6		T37	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	995	1			T153	8		T49	6		T254	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T36	10		T143	17		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T38	10		T109	8		T97	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T144	12		T37	14		T179	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	16		T233	4		T107	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	2		T144	12		T234	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T61	11		T37	4		T117	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T61	6		T116	1		T54	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T117	9		T173	1		T253	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T73	8		T38	16		T246	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T150	4		T161	2		T235	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T2	1		T12	14		T57	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T229	4		T208	7		T235	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T143	12		T117	3		T162	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	11		T61	11		T236	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T196	9		T197	2		T204	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T208	5		T108	2		T238	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T2	2		T37	3		T51	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T257	6		T287	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T188	20		T99	1		T278	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T245	4		T260	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T55	7		T288	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	10		T43	1		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T51	18		T188	12		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	17		T15	1		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	1		T228	15		T233	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T152	1		T36	1		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T47	12		T116	1		T38	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T144	1		T37	14		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T3	1		T42	1		T233	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T42	1		T43	2		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T37	1		T117	15		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	1		T38	15		T234	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T61	13		T146	5		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	14		T61	6		T36	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T143	8		T117	13		T253	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	1		T2	3		T62	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T13	5		T152	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T1	1		T14	2		T62	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1662	1			T3	1		T5	13		T10	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T2	102		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T287	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T245	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T55	4		T288	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T144	12		T145	8		T53	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T51	15		T38	9		T234	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T15	8		T149	6		T37	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T12	1		T97	11		T102	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T36	10		T143	17		T145	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T38	10		T109	8		T60	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T144	12		T37	14		T179	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T3	16		T233	4		T107	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T144	12		T246	8		T234	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T37	4		T117	12		T56	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	2		T38	16		T234	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T61	11		T173	1		T196	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	14		T61	6		T73	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T117	9		T253	8		T241	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	1		T73	7		T237	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T150	4		T229	4		T208	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T143	12		T117	3		T162	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1178	1			T14	11		T61	11		T153	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	2		T37	3		T51	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	1		T43	1		T47	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T12	2		T51	23		T188	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T15	9		T42	1		T149	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1319	1			T5	1		T10	2		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	1		T36	11		T143	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T47	1		T116	1		T38	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T152	1		T144	13		T37	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	17		T42	1		T233	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T3	3		T42	1		T43	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T61	12		T37	5		T117	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T61	7		T116	2		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T143	1		T117	10		T173	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T152	1		T36	1		T73	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T150	5		T161	3		T235	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	2		T2	3		T12	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	1		T152	1		T229	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T14	1		T62	1		T143	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	1		T14	12		T61	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T179	1		T196	10		T197	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T208	6		T108	3		T99	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17504	1			T2	104		T6	114		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	9		T145	11		T146	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T51	10		T188	11		T55	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T228	7		T52	3		T174	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1202	1			T5	12		T10	30		T11	41
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	16		T143	12		T145	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T47	7		T38	11		T109	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T37	13		T179	9		T58	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T233	4		T107	8		T248	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T234	16		T155	12		T255	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T61	12		T117	14		T146	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T61	5		T156	8		T105	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T143	7		T117	12		T253	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T36	3		T73	6		T38	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T161	13		T235	9		T241	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T2	1		T12	13		T62	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	4		T229	3		T208	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	1		T62	11		T143	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	13		T61	13		T188	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T179	4		T197	11		T204	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T208	7		T108	20		T252	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T289	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T257	1		T287	13		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T188	1		T99	1		T278	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T245	4		T260	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T55	7		T288	16		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T13	1		T43	1		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T51	23		T188	1		T38	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	1		T15	9		T149	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	2		T228	1		T233	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T152	1		T36	11		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T47	2		T116	1		T38	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T144	13		T37	15		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	17		T42	1		T233	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T42	1		T43	2		T144	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T37	5		T117	13		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	3		T38	17		T234	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T61	12		T146	1		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T12	15		T61	7		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T143	1		T117	10		T253	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T1	1		T2	3		T62	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T13	1		T152	1		T150	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	1		T14	1		T62	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1529	1			T3	1		T5	1		T10	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17494	1			T2	104		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T257	5		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T188	19		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T245	3		T260	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T55	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T13	9		T145	11		T146	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T51	10		T188	11		T234	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	16		T228	7		T154	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T228	14		T260	9		T275	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T143	12		T145	9		T52	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T47	10		T38	11		T109	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T37	13		T179	9		T245	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T233	4		T107	8		T203	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T234	8		T155	12		T58	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T117	14		T248	9		T166	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T38	14		T234	8		T105	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T61	12		T146	4		T241	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	13		T61	5		T36	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T143	7		T117	12		T253	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T2	1		T62	15		T73	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	4		T229	3		T148	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T14	1		T62	11		T143	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1311	1			T5	12		T10	30		T11	41

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

auto[0]

4196

1

T2

1

T5

12

T10

30