Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26640

1

T1

2

T2

108

T3

21

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22891

1

T2

108

T3

3

T5

13

auto[ADC_CTRL_FILTER_COND_OUT]

3749

1

T1

2

T3

18

T12

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20618

1

T1

2

T2

108

T3

3

auto[1]

6022

1

T3

18

T5

13

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22640

1

T1

2

T2

105

T3

3

auto[1]

4000

1

T2

3

T3

18

T12

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	654	1			T6	1		T42	1		T44	1
values[0]	3	1			T103	1		T227	1		T187	1
values[1]	765	1			T1	1		T61	37		T152	1
values[2]	2755	1			T5	13		T10	32		T11	44
values[3]	814	1			T13	5		T36	4		T117	27
values[4]	714	1			T12	2		T13	17		T14	27
values[5]	621	1			T3	1		T15	9		T42	1
values[6]	641	1			T12	28		T36	11		T47	4
values[7]	732	1			T1	1		T3	3		T43	1
values[8]	863	1			T2	4		T3	17		T13	10
values[9]	987	1			T62	16		T42	1		T150	5
minimum	17091	1			T2	104		T6	113		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	753	1			T1	1		T61	37		T152	2
values[1]	2875	1			T5	13		T10	32		T11	44
values[2]	798	1			T12	2		T13	22		T152	1
values[3]	717	1			T14	27		T15	9		T62	12
values[4]	633	1			T3	1		T12	28		T36	11
values[5]	587	1			T3	3		T47	4		T149	7
values[6]	808	1			T1	1		T13	10		T43	1
values[7]	833	1			T2	4		T3	17		T61	24
values[8]	868	1			T42	2		T47	8		T150	5
values[9]	192	1			T62	16		T143	25		T155	29
minimum	17576	1			T2	104		T6	114		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

4196

1

T2

1

T5

12

T10

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T61	20		T152	1		T144	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	1		T152	1		T116	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1550	1			T5	13		T10	32		T11	44
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T43	1		T47	1		T233	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T12	1		T13	22		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T152	1		T36	4		T146	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T62	12		T151	1		T53	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T14	16		T15	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T246	1		T54	6		T55	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	1		T12	14		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T3	1		T47	4		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T37	15		T120	10		T53	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T43	1		T146	1		T154	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	1		T13	10		T73	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T2	3		T61	13		T229	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T3	1		T51	18		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T47	8		T208	8		T235	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T42	2		T150	1		T117	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T62	16		T193	1		T290	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T143	13		T155	14		T241	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17378	1			T2	102		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T43	1		T233	1		T291	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T61	17		T144	12		T145	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T116	1		T145	8		T162	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T153	8		T49	6		T73	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T233	4		T235	8		T236	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	1		T38	9		T110	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T161	2		T108	2		T253	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T234	8		T292	5		T32	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	11		T15	8		T144	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T246	4		T54	2		T59	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	14		T36	10		T143	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T3	2		T149	6		T144	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T37	18		T53	1		T155	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T54	2		T235	5		T234	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T73	1		T237	14		T248	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	1		T61	11		T229	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	16		T51	15		T246	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T208	5		T235	9		T57	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T150	4		T117	3		T196	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T184	14		T293	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T143	12		T155	15		T241	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	2		T37	3		T51	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T291	1		T285	9		T243	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	476	1			T6	1		T44	1		T45	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T42	1		T196	1		T99	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T187	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T103	1		T227	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T61	20		T144	1		T188	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	1		T152	1		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1526	1			T5	13		T10	32		T11	44
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T43	1		T47	1		T233	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	5		T117	15		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T36	4		T161	14		T54	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	1		T13	17		T62	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T14	16		T152	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T54	6		T55	1		T59	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	1		T15	1		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	4		T149	1		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T12	14		T36	1		T37	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	1		T43	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	1		T120	10		T179	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T2	3		T61	13		T38	27
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T3	1		T13	10		T73	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T62	16		T229	4		T146	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T42	1		T150	1		T143	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16960	1			T2	102		T6	113		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T235	9		T231	11		T294	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T196	4		T241	13		T192	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T61	17		T144	12		T145	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T116	1		T145	8		T162	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T153	8		T49	6		T73	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T233	4		T235	8		T269	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T117	12		T38	9		T110	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T161	2		T108	2		T253	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T12	1		T234	8		T275	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	11		T144	12		T173	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T54	2		T59	1		T60	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T15	8		T143	17		T117	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T149	6		T144	12		T246	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	14		T36	10		T37	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	2		T54	2		T235	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T156	10		T237	14		T241	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T2	1		T61	11		T38	26
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	16		T73	1		T51	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T229	4		T208	5		T97	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T150	4		T143	12		T117	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	2		T37	3		T51	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T61	19		T152	1		T144	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T1	1		T152	1		T116	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T5	1		T10	2		T11	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T43	1		T47	1		T233	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	2		T13	2		T38	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T152	1		T36	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T62	1		T151	1		T53	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T14	13		T15	9		T144	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T246	5		T54	4		T55	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T3	1		T12	15		T36	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T3	3		T47	1		T149	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T37	20		T120	1		T53	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T43	1		T146	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	1		T13	1		T73	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	3		T61	12		T229	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T3	17		T51	23		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T47	1		T208	6		T235	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T42	2		T150	5		T117	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T62	1		T193	1		T290	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T143	13		T155	16		T241	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17532	1			T2	104		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T43	1		T233	1		T291	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T61	18		T188	19		T145	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T145	11		T162	3		T174	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T5	12		T10	30		T11	41
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T233	4		T148	10		T235	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	20		T110	7		T234	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T36	3		T146	4		T161	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T62	11		T234	9		T176	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T14	14		T143	7		T188	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T54	4		T59	2		T256	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	13		T143	12		T117	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T47	3		T109	8		T245	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T37	13		T120	9		T179	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T154	3		T108	12		T235	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	9		T237	15		T248	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	1		T61	12		T229	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T51	10		T55	4		T277	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T47	7		T208	7		T245	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T117	1		T237	10		T241	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T62	15		T290	10		T184	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T143	12		T155	13		T241	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T295	4		T296	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T285	7		T243	12		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	442	1			T6	1		T44	1		T45	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T42	1		T196	5		T99	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T187	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T103	1		T227	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T61	19		T144	13		T188	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	1		T152	1		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T5	1		T10	2		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T43	1		T47	1		T233	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	1		T117	13		T38	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T36	1		T161	3		T54	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T12	2		T13	1		T62	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T14	13		T152	1		T144	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T54	4		T55	1		T59	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	1		T15	9		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T47	1		T149	7		T144	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T12	15		T36	11		T37	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	3		T43	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	1		T120	1		T179	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	3		T61	12		T38	28
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T3	17		T13	1		T73	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T62	1		T229	5		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T42	1		T150	5		T143	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17091	1			T2	104		T6	113		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T47	7		T230	10		T231	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T241	13		T192	8		T297	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T61	18		T188	19		T145	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T145	11		T162	3		T174	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T5	12		T10	30		T11	41
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T233	4		T148	10		T235	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	4		T117	14		T110	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T36	3		T161	13		T108	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	16		T62	11		T234	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	14		T188	11		T146	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T54	4		T59	2		T256	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T143	19		T117	12		T228	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T47	3		T109	8		T245	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	13		T37	13		T148	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T154	3		T235	9		T234	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T120	9		T179	4		T156	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	1		T61	12		T38	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	9		T51	10		T55	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T62	15		T229	3		T146	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T143	12		T117	1		T155	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

auto[0]

4196

1

T2

1

T5

12

T10

30