Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26640

1

T1

2

T2

108

T3

21

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23127

1

T2

104

T3

17

T5

13

auto[ADC_CTRL_FILTER_COND_OUT]

3513

1

T1

2

T2

4

T3

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20875

1

T1

1

T2

104

T3

1

auto[1]

5765

1

T1

1

T2

4

T3

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22640

1

T1

2

T2

105

T3

3

auto[1]

4000

1

T2

3

T3

18

T12

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	15	1			T152	1		T307	1		T308	10
values[0]	24	1			T309	7		T34	1		T310	1
values[1]	616	1			T42	1		T117	5		T188	12
values[2]	580	1			T12	2		T43	1		T144	13
values[3]	663	1			T1	1		T2	4		T14	2
values[4]	673	1			T152	1		T36	11		T43	1
values[5]	730	1			T37	7		T116	1		T117	27
values[6]	650	1			T13	10		T152	1		T36	4
values[7]	744	1			T13	5		T61	37		T43	1
values[8]	806	1			T13	17		T62	28		T47	1
values[9]	3645	1			T1	1		T3	21		T5	13
minimum	17494	1			T2	104		T6	114		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	713	1			T12	2		T117	5		T188	12
values[1]	542	1			T1	1		T42	1		T43	1
values[2]	680	1			T2	4		T14	2		T36	11
values[3]	703	1			T152	1		T43	1		T51	33
values[4]	815	1			T42	1		T37	7		T117	27
values[5]	603	1			T13	10		T61	37		T152	1
values[6]	2957	1			T5	13		T10	32		T11	44
values[7]	708	1			T61	24		T62	12		T144	13
values[8]	1136	1			T1	1		T12	28		T14	25
values[9]	224	1			T3	21		T145	20		T53	3
minimum	17559	1			T2	104		T6	114		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

4196

1

T2

1

T5

12

T10

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	1		T117	2		T246	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T188	12		T38	1		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T42	1		T146	13		T162	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T1	1		T43	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T14	2		T36	1		T73	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T2	3		T117	13		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T152	1		T116	1		T120	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T43	1		T51	18		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T42	1		T37	1		T38	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T117	15		T233	5		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	10		T61	6		T36	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T61	14		T152	1		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1542	1			T5	13		T10	32		T11	44
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	17		T62	16		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T62	12		T144	1		T143	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T61	13		T233	1		T232	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T14	14		T15	1		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	380	1			T1	1		T12	14		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T3	1		T145	12		T53	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T3	2		T39	11		T311	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17378	1			T2	102		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T38	12		T312	10		T313	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	1		T117	3		T246	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T38	9		T246	5		T155	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T162	3		T107	15		T110	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T144	12		T55	4		T236	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T36	10		T73	7		T229	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	1		T117	9		T38	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T234	8		T156	10		T97	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T51	15		T54	2		T169	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T37	6		T38	16		T235	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T117	12		T233	4		T179	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T61	6		T54	4		T196	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T61	11		T149	6		T191	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1045	1			T153	8		T49	6		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T144	12		T37	4		T161	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T144	12		T116	1		T208	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T61	11		T232	10		T57	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T14	11		T15	8		T73	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T12	14		T150	4		T143	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T3	16		T145	8		T53	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T3	2		T39	13		T311	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	2		T37	3		T51	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T38	10		T312	5		T313	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T307	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T152	1		T308	10		T286	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T309	3		T310	1		T304	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T34	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T42	1		T117	2		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T188	12		T38	13		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T12	1		T162	4		T107	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T43	1		T144	1		T173	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T14	2		T73	7		T146	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	1		T2	3		T117	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T152	1		T36	1		T120	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T43	1		T51	18		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T37	1		T116	1		T38	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T117	15		T147	1		T179	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	10		T36	4		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T152	1		T149	1		T228	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T13	5		T61	6		T143	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T61	14		T43	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T62	12		T47	1		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	17		T62	16		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1697	1			T3	1		T5	13		T10	32
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	462	1			T1	1		T3	2		T12	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T2	102		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T286	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T309	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T117	3		T246	4		T235	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T38	19		T246	5		T56	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	1		T162	3		T107	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T144	12		T173	11		T55	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T73	7		T173	1		T110	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T2	1		T117	9		T38	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T36	10		T229	4		T54	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T51	15		T241	15		T268	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T37	6		T38	16		T235	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T117	12		T179	11		T253	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T239	2		T241	13		T252	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T149	6		T233	4		T174	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T61	6		T143	12		T54	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T61	11		T156	10		T245	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T144	12		T116	1		T246	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T144	12		T150	4		T37	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1149	1			T3	16		T14	11		T15	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T3	2		T12	14		T61	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	2		T37	3		T51	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	2		T117	4		T246	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T188	1		T38	10		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T42	1		T146	1		T162	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T1	1		T43	1		T144	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	1		T36	11		T73	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	3		T117	10		T38	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T152	1		T116	1		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T43	1		T51	23		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T42	1		T37	7		T38	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T117	13		T233	5		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T13	1		T61	7		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T61	12		T152	1		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T5	1		T10	2		T11	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	1		T62	1		T144	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T62	1		T144	13		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T61	12		T233	1		T232	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T14	12		T15	9		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T1	1		T12	15		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T3	17		T145	9		T53	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T3	4		T39	14		T311	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17495	1			T2	104		T6	114		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T38	11		T312	11		T313	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T117	1		T235	9		T104	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T188	11		T148	2		T155	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T146	12		T162	3		T154	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T55	4		T252	1		T204	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T14	1		T73	6		T229	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	1		T117	12		T228	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T120	9		T148	12		T108	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T51	10		T54	4		T169	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T38	14		T235	12		T241	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T117	14		T233	4		T179	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	9		T61	5		T36	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T61	13		T228	14		T146	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1212	1			T5	12		T10	30		T11	41
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	16		T62	15		T161	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T62	11		T143	7		T208	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T61	12		T232	10		T204	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T14	13		T145	9		T208	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T12	13		T47	10		T143	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T145	11		T58	1		T273	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T39	10		T311	19		T314	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T304	14		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T38	11		T312	4		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T307	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T152	1		T308	1		T286	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T309	5		T310	1		T304	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T34	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T42	1		T117	4		T246	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T188	1		T38	21		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	2		T162	4		T107	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T43	1		T144	13		T173	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	1		T73	8		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T1	1		T2	3		T117	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T152	1		T36	11		T120	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T43	1		T51	23		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T37	7		T116	1		T38	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T117	13		T147	1		T179	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T13	1		T36	1		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T152	1		T149	7		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T13	1		T61	7		T143	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T61	12		T43	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T62	1		T47	1		T144	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	1		T62	1		T144	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1511	1			T3	17		T5	1		T10	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	408	1			T1	1		T3	4		T12	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17494	1			T2	104		T6	114		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T308	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T309	2		T304	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T117	1		T235	9		T104	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T188	11		T38	11		T148	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T162	3		T107	14		T203	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T173	8		T55	4		T155	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T14	1		T73	6		T146	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	1		T117	12		T228	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T120	9		T229	3		T148	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T51	10		T241	14		T268	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T38	14		T235	12		T276	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T117	14		T179	9		T253	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	9		T36	3		T241	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T228	14		T146	4		T233	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	4		T61	5		T143	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T61	13		T156	8		T245	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T62	11		T143	7		T234	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	16		T62	15		T161	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1335	1			T5	12		T10	30		T11	41
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T12	13		T61	12		T47	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22444

1

T1

2

T2

107

T3

21

auto[1]

auto[0]

4196

1

T2

1

T5

12

T10

30