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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.78 99.07 96.67 100.00 100.00 98.83 98.33 91.56


Total test records in report: 918
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T793 /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.4284521033 May 21 02:41:37 PM PDT 24 May 21 02:43:26 PM PDT 24 104337928032 ps
T794 /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.753535200 May 21 02:40:38 PM PDT 24 May 21 02:42:33 PM PDT 24 100127825256 ps
T795 /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2821472114 May 21 02:42:50 PM PDT 24 May 21 03:03:05 PM PDT 24 497674446839 ps
T796 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2134300029 May 21 02:11:31 PM PDT 24 May 21 02:11:35 PM PDT 24 510567637 ps
T797 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3393277032 May 21 02:11:50 PM PDT 24 May 21 02:11:54 PM PDT 24 437170294 ps
T74 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3672616379 May 21 02:11:27 PM PDT 24 May 21 02:11:51 PM PDT 24 8836671887 ps
T798 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1136055032 May 21 02:11:38 PM PDT 24 May 21 02:11:42 PM PDT 24 538325578 ps
T799 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1086464300 May 21 02:11:25 PM PDT 24 May 21 02:11:28 PM PDT 24 354773515 ps
T137 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3195805390 May 21 02:11:26 PM PDT 24 May 21 02:11:30 PM PDT 24 461274847 ps
T800 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.394889583 May 21 02:11:55 PM PDT 24 May 21 02:11:59 PM PDT 24 414864497 ps
T82 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1108823347 May 21 02:11:18 PM PDT 24 May 21 02:11:21 PM PDT 24 518443472 ps
T78 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.112880952 May 21 02:11:38 PM PDT 24 May 21 02:11:42 PM PDT 24 1065999747 ps
T85 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2745618222 May 21 02:11:48 PM PDT 24 May 21 02:11:52 PM PDT 24 874158226 ps
T138 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1266364743 May 21 02:11:22 PM PDT 24 May 21 02:11:25 PM PDT 24 301786260 ps
T86 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2497149346 May 21 02:11:40 PM PDT 24 May 21 02:11:46 PM PDT 24 467829303 ps
T70 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.33225235 May 21 02:11:23 PM PDT 24 May 21 02:11:27 PM PDT 24 4508358568 ps
T801 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2956263562 May 21 02:11:37 PM PDT 24 May 21 02:11:41 PM PDT 24 482236727 ps
T802 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3737702728 May 21 02:11:50 PM PDT 24 May 21 02:11:53 PM PDT 24 429608019 ps
T75 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3160599285 May 21 02:11:23 PM PDT 24 May 21 02:11:36 PM PDT 24 4448395894 ps
T76 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1023711779 May 21 02:11:28 PM PDT 24 May 21 02:11:33 PM PDT 24 4884644513 ps
T87 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1126354607 May 21 02:11:16 PM PDT 24 May 21 02:11:20 PM PDT 24 579084038 ps
T83 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3861792783 May 21 02:11:45 PM PDT 24 May 21 02:11:46 PM PDT 24 569263152 ps
T71 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1775556940 May 21 02:11:23 PM PDT 24 May 21 02:11:28 PM PDT 24 2369131519 ps
T72 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3241315947 May 21 02:11:21 PM PDT 24 May 21 02:11:27 PM PDT 24 5568046501 ps
T124 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3346266265 May 21 02:11:37 PM PDT 24 May 21 02:11:42 PM PDT 24 337869836 ps
T803 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1460945382 May 21 02:11:50 PM PDT 24 May 21 02:11:53 PM PDT 24 378051717 ps
T804 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1757142260 May 21 02:11:49 PM PDT 24 May 21 02:11:53 PM PDT 24 363878494 ps
T125 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2507890888 May 21 02:11:43 PM PDT 24 May 21 02:11:46 PM PDT 24 496069015 ps
T84 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3341978437 May 21 02:11:20 PM PDT 24 May 21 02:11:24 PM PDT 24 408723721 ps
T805 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.390369284 May 21 02:11:35 PM PDT 24 May 21 02:11:39 PM PDT 24 537600226 ps
T139 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3696143300 May 21 02:11:26 PM PDT 24 May 21 02:11:31 PM PDT 24 1992775043 ps
T142 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2615534446 May 21 02:11:14 PM PDT 24 May 21 02:11:18 PM PDT 24 621393206 ps
T806 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3206447786 May 21 02:11:51 PM PDT 24 May 21 02:11:54 PM PDT 24 354704928 ps
T140 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1010518834 May 21 02:11:37 PM PDT 24 May 21 02:11:41 PM PDT 24 549029683 ps
T89 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3368407630 May 21 02:11:27 PM PDT 24 May 21 02:11:30 PM PDT 24 447221808 ps
T807 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2225063223 May 21 02:11:54 PM PDT 24 May 21 02:11:58 PM PDT 24 505374137 ps
T808 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1704484338 May 21 02:11:41 PM PDT 24 May 21 02:11:45 PM PDT 24 466755385 ps
T809 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1619507374 May 21 02:11:50 PM PDT 24 May 21 02:11:55 PM PDT 24 610195821 ps
T810 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2226702354 May 21 02:11:53 PM PDT 24 May 21 02:11:56 PM PDT 24 322969394 ps
T811 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2797545819 May 21 02:11:24 PM PDT 24 May 21 02:11:27 PM PDT 24 430841635 ps
T812 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3365044257 May 21 02:11:34 PM PDT 24 May 21 02:11:37 PM PDT 24 299478316 ps
T813 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1674178354 May 21 02:11:48 PM PDT 24 May 21 02:11:51 PM PDT 24 419602018 ps
T141 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3054570481 May 21 02:11:38 PM PDT 24 May 21 02:11:43 PM PDT 24 2249043059 ps
T814 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2123455692 May 21 02:11:56 PM PDT 24 May 21 02:11:59 PM PDT 24 601972278 ps
T815 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3879400287 May 21 02:11:54 PM PDT 24 May 21 02:11:57 PM PDT 24 431826981 ps
T90 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.345200118 May 21 02:11:47 PM PDT 24 May 21 02:11:52 PM PDT 24 466815257 ps
T816 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3984663062 May 21 02:11:21 PM PDT 24 May 21 02:11:25 PM PDT 24 529777510 ps
T126 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2914880265 May 21 02:11:44 PM PDT 24 May 21 02:11:46 PM PDT 24 549131017 ps
T341 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3534215759 May 21 02:11:50 PM PDT 24 May 21 02:12:00 PM PDT 24 4430245893 ps
T817 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1995536546 May 21 02:11:50 PM PDT 24 May 21 02:11:54 PM PDT 24 413466354 ps
T91 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1493646207 May 21 02:11:21 PM PDT 24 May 21 02:11:26 PM PDT 24 548866647 ps
T818 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4050445126 May 21 02:11:35 PM PDT 24 May 21 02:11:41 PM PDT 24 395467702 ps
T819 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1768173665 May 21 02:11:21 PM PDT 24 May 21 02:11:24 PM PDT 24 970873968 ps
T820 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2233083049 May 21 02:11:39 PM PDT 24 May 21 02:11:44 PM PDT 24 376228529 ps
T338 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.429708409 May 21 02:11:34 PM PDT 24 May 21 02:11:48 PM PDT 24 4253736394 ps
T821 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4112225051 May 21 02:11:14 PM PDT 24 May 21 02:11:18 PM PDT 24 432519165 ps
T127 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.790996326 May 21 02:11:24 PM PDT 24 May 21 02:12:10 PM PDT 24 12470417704 ps
T822 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1858589110 May 21 02:11:42 PM PDT 24 May 21 02:11:46 PM PDT 24 512051778 ps
T128 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1145106537 May 21 02:11:16 PM PDT 24 May 21 02:11:35 PM PDT 24 44975971183 ps
T823 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2853260388 May 21 02:11:16 PM PDT 24 May 21 02:11:20 PM PDT 24 503597013 ps
T824 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3551957824 May 21 02:11:50 PM PDT 24 May 21 02:11:54 PM PDT 24 442385194 ps
T825 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.151979317 May 21 02:11:47 PM PDT 24 May 21 02:11:50 PM PDT 24 2377588199 ps
T339 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2632931752 May 21 02:11:40 PM PDT 24 May 21 02:11:56 PM PDT 24 8463202016 ps
T826 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3828661059 May 21 02:11:33 PM PDT 24 May 21 02:11:35 PM PDT 24 473595077 ps
T827 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3996120992 May 21 02:11:24 PM PDT 24 May 21 02:12:12 PM PDT 24 26980607399 ps
T828 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.180923898 May 21 02:11:51 PM PDT 24 May 21 02:11:55 PM PDT 24 525389789 ps
T829 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.951603648 May 21 02:11:18 PM PDT 24 May 21 02:11:21 PM PDT 24 802389977 ps
T830 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.335330258 May 21 02:11:44 PM PDT 24 May 21 02:11:49 PM PDT 24 4436933668 ps
T831 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3214963521 May 21 02:11:37 PM PDT 24 May 21 02:11:43 PM PDT 24 558711405 ps
T832 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.607173144 May 21 02:11:29 PM PDT 24 May 21 02:11:37 PM PDT 24 4112500897 ps
T129 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.940616312 May 21 02:11:20 PM PDT 24 May 21 02:11:25 PM PDT 24 1111152831 ps
T833 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2833992113 May 21 02:11:27 PM PDT 24 May 21 02:11:32 PM PDT 24 477690503 ps
T834 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1971709462 May 21 02:11:21 PM PDT 24 May 21 02:11:25 PM PDT 24 792205177 ps
T835 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2784971957 May 21 02:11:29 PM PDT 24 May 21 02:11:32 PM PDT 24 474391665 ps
T836 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.692952349 May 21 02:11:45 PM PDT 24 May 21 02:11:56 PM PDT 24 4607123456 ps
T837 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2794345644 May 21 02:11:26 PM PDT 24 May 21 02:11:29 PM PDT 24 287935357 ps
T130 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2729582121 May 21 02:11:14 PM PDT 24 May 21 02:11:18 PM PDT 24 829022643 ps
T838 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2115094819 May 21 02:11:50 PM PDT 24 May 21 02:11:54 PM PDT 24 397185388 ps
T839 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.212007236 May 21 02:11:34 PM PDT 24 May 21 02:11:45 PM PDT 24 4239986536 ps
T840 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.270711524 May 21 02:11:15 PM PDT 24 May 21 02:11:18 PM PDT 24 569700601 ps
T841 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1967603934 May 21 02:11:26 PM PDT 24 May 21 02:11:30 PM PDT 24 479181878 ps
T842 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.696467074 May 21 02:11:35 PM PDT 24 May 21 02:11:39 PM PDT 24 416671462 ps
T843 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.424607308 May 21 02:11:29 PM PDT 24 May 21 02:11:31 PM PDT 24 514032699 ps
T844 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3445164897 May 21 02:11:50 PM PDT 24 May 21 02:11:54 PM PDT 24 343326234 ps
T845 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1003956886 May 21 02:11:24 PM PDT 24 May 21 02:11:27 PM PDT 24 413840794 ps
T846 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1529703639 May 21 02:11:50 PM PDT 24 May 21 02:11:54 PM PDT 24 501839265 ps
T847 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.343405591 May 21 02:11:14 PM PDT 24 May 21 02:11:25 PM PDT 24 8850560771 ps
T848 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3704696536 May 21 02:11:55 PM PDT 24 May 21 02:11:58 PM PDT 24 500856093 ps
T849 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1070638733 May 21 02:11:44 PM PDT 24 May 21 02:11:46 PM PDT 24 331799177 ps
T92 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.900629854 May 21 02:11:23 PM PDT 24 May 21 02:11:33 PM PDT 24 8171878264 ps
T850 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3602927318 May 21 02:11:48 PM PDT 24 May 21 02:11:51 PM PDT 24 505985800 ps
T851 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.476506335 May 21 02:11:33 PM PDT 24 May 21 02:11:36 PM PDT 24 348347420 ps
T852 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.4030418032 May 21 02:11:36 PM PDT 24 May 21 02:11:42 PM PDT 24 736110375 ps
T853 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.4160583721 May 21 02:11:44 PM PDT 24 May 21 02:11:56 PM PDT 24 4315892220 ps
T854 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2064294942 May 21 02:11:43 PM PDT 24 May 21 02:11:45 PM PDT 24 496791650 ps
T131 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1562150569 May 21 02:11:39 PM PDT 24 May 21 02:11:44 PM PDT 24 329896269 ps
T855 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3116983526 May 21 02:11:35 PM PDT 24 May 21 02:11:49 PM PDT 24 4626884983 ps
T856 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2493240146 May 21 02:11:38 PM PDT 24 May 21 02:11:42 PM PDT 24 503488847 ps
T857 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2290446784 May 21 02:11:51 PM PDT 24 May 21 02:11:54 PM PDT 24 430912294 ps
T858 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2447799331 May 21 02:11:49 PM PDT 24 May 21 02:11:53 PM PDT 24 429151316 ps
T342 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1911915802 May 21 02:11:35 PM PDT 24 May 21 02:11:44 PM PDT 24 4275664362 ps
T859 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.652107737 May 21 02:11:23 PM PDT 24 May 21 02:11:31 PM PDT 24 2419459061 ps
T132 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2712365673 May 21 02:11:36 PM PDT 24 May 21 02:11:40 PM PDT 24 531448956 ps
T860 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.855671024 May 21 02:11:21 PM PDT 24 May 21 02:11:25 PM PDT 24 512826193 ps
T861 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2156013189 May 21 02:11:33 PM PDT 24 May 21 02:11:40 PM PDT 24 8834872705 ps
T862 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3070715159 May 21 02:11:38 PM PDT 24 May 21 02:11:50 PM PDT 24 4286974175 ps
T863 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3406713771 May 21 02:11:50 PM PDT 24 May 21 02:11:54 PM PDT 24 474031676 ps
T864 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1115833779 May 21 02:11:51 PM PDT 24 May 21 02:11:55 PM PDT 24 285904600 ps
T865 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.844661600 May 21 02:11:51 PM PDT 24 May 21 02:11:55 PM PDT 24 305698906 ps
T866 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3355625464 May 21 02:11:34 PM PDT 24 May 21 02:11:38 PM PDT 24 494476835 ps
T867 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3076902927 May 21 02:11:31 PM PDT 24 May 21 02:11:35 PM PDT 24 609304615 ps
T868 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.169764635 May 21 02:11:19 PM PDT 24 May 21 02:11:21 PM PDT 24 380769476 ps
T133 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3554480020 May 21 02:11:24 PM PDT 24 May 21 02:11:28 PM PDT 24 533518613 ps
T869 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3836066356 May 21 02:11:49 PM PDT 24 May 21 02:11:53 PM PDT 24 529260748 ps
T870 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3033849145 May 21 02:11:50 PM PDT 24 May 21 02:11:54 PM PDT 24 560455394 ps
T871 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.951349476 May 21 02:11:20 PM PDT 24 May 21 02:11:25 PM PDT 24 886452024 ps
T872 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4117009416 May 21 02:11:30 PM PDT 24 May 21 02:11:33 PM PDT 24 566555671 ps
T136 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.727616247 May 21 02:11:46 PM PDT 24 May 21 02:11:48 PM PDT 24 330291731 ps
T873 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3624376694 May 21 02:11:35 PM PDT 24 May 21 02:11:39 PM PDT 24 358621337 ps
T874 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4186278711 May 21 02:11:27 PM PDT 24 May 21 02:11:31 PM PDT 24 347373386 ps
T875 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1327405185 May 21 02:11:51 PM PDT 24 May 21 02:11:55 PM PDT 24 518533192 ps
T876 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1257476470 May 21 02:11:21 PM PDT 24 May 21 02:11:25 PM PDT 24 653581670 ps
T877 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.276438254 May 21 02:11:54 PM PDT 24 May 21 02:11:59 PM PDT 24 4177832311 ps
T878 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.554805086 May 21 02:11:27 PM PDT 24 May 21 02:11:32 PM PDT 24 559491006 ps
T879 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2734659648 May 21 02:11:32 PM PDT 24 May 21 02:11:35 PM PDT 24 2026846318 ps
T880 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.364167803 May 21 02:11:33 PM PDT 24 May 21 02:11:37 PM PDT 24 596198354 ps
T881 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2172741655 May 21 02:11:30 PM PDT 24 May 21 02:11:51 PM PDT 24 7833113364 ps
T93 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1756582638 May 21 02:11:25 PM PDT 24 May 21 02:11:31 PM PDT 24 4288954812 ps
T882 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2501246419 May 21 02:11:27 PM PDT 24 May 21 02:11:31 PM PDT 24 541524821 ps
T883 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.4252262957 May 21 02:11:37 PM PDT 24 May 21 02:11:43 PM PDT 24 4298713966 ps
T884 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2940245542 May 21 02:11:40 PM PDT 24 May 21 02:11:44 PM PDT 24 629418691 ps
T134 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3853082816 May 21 02:11:23 PM PDT 24 May 21 02:11:31 PM PDT 24 26550225973 ps
T885 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.231169903 May 21 02:11:14 PM PDT 24 May 21 02:11:24 PM PDT 24 8475885087 ps
T886 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2957137637 May 21 02:11:25 PM PDT 24 May 21 02:11:28 PM PDT 24 444516069 ps
T887 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1048082915 May 21 02:11:31 PM PDT 24 May 21 02:11:49 PM PDT 24 4264645986 ps
T888 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3256710548 May 21 02:11:20 PM PDT 24 May 21 02:11:23 PM PDT 24 626395682 ps
T889 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.575161932 May 21 02:11:18 PM PDT 24 May 21 02:11:21 PM PDT 24 456572190 ps
T890 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1143063292 May 21 02:11:38 PM PDT 24 May 21 02:11:41 PM PDT 24 375390553 ps
T891 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1949490082 May 21 02:11:48 PM PDT 24 May 21 02:11:51 PM PDT 24 320738150 ps
T892 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1246514345 May 21 02:11:37 PM PDT 24 May 21 02:11:42 PM PDT 24 574522121 ps
T893 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1498620459 May 21 02:11:20 PM PDT 24 May 21 02:11:23 PM PDT 24 340349425 ps
T894 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3798824034 May 21 02:11:24 PM PDT 24 May 21 02:11:33 PM PDT 24 4687772656 ps
T895 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.293103912 May 21 02:11:32 PM PDT 24 May 21 02:11:40 PM PDT 24 2833751669 ps
T340 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.76461723 May 21 02:11:26 PM PDT 24 May 21 02:11:35 PM PDT 24 4096409138 ps
T896 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1471112999 May 21 02:11:47 PM PDT 24 May 21 02:11:53 PM PDT 24 4519633852 ps
T897 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3885478399 May 21 02:11:49 PM PDT 24 May 21 02:11:53 PM PDT 24 485975558 ps
T898 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2843191561 May 21 02:11:27 PM PDT 24 May 21 02:11:32 PM PDT 24 716145750 ps
T899 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.973807883 May 21 02:11:57 PM PDT 24 May 21 02:12:01 PM PDT 24 280446825 ps
T900 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.91459149 May 21 02:11:21 PM PDT 24 May 21 02:11:25 PM PDT 24 472732394 ps
T901 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3328915205 May 21 02:11:27 PM PDT 24 May 21 02:11:30 PM PDT 24 678295046 ps
T135 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2571707110 May 21 02:11:19 PM PDT 24 May 21 02:11:42 PM PDT 24 6031582424 ps
T902 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3921509986 May 21 02:11:37 PM PDT 24 May 21 02:11:58 PM PDT 24 8837297023 ps
T903 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1863461497 May 21 02:11:21 PM PDT 24 May 21 02:11:24 PM PDT 24 1026559830 ps
T904 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.555014328 May 21 02:11:34 PM PDT 24 May 21 02:11:41 PM PDT 24 4997803098 ps
T905 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3640937303 May 21 02:11:18 PM PDT 24 May 21 02:11:22 PM PDT 24 2147340790 ps
T906 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1340710020 May 21 02:11:51 PM PDT 24 May 21 02:11:55 PM PDT 24 401888326 ps
T907 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.940704841 May 21 02:11:41 PM PDT 24 May 21 02:11:46 PM PDT 24 5174163533 ps
T908 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2000015870 May 21 02:11:20 PM PDT 24 May 21 02:11:23 PM PDT 24 639497645 ps
T909 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.940497902 May 21 02:11:40 PM PDT 24 May 21 02:11:54 PM PDT 24 4586465619 ps
T910 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.403089561 May 21 02:11:45 PM PDT 24 May 21 02:11:47 PM PDT 24 390084745 ps
T911 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1347093175 May 21 02:11:54 PM PDT 24 May 21 02:11:57 PM PDT 24 294745109 ps
T912 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.4194948987 May 21 02:11:51 PM PDT 24 May 21 02:11:54 PM PDT 24 423062041 ps
T913 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3054272063 May 21 02:11:26 PM PDT 24 May 21 02:11:30 PM PDT 24 380954991 ps
T914 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2630659382 May 21 02:11:25 PM PDT 24 May 21 02:11:28 PM PDT 24 422902110 ps
T915 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1858141468 May 21 02:11:38 PM PDT 24 May 21 02:11:43 PM PDT 24 597534534 ps
T916 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3048944603 May 21 02:11:21 PM PDT 24 May 21 02:11:25 PM PDT 24 1034487879 ps
T917 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1236090335 May 21 02:11:39 PM PDT 24 May 21 02:11:43 PM PDT 24 290806853 ps
T918 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2173419595 May 21 02:11:30 PM PDT 24 May 21 02:11:34 PM PDT 24 345501387 ps

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2818731869
Short name T2
Test name
Test status
Simulation time 105688461283 ps
CPU time 41.44 seconds
Started May 21 02:40:53 PM PDT 24
Finished May 21 02:41:49 PM PDT 24
Peak memory 210184 kb
Host smart-42e89a29-90b0-4f87-bd4d-287968d348fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818731869 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2818731869
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3588508994
Short name T37
Test name
Test status
Simulation time 646359788430 ps
CPU time 703.44 seconds
Started May 21 02:40:52 PM PDT 24
Finished May 21 02:52:51 PM PDT 24
Peak memory 210356 kb
Host smart-e3b16e4b-e87a-4ed2-96dc-dc59c128a9b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588508994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3588508994
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.112691295
Short name T13
Test name
Test status
Simulation time 548169717147 ps
CPU time 310.55 seconds
Started May 21 02:40:38 PM PDT 24
Finished May 21 02:45:54 PM PDT 24
Peak memory 201864 kb
Host smart-02cc22d3-5614-4be0-a6de-a595d3cbc1ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112691295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.112691295
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3907608565
Short name T117
Test name
Test status
Simulation time 489958807524 ps
CPU time 1167.36 seconds
Started May 21 02:41:54 PM PDT 24
Finished May 21 03:01:26 PM PDT 24
Peak memory 201792 kb
Host smart-1efbe423-71e2-48b2-b2c3-1767efd2ad26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907608565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3907608565
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.514289893
Short name T61
Test name
Test status
Simulation time 528628580463 ps
CPU time 332.25 seconds
Started May 21 02:42:19 PM PDT 24
Finished May 21 02:47:53 PM PDT 24
Peak memory 201784 kb
Host smart-51830e3c-7ebb-4544-998f-afc1c4cf30b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514289893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.514289893
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.810970002
Short name T21
Test name
Test status
Simulation time 243340416563 ps
CPU time 530.86 seconds
Started May 21 02:43:08 PM PDT 24
Finished May 21 02:52:01 PM PDT 24
Peak memory 218664 kb
Host smart-8ef0e2e7-acbd-4719-a845-d1072b6be3f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810970002 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.810970002
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3773763928
Short name T234
Test name
Test status
Simulation time 606119795150 ps
CPU time 610.5 seconds
Started May 21 02:43:27 PM PDT 24
Finished May 21 02:53:40 PM PDT 24
Peak memory 201924 kb
Host smart-e0a8b797-dee1-4b80-9403-36b3ab6c50dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773763928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3773763928
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3709274000
Short name T3
Test name
Test status
Simulation time 497141392118 ps
CPU time 620.93 seconds
Started May 21 02:39:43 PM PDT 24
Finished May 21 02:50:24 PM PDT 24
Peak memory 201788 kb
Host smart-c9ddabd1-b9c6-4623-938e-554bce07e1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709274000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3709274000
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2110034471
Short name T38
Test name
Test status
Simulation time 688230412015 ps
CPU time 575.28 seconds
Started May 21 02:40:56 PM PDT 24
Finished May 21 02:50:47 PM PDT 24
Peak memory 201860 kb
Host smart-ebae8016-6387-435b-a7fe-964f8b314bdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110034471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2110034471
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.308567189
Short name T54
Test name
Test status
Simulation time 334414247335 ps
CPU time 143.3 seconds
Started May 21 02:46:10 PM PDT 24
Finished May 21 02:48:35 PM PDT 24
Peak memory 210156 kb
Host smart-bb596416-df3d-4df1-bf62-09a42b96497b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308567189 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.308567189
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1482800713
Short name T57
Test name
Test status
Simulation time 571238166114 ps
CPU time 166.48 seconds
Started May 21 02:45:40 PM PDT 24
Finished May 21 02:48:27 PM PDT 24
Peak memory 210360 kb
Host smart-dfeb2e7d-382a-487d-a19a-d55839698cb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482800713 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1482800713
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.31984920
Short name T252
Test name
Test status
Simulation time 543906470844 ps
CPU time 560.96 seconds
Started May 21 02:42:54 PM PDT 24
Finished May 21 02:52:18 PM PDT 24
Peak memory 201868 kb
Host smart-6cb80cb0-f61c-496c-bdae-e24d999b4b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31984920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.31984920
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.204751043
Short name T148
Test name
Test status
Simulation time 579962587248 ps
CPU time 347.43 seconds
Started May 21 02:41:27 PM PDT 24
Finished May 21 02:47:21 PM PDT 24
Peak memory 201816 kb
Host smart-be59d64d-ed6b-42b6-b2ea-a5acf3dbdfb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204751043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.204751043
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3375272737
Short name T241
Test name
Test status
Simulation time 545108753405 ps
CPU time 1280.88 seconds
Started May 21 02:46:02 PM PDT 24
Finished May 21 03:07:23 PM PDT 24
Peak memory 201840 kb
Host smart-f9c74f2f-3dd4-4093-ae74-6860c0718bc2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375272737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3375272737
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2006522246
Short name T119
Test name
Test status
Simulation time 535235187 ps
CPU time 1.28 seconds
Started May 21 02:39:42 PM PDT 24
Finished May 21 02:40:03 PM PDT 24
Peak memory 201576 kb
Host smart-506ba731-5fab-4dc7-87c9-ff74f175033a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006522246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2006522246
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1318664907
Short name T153
Test name
Test status
Simulation time 168644974608 ps
CPU time 387.16 seconds
Started May 21 02:42:27 PM PDT 24
Finished May 21 02:48:57 PM PDT 24
Peak memory 201836 kb
Host smart-dc7c024e-d0cb-4d0d-b91c-464b0454837c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318664907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1318664907
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2507890888
Short name T125
Test name
Test status
Simulation time 496069015 ps
CPU time 1.92 seconds
Started May 21 02:11:43 PM PDT 24
Finished May 21 02:11:46 PM PDT 24
Peak memory 201716 kb
Host smart-e865168d-6f51-42f6-ab93-8c5f34e822ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507890888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2507890888
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3672616379
Short name T74
Test name
Test status
Simulation time 8836671887 ps
CPU time 22.67 seconds
Started May 21 02:11:27 PM PDT 24
Finished May 21 02:11:51 PM PDT 24
Peak memory 201972 kb
Host smart-e932a7d8-7a1a-4817-8817-a0a93630ea27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672616379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3672616379
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3658551194
Short name T105
Test name
Test status
Simulation time 261513588621 ps
CPU time 473.37 seconds
Started May 21 02:42:13 PM PDT 24
Finished May 21 02:50:08 PM PDT 24
Peak memory 210456 kb
Host smart-9530f8d2-b9e6-456b-83e4-b95321a496eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658551194 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3658551194
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1158005951
Short name T107
Test name
Test status
Simulation time 351101302510 ps
CPU time 100.1 seconds
Started May 21 02:45:06 PM PDT 24
Finished May 21 02:46:47 PM PDT 24
Peak memory 201892 kb
Host smart-cc17677a-a212-4b96-86d2-ec8ae210d062
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158005951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1158005951
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.4152635801
Short name T208
Test name
Test status
Simulation time 420041530236 ps
CPU time 881.75 seconds
Started May 21 02:42:44 PM PDT 24
Finished May 21 02:57:29 PM PDT 24
Peak memory 201876 kb
Host smart-50cf6b9e-41ac-491a-903a-7182bd63199c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152635801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.4152635801
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.112880952
Short name T78
Test name
Test status
Simulation time 1065999747 ps
CPU time 1.49 seconds
Started May 21 02:11:38 PM PDT 24
Finished May 21 02:11:42 PM PDT 24
Peak memory 201924 kb
Host smart-29a7198c-3362-406f-9b8b-4d4b8b60b1c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112880952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.112880952
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3370584441
Short name T282
Test name
Test status
Simulation time 541273994600 ps
CPU time 259.84 seconds
Started May 21 02:40:38 PM PDT 24
Finished May 21 02:45:02 PM PDT 24
Peak memory 201908 kb
Host smart-40361e50-50d3-45bb-8a48-5079823f7db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370584441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3370584441
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2951803596
Short name T12
Test name
Test status
Simulation time 363815088999 ps
CPU time 87.57 seconds
Started May 21 02:44:25 PM PDT 24
Finished May 21 02:45:54 PM PDT 24
Peak memory 201872 kb
Host smart-4a0269ee-a372-4a1e-8eea-56866d39ed87
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951803596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2951803596
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.4157934798
Short name T259
Test name
Test status
Simulation time 545255966037 ps
CPU time 316.26 seconds
Started May 21 02:40:39 PM PDT 24
Finished May 21 02:46:01 PM PDT 24
Peak memory 201864 kb
Host smart-db8bd419-bed3-4180-b75b-ff4d8528a04e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157934798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.4157934798
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2152244259
Short name T160
Test name
Test status
Simulation time 490080569711 ps
CPU time 518.06 seconds
Started May 21 02:42:31 PM PDT 24
Finished May 21 02:51:12 PM PDT 24
Peak memory 201896 kb
Host smart-e718e879-1669-41a2-b27d-37a0371832c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152244259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2152244259
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3581899213
Short name T204
Test name
Test status
Simulation time 521149817416 ps
CPU time 394.59 seconds
Started May 21 02:41:08 PM PDT 24
Finished May 21 02:47:57 PM PDT 24
Peak memory 201888 kb
Host smart-2765055b-8df6-43cf-a889-9d65d3c0906b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581899213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3581899213
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1657482438
Short name T143
Test name
Test status
Simulation time 532982039984 ps
CPU time 1128.39 seconds
Started May 21 02:42:58 PM PDT 24
Finished May 21 03:01:50 PM PDT 24
Peak memory 201888 kb
Host smart-2e270f45-87ed-4bce-9c2f-20008e4efc20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657482438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1657482438
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.275772473
Short name T285
Test name
Test status
Simulation time 502360848777 ps
CPU time 551.86 seconds
Started May 21 02:43:07 PM PDT 24
Finished May 21 02:52:20 PM PDT 24
Peak memory 201856 kb
Host smart-d4894063-5e1f-4403-887a-8de4f5da8a37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275772473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.
275772473
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3673916997
Short name T80
Test name
Test status
Simulation time 4005099221 ps
CPU time 9.4 seconds
Started May 21 02:39:43 PM PDT 24
Finished May 21 02:40:12 PM PDT 24
Peak memory 217240 kb
Host smart-036a7eb6-5ab6-47d1-befd-d14dded7c6d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673916997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3673916997
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1866866582
Short name T47
Test name
Test status
Simulation time 549385380051 ps
CPU time 1166.6 seconds
Started May 21 02:43:49 PM PDT 24
Finished May 21 03:03:16 PM PDT 24
Peak memory 201776 kb
Host smart-5a16bb47-f643-4bcf-b710-f69b700c1c94
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866866582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1866866582
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.336602080
Short name T145
Test name
Test status
Simulation time 364037880340 ps
CPU time 229 seconds
Started May 21 02:42:37 PM PDT 24
Finished May 21 02:46:30 PM PDT 24
Peak memory 201868 kb
Host smart-eba87825-508f-48e9-a383-8e9be7800ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336602080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.336602080
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.59577466
Short name T51
Test name
Test status
Simulation time 179420937694 ps
CPU time 116.07 seconds
Started May 21 02:40:35 PM PDT 24
Finished May 21 02:42:34 PM PDT 24
Peak memory 210180 kb
Host smart-2b7a55cd-3045-479f-906f-9edf53f1f114
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59577466 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.59577466
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.20531452
Short name T184
Test name
Test status
Simulation time 341821163810 ps
CPU time 226.13 seconds
Started May 21 02:46:03 PM PDT 24
Finished May 21 02:49:50 PM PDT 24
Peak memory 201896 kb
Host smart-9f55e039-4bbc-4851-96fd-23e1ce937ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20531452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.20531452
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.2287761258
Short name T52
Test name
Test status
Simulation time 96416731160 ps
CPU time 82.34 seconds
Started May 21 02:40:56 PM PDT 24
Finished May 21 02:42:34 PM PDT 24
Peak memory 210572 kb
Host smart-da616c6a-feaa-4ed3-90c9-a1f5ea6de3d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287761258 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.2287761258
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.4246434107
Short name T331
Test name
Test status
Simulation time 489295050834 ps
CPU time 580.9 seconds
Started May 21 02:40:53 PM PDT 24
Finished May 21 02:50:49 PM PDT 24
Peak memory 201756 kb
Host smart-d4279d24-cbc6-4716-875e-82648854521d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246434107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.4246434107
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2220568039
Short name T245
Test name
Test status
Simulation time 542949128409 ps
CPU time 92.85 seconds
Started May 21 02:43:17 PM PDT 24
Finished May 21 02:44:52 PM PDT 24
Peak memory 201868 kb
Host smart-61e0aa35-0bd7-4946-93f0-59eb17f0042f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220568039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2220568039
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.941013370
Short name T235
Test name
Test status
Simulation time 528258141954 ps
CPU time 1252.29 seconds
Started May 21 02:45:38 PM PDT 24
Finished May 21 03:06:32 PM PDT 24
Peak memory 201788 kb
Host smart-179a2909-de57-412d-8841-60bccc812584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941013370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.941013370
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1073600844
Short name T181
Test name
Test status
Simulation time 370419725460 ps
CPU time 208.58 seconds
Started May 21 02:45:55 PM PDT 24
Finished May 21 02:49:26 PM PDT 24
Peak memory 201976 kb
Host smart-bbff1ad0-08da-4a81-9a13-f5494d1c9485
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073600844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1073600844
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3416141761
Short name T248
Test name
Test status
Simulation time 507209847882 ps
CPU time 1069.68 seconds
Started May 21 02:41:44 PM PDT 24
Finished May 21 02:59:37 PM PDT 24
Peak memory 201924 kb
Host smart-ccdbd664-62b3-4342-b218-00bb01149ece
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416141761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3416141761
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.423812832
Short name T108
Test name
Test status
Simulation time 1393495303502 ps
CPU time 1228.88 seconds
Started May 21 02:44:46 PM PDT 24
Finished May 21 03:05:16 PM PDT 24
Peak memory 210384 kb
Host smart-acc2ee2b-afa9-4566-8760-eb352f8b4dea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423812832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
423812832
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1834464337
Short name T242
Test name
Test status
Simulation time 430297117708 ps
CPU time 438.28 seconds
Started May 21 02:44:59 PM PDT 24
Finished May 21 02:52:19 PM PDT 24
Peak memory 201768 kb
Host smart-daeae091-ddeb-46ac-9ee4-7e4732c0e906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834464337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1834464337
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2937815336
Short name T257
Test name
Test status
Simulation time 580827662216 ps
CPU time 264.24 seconds
Started May 21 02:40:37 PM PDT 24
Finished May 21 02:45:04 PM PDT 24
Peak memory 202108 kb
Host smart-2652136f-9004-4f5b-aa95-1d306a888a7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937815336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2937815336
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2448211487
Short name T103
Test name
Test status
Simulation time 499619640343 ps
CPU time 298.51 seconds
Started May 21 02:39:48 PM PDT 24
Finished May 21 02:45:05 PM PDT 24
Peak memory 201824 kb
Host smart-a5c681b9-9abe-4702-9f9a-5e7b0d66176c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448211487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2448211487
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.2104591185
Short name T309
Test name
Test status
Simulation time 491716763497 ps
CPU time 98.11 seconds
Started May 21 02:42:31 PM PDT 24
Finished May 21 02:44:11 PM PDT 24
Peak memory 201860 kb
Host smart-60e635e3-ab60-434b-b454-d35d9b3ab248
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104591185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.2104591185
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1145106537
Short name T128
Test name
Test status
Simulation time 44975971183 ps
CPU time 17.74 seconds
Started May 21 02:11:16 PM PDT 24
Finished May 21 02:11:35 PM PDT 24
Peak memory 201944 kb
Host smart-6e87ddb7-488f-4f86-97d3-e24f728bf5b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145106537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1145106537
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2937885007
Short name T308
Test name
Test status
Simulation time 510371812841 ps
CPU time 595.75 seconds
Started May 21 02:42:44 PM PDT 24
Finished May 21 02:52:43 PM PDT 24
Peak memory 201924 kb
Host smart-915b1708-d5b7-46c1-b6d9-7d550aa45c37
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937885007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2937885007
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.689265572
Short name T229
Test name
Test status
Simulation time 159775018075 ps
CPU time 177.66 seconds
Started May 21 02:44:27 PM PDT 24
Finished May 21 02:47:26 PM PDT 24
Peak memory 201780 kb
Host smart-865edf7c-399a-4b03-a54d-540e67c1b1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689265572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.689265572
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3801065748
Short name T55
Test name
Test status
Simulation time 378173865532 ps
CPU time 173.08 seconds
Started May 21 02:40:31 PM PDT 24
Finished May 21 02:43:27 PM PDT 24
Peak memory 210188 kb
Host smart-20c3f8cf-b416-4211-8b46-de23bff87018
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801065748 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3801065748
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3292516247
Short name T303
Test name
Test status
Simulation time 487983283975 ps
CPU time 476.01 seconds
Started May 21 02:40:50 PM PDT 24
Finished May 21 02:48:59 PM PDT 24
Peak memory 202208 kb
Host smart-1fcf8991-f230-4bf7-be27-6cb81cb57f1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292516247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3292516247
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2782942721
Short name T290
Test name
Test status
Simulation time 552398458790 ps
CPU time 1250.68 seconds
Started May 21 02:44:29 PM PDT 24
Finished May 21 03:05:22 PM PDT 24
Peak memory 201868 kb
Host smart-6e0187b1-dedf-4d18-9b99-bede920634b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782942721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2782942721
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4050445126
Short name T818
Test name
Test status
Simulation time 395467702 ps
CPU time 3.55 seconds
Started May 21 02:11:35 PM PDT 24
Finished May 21 02:11:41 PM PDT 24
Peak memory 201948 kb
Host smart-3baaa85e-2433-4d2d-a9c9-2c7f9b9a01ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050445126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.4050445126
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3331885415
Short name T162
Test name
Test status
Simulation time 162360451164 ps
CPU time 47.19 seconds
Started May 21 02:39:42 PM PDT 24
Finished May 21 02:40:49 PM PDT 24
Peak memory 201816 kb
Host smart-18a6897c-362d-46e9-99bf-f9a851481b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331885415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3331885415
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.971890440
Short name T330
Test name
Test status
Simulation time 416207586059 ps
CPU time 168.27 seconds
Started May 21 02:39:44 PM PDT 24
Finished May 21 02:42:52 PM PDT 24
Peak memory 210544 kb
Host smart-d7004972-e367-4d22-a978-2dc4e67427f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971890440 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.971890440
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3444510170
Short name T273
Test name
Test status
Simulation time 380493140767 ps
CPU time 890.46 seconds
Started May 21 02:41:12 PM PDT 24
Finished May 21 02:56:15 PM PDT 24
Peak memory 201928 kb
Host smart-3716c632-ea20-4e4a-92c2-5108c5cd59f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444510170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3444510170
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3925973594
Short name T188
Test name
Test status
Simulation time 363607510558 ps
CPU time 710.07 seconds
Started May 21 02:42:13 PM PDT 24
Finished May 21 02:54:05 PM PDT 24
Peak memory 201852 kb
Host smart-45933248-be52-4cb3-94bb-7a1704680933
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925973594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3925973594
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2003845484
Short name T34
Test name
Test status
Simulation time 494026154220 ps
CPU time 301.87 seconds
Started May 21 02:42:27 PM PDT 24
Finished May 21 02:47:32 PM PDT 24
Peak memory 201800 kb
Host smart-ac9066d2-d93c-40c3-b95f-327cb87ab903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003845484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2003845484
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3118778834
Short name T185
Test name
Test status
Simulation time 524844962299 ps
CPU time 340.47 seconds
Started May 21 02:40:08 PM PDT 24
Finished May 21 02:45:58 PM PDT 24
Peak memory 201844 kb
Host smart-3ff760ef-ee89-4afb-af19-1391bae05a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118778834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3118778834
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.152947417
Short name T65
Test name
Test status
Simulation time 112687301775 ps
CPU time 642.18 seconds
Started May 21 02:46:12 PM PDT 24
Finished May 21 02:56:57 PM PDT 24
Peak memory 202180 kb
Host smart-daf220a4-0759-4493-8fa5-c6719bcc1d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152947417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.152947417
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.906741066
Short name T261
Test name
Test status
Simulation time 340770708073 ps
CPU time 427.47 seconds
Started May 21 02:41:08 PM PDT 24
Finished May 21 02:48:29 PM PDT 24
Peak memory 201836 kb
Host smart-60dc434b-1424-487a-bdcc-670cdc30b917
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906741066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.906741066
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.4122837641
Short name T240
Test name
Test status
Simulation time 510487382241 ps
CPU time 840.39 seconds
Started May 21 02:41:03 PM PDT 24
Finished May 21 02:55:18 PM PDT 24
Peak memory 201944 kb
Host smart-01964557-6090-41b2-8cee-b475dbb9f252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122837641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.4122837641
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1266282149
Short name T249
Test name
Test status
Simulation time 38807683269 ps
CPU time 115.71 seconds
Started May 21 02:42:28 PM PDT 24
Finished May 21 02:44:26 PM PDT 24
Peak memory 210480 kb
Host smart-1b654fa7-6c1a-41d7-bf90-fcd519b92027
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266282149 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1266282149
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2949060701
Short name T177
Test name
Test status
Simulation time 322816813358 ps
CPU time 726.68 seconds
Started May 21 02:44:41 PM PDT 24
Finished May 21 02:56:49 PM PDT 24
Peak memory 201872 kb
Host smart-a6a2a8ea-0323-4a38-bf7f-15d39b414b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949060701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2949060701
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1704854337
Short name T349
Test name
Test status
Simulation time 604716064340 ps
CPU time 813.66 seconds
Started May 21 02:40:51 PM PDT 24
Finished May 21 02:54:39 PM PDT 24
Peak memory 201896 kb
Host smart-e482daea-817d-4790-9b3c-d85808d31da2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704854337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1704854337
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3603628052
Short name T217
Test name
Test status
Simulation time 143326480907 ps
CPU time 758.41 seconds
Started May 21 02:40:52 PM PDT 24
Finished May 21 02:53:46 PM PDT 24
Peak memory 202100 kb
Host smart-582932f2-1b30-4cda-8d9e-d105de3d3fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603628052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3603628052
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3049211298
Short name T315
Test name
Test status
Simulation time 493874653046 ps
CPU time 1048.88 seconds
Started May 21 02:41:40 PM PDT 24
Finished May 21 02:59:11 PM PDT 24
Peak memory 201952 kb
Host smart-7c319f22-aea7-411d-b674-b99e2f6c21f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049211298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3049211298
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.2473209023
Short name T253
Test name
Test status
Simulation time 177810365765 ps
CPU time 83.69 seconds
Started May 21 02:42:27 PM PDT 24
Finished May 21 02:43:53 PM PDT 24
Peak memory 201876 kb
Host smart-be658baf-2fa9-4b61-aed2-aa94451c540b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473209023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.2473209023
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.4284627435
Short name T187
Test name
Test status
Simulation time 161566905308 ps
CPU time 372.16 seconds
Started May 21 02:43:44 PM PDT 24
Finished May 21 02:49:58 PM PDT 24
Peak memory 201928 kb
Host smart-67de47e5-7354-40f6-b3f7-d11513ffc516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284627435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.4284627435
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.4010165331
Short name T272
Test name
Test status
Simulation time 336182885818 ps
CPU time 176.17 seconds
Started May 21 02:43:51 PM PDT 24
Finished May 21 02:46:49 PM PDT 24
Peak memory 201876 kb
Host smart-417ee87c-fff9-45b4-a72b-3ba676c980ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010165331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.4010165331
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1650297500
Short name T221
Test name
Test status
Simulation time 138274415588 ps
CPU time 710.24 seconds
Started May 21 02:44:10 PM PDT 24
Finished May 21 02:56:02 PM PDT 24
Peak memory 202260 kb
Host smart-d0219caf-a584-4497-81de-59f11b1e76d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650297500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1650297500
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.769492505
Short name T256
Test name
Test status
Simulation time 335062933116 ps
CPU time 115.91 seconds
Started May 21 02:45:21 PM PDT 24
Finished May 21 02:47:18 PM PDT 24
Peak memory 201812 kb
Host smart-7795b405-07ac-450f-a8f9-f7219aa365f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769492505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.769492505
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1336545865
Short name T307
Test name
Test status
Simulation time 330474315040 ps
CPU time 396.29 seconds
Started May 21 02:45:56 PM PDT 24
Finished May 21 02:52:35 PM PDT 24
Peak memory 201768 kb
Host smart-7f3df823-77f7-4c11-892d-efe65cec88ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336545865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1336545865
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.900629854
Short name T92
Test name
Test status
Simulation time 8171878264 ps
CPU time 7.95 seconds
Started May 21 02:11:23 PM PDT 24
Finished May 21 02:11:33 PM PDT 24
Peak memory 201972 kb
Host smart-3d5adcab-4deb-4dd4-ae82-cf6d6c223aa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900629854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.900629854
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.429708409
Short name T338
Test name
Test status
Simulation time 4253736394 ps
CPU time 11.35 seconds
Started May 21 02:11:34 PM PDT 24
Finished May 21 02:11:48 PM PDT 24
Peak memory 201948 kb
Host smart-bdc9afaa-3166-46a3-b55e-295d7b030d84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429708409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.429708409
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2108687779
Short name T295
Test name
Test status
Simulation time 255016816600 ps
CPU time 158.33 seconds
Started May 21 02:39:42 PM PDT 24
Finished May 21 02:42:40 PM PDT 24
Peak memory 201852 kb
Host smart-a22aad2d-4f01-4801-b250-16350b16147d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108687779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2108687779
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.490236650
Short name T345
Test name
Test status
Simulation time 300585729525 ps
CPU time 635.06 seconds
Started May 21 02:39:47 PM PDT 24
Finished May 21 02:50:41 PM PDT 24
Peak memory 210460 kb
Host smart-32b1600b-e47a-4a85-9c87-8136188b396c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490236650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.490236650
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.2566807801
Short name T224
Test name
Test status
Simulation time 418838049309 ps
CPU time 1227.98 seconds
Started May 21 02:40:49 PM PDT 24
Finished May 21 03:01:31 PM PDT 24
Peak memory 210428 kb
Host smart-dd88e55c-eee2-4e61-b180-3c32246e6303
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566807801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.2566807801
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1653054645
Short name T304
Test name
Test status
Simulation time 562602124744 ps
CPU time 1351.15 seconds
Started May 21 02:40:47 PM PDT 24
Finished May 21 03:03:31 PM PDT 24
Peak memory 201936 kb
Host smart-30a990ba-fa4f-440c-8fe1-1fec6342463b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653054645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1653054645
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.455800389
Short name T212
Test name
Test status
Simulation time 87626653124 ps
CPU time 508.84 seconds
Started May 21 02:40:44 PM PDT 24
Finished May 21 02:49:20 PM PDT 24
Peak memory 202128 kb
Host smart-6f9cd67d-0ada-4fa6-a062-4eca8be3e602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455800389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.455800389
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2557523516
Short name T206
Test name
Test status
Simulation time 84337980493 ps
CPU time 315.81 seconds
Started May 21 02:40:53 PM PDT 24
Finished May 21 02:46:25 PM PDT 24
Peak memory 202180 kb
Host smart-a775dc45-6582-464d-b499-04f525847a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557523516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2557523516
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.596826691
Short name T6
Test name
Test status
Simulation time 73242278415 ps
CPU time 406.5 seconds
Started May 21 02:41:00 PM PDT 24
Finished May 21 02:48:02 PM PDT 24
Peak memory 202160 kb
Host smart-52a29f00-60f8-46ef-bde5-8cdcfa63ec05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596826691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.596826691
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2473413980
Short name T289
Test name
Test status
Simulation time 115501871421 ps
CPU time 151.12 seconds
Started May 21 02:40:56 PM PDT 24
Finished May 21 02:43:44 PM PDT 24
Peak memory 218004 kb
Host smart-17d8ec79-9e4b-48ed-974a-ab856c544d35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473413980 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2473413980
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1314937893
Short name T263
Test name
Test status
Simulation time 199940309784 ps
CPU time 432.4 seconds
Started May 21 02:39:56 PM PDT 24
Finished May 21 02:47:23 PM PDT 24
Peak memory 201872 kb
Host smart-8fbf0132-7118-4c07-88f2-836aac7c69f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314937893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1314937893
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.976240505
Short name T332
Test name
Test status
Simulation time 169677527060 ps
CPU time 412.37 seconds
Started May 21 02:41:24 PM PDT 24
Finished May 21 02:48:24 PM PDT 24
Peak memory 201864 kb
Host smart-010c6489-d330-44dd-a4cc-d2141bf6a9c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976240505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
976240505
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.888120432
Short name T110
Test name
Test status
Simulation time 268674587042 ps
CPU time 111.63 seconds
Started May 21 02:41:59 PM PDT 24
Finished May 21 02:43:54 PM PDT 24
Peak memory 201872 kb
Host smart-184414ad-6e73-4757-9089-c926d29e86f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888120432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.888120432
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3544844934
Short name T286
Test name
Test status
Simulation time 329522739059 ps
CPU time 766.4 seconds
Started May 21 02:42:14 PM PDT 24
Finished May 21 02:55:03 PM PDT 24
Peak memory 201804 kb
Host smart-1ee18879-db03-4354-9538-d7e59f9ed0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544844934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3544844934
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3914976823
Short name T287
Test name
Test status
Simulation time 331764484357 ps
CPU time 185.94 seconds
Started May 21 02:42:16 PM PDT 24
Finished May 21 02:45:24 PM PDT 24
Peak memory 201876 kb
Host smart-ddc1e8dd-f375-4cd8-9212-26eca8eb9f7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914976823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3914976823
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.315376870
Short name T195
Test name
Test status
Simulation time 535654248791 ps
CPU time 282.51 seconds
Started May 21 02:43:15 PM PDT 24
Finished May 21 02:48:00 PM PDT 24
Peak memory 201892 kb
Host smart-11d9801e-cf15-488a-9362-36117ab42c41
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315376870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.315376870
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2707116487
Short name T219
Test name
Test status
Simulation time 85961958152 ps
CPU time 149.68 seconds
Started May 21 02:43:38 PM PDT 24
Finished May 21 02:46:09 PM PDT 24
Peak memory 210460 kb
Host smart-fb3d3671-a3be-4a48-a216-c0f9495ff3f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707116487 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2707116487
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.89342149
Short name T347
Test name
Test status
Simulation time 82636838739 ps
CPU time 441.53 seconds
Started May 21 02:40:19 PM PDT 24
Finished May 21 02:47:43 PM PDT 24
Peak memory 202236 kb
Host smart-5b34bab1-cbc8-4cc8-90df-fc4b0b235b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89342149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.89342149
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.4242718373
Short name T196
Test name
Test status
Simulation time 498054117881 ps
CPU time 322.69 seconds
Started May 21 02:44:29 PM PDT 24
Finished May 21 02:49:54 PM PDT 24
Peak memory 201920 kb
Host smart-cb32a734-db68-4e37-a2dd-6bebd975c527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242718373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.4242718373
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.4281406792
Short name T179
Test name
Test status
Simulation time 348279231893 ps
CPU time 204.45 seconds
Started May 21 02:45:50 PM PDT 24
Finished May 21 02:49:16 PM PDT 24
Peak memory 201840 kb
Host smart-9cf66a36-205b-464e-919c-3a336cedd57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281406792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.4281406792
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.874160763
Short name T32
Test name
Test status
Simulation time 759043611744 ps
CPU time 892.53 seconds
Started May 21 02:40:39 PM PDT 24
Finished May 21 02:55:37 PM PDT 24
Peak memory 202100 kb
Host smart-d4e75474-36c1-4f5d-8c49-e4161cdab78f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874160763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.874160763
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.951603648
Short name T829
Test name
Test status
Simulation time 802389977 ps
CPU time 1.9 seconds
Started May 21 02:11:18 PM PDT 24
Finished May 21 02:11:21 PM PDT 24
Peak memory 201916 kb
Host smart-acdaca36-119c-48ba-a721-03d7313cfce5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951603648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.951603648
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2615534446
Short name T142
Test name
Test status
Simulation time 621393206 ps
CPU time 1.41 seconds
Started May 21 02:11:14 PM PDT 24
Finished May 21 02:11:18 PM PDT 24
Peak memory 201708 kb
Host smart-065518a8-a470-420a-b2d4-164e0ab8b2d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615534446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2615534446
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1108823347
Short name T82
Test name
Test status
Simulation time 518443472 ps
CPU time 2.04 seconds
Started May 21 02:11:18 PM PDT 24
Finished May 21 02:11:21 PM PDT 24
Peak memory 201728 kb
Host smart-7ad5b0a1-31e3-4ec0-ab77-834d63f19536
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108823347 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1108823347
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4112225051
Short name T821
Test name
Test status
Simulation time 432519165 ps
CPU time 1.08 seconds
Started May 21 02:11:14 PM PDT 24
Finished May 21 02:11:18 PM PDT 24
Peak memory 201728 kb
Host smart-40bcc894-a78a-4aa1-ac26-60ad434dc7d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112225051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.4112225051
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.575161932
Short name T889
Test name
Test status
Simulation time 456572190 ps
CPU time 1.42 seconds
Started May 21 02:11:18 PM PDT 24
Finished May 21 02:11:21 PM PDT 24
Peak memory 201728 kb
Host smart-aa6ed5df-5152-4d27-a535-9a219066383b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575161932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.575161932
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3640937303
Short name T905
Test name
Test status
Simulation time 2147340790 ps
CPU time 2.98 seconds
Started May 21 02:11:18 PM PDT 24
Finished May 21 02:11:22 PM PDT 24
Peak memory 201668 kb
Host smart-28bd290b-fd48-4d10-8168-ed7d40b5e265
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640937303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3640937303
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1126354607
Short name T87
Test name
Test status
Simulation time 579084038 ps
CPU time 2.25 seconds
Started May 21 02:11:16 PM PDT 24
Finished May 21 02:11:20 PM PDT 24
Peak memory 201980 kb
Host smart-f9ac1aa6-4011-4d82-83b7-6bf183e33c8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126354607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1126354607
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.231169903
Short name T885
Test name
Test status
Simulation time 8475885087 ps
CPU time 7.47 seconds
Started May 21 02:11:14 PM PDT 24
Finished May 21 02:11:24 PM PDT 24
Peak memory 201980 kb
Host smart-d884d359-811d-46b5-85af-8a313c5b779a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231169903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.231169903
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.940616312
Short name T129
Test name
Test status
Simulation time 1111152831 ps
CPU time 3.16 seconds
Started May 21 02:11:20 PM PDT 24
Finished May 21 02:11:25 PM PDT 24
Peak memory 201964 kb
Host smart-90ac6292-cb5e-49d6-a032-4f91ec42c11a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940616312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.940616312
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2571707110
Short name T135
Test name
Test status
Simulation time 6031582424 ps
CPU time 21.89 seconds
Started May 21 02:11:19 PM PDT 24
Finished May 21 02:11:42 PM PDT 24
Peak memory 201976 kb
Host smart-bb6bf669-d3f3-4351-b9e0-ff0205b5886c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571707110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2571707110
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2729582121
Short name T130
Test name
Test status
Simulation time 829022643 ps
CPU time 1.64 seconds
Started May 21 02:11:14 PM PDT 24
Finished May 21 02:11:18 PM PDT 24
Peak memory 201712 kb
Host smart-879c591f-af7b-45b3-b322-6f92ca818e43
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729582121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2729582121
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1003956886
Short name T845
Test name
Test status
Simulation time 413840794 ps
CPU time 1.8 seconds
Started May 21 02:11:24 PM PDT 24
Finished May 21 02:11:27 PM PDT 24
Peak memory 201748 kb
Host smart-a3e01a47-4855-4d9c-bef4-c77fe5ce5eed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003956886 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1003956886
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.270711524
Short name T840
Test name
Test status
Simulation time 569700601 ps
CPU time 1.1 seconds
Started May 21 02:11:15 PM PDT 24
Finished May 21 02:11:18 PM PDT 24
Peak memory 201744 kb
Host smart-dd67488d-2cd5-45e1-8960-30d0ab49a8f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270711524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.270711524
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.169764635
Short name T868
Test name
Test status
Simulation time 380769476 ps
CPU time 0.84 seconds
Started May 21 02:11:19 PM PDT 24
Finished May 21 02:11:21 PM PDT 24
Peak memory 201732 kb
Host smart-c1f484eb-334f-4799-9d5c-72791820f991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169764635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.169764635
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3241315947
Short name T72
Test name
Test status
Simulation time 5568046501 ps
CPU time 3.93 seconds
Started May 21 02:11:21 PM PDT 24
Finished May 21 02:11:27 PM PDT 24
Peak memory 201908 kb
Host smart-d53f7a17-956d-42bf-85a7-9db97f7d900e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241315947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3241315947
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2853260388
Short name T823
Test name
Test status
Simulation time 503597013 ps
CPU time 1.87 seconds
Started May 21 02:11:16 PM PDT 24
Finished May 21 02:11:20 PM PDT 24
Peak memory 201964 kb
Host smart-bf4a868f-f9c1-4029-a8a7-0cd60d8bb579
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853260388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2853260388
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.343405591
Short name T847
Test name
Test status
Simulation time 8850560771 ps
CPU time 8.11 seconds
Started May 21 02:11:14 PM PDT 24
Finished May 21 02:11:25 PM PDT 24
Peak memory 201984 kb
Host smart-6b88c432-c759-416b-9e55-42a7d2cdd946
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343405591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.343405591
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.476506335
Short name T851
Test name
Test status
Simulation time 348347420 ps
CPU time 1.17 seconds
Started May 21 02:11:33 PM PDT 24
Finished May 21 02:11:36 PM PDT 24
Peak memory 201764 kb
Host smart-488092f9-62a3-42b4-826e-4c509eb55728
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476506335 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.476506335
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1010518834
Short name T140
Test name
Test status
Simulation time 549029683 ps
CPU time 1.42 seconds
Started May 21 02:11:37 PM PDT 24
Finished May 21 02:11:41 PM PDT 24
Peak memory 201684 kb
Host smart-1eb252d0-8e19-4e6e-b40a-a53a0c6b82b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010518834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1010518834
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.696467074
Short name T842
Test name
Test status
Simulation time 416671462 ps
CPU time 1.52 seconds
Started May 21 02:11:35 PM PDT 24
Finished May 21 02:11:39 PM PDT 24
Peak memory 201632 kb
Host smart-5be78002-37fb-4710-b5e3-6723a8c652c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696467074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.696467074
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.555014328
Short name T904
Test name
Test status
Simulation time 4997803098 ps
CPU time 4.31 seconds
Started May 21 02:11:34 PM PDT 24
Finished May 21 02:11:41 PM PDT 24
Peak memory 201988 kb
Host smart-b228245b-105c-4c12-b50a-e0ddb297be5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555014328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.555014328
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1911915802
Short name T342
Test name
Test status
Simulation time 4275664362 ps
CPU time 6.47 seconds
Started May 21 02:11:35 PM PDT 24
Finished May 21 02:11:44 PM PDT 24
Peak memory 201940 kb
Host smart-2bcd7b84-65f5-4d75-8f9b-ca131ad359d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911915802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1911915802
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.364167803
Short name T880
Test name
Test status
Simulation time 596198354 ps
CPU time 2.27 seconds
Started May 21 02:11:33 PM PDT 24
Finished May 21 02:11:37 PM PDT 24
Peak memory 201736 kb
Host smart-545e6b8a-ce44-4ca7-b9a2-3d792652d9f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364167803 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.364167803
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3828661059
Short name T826
Test name
Test status
Simulation time 473595077 ps
CPU time 1.09 seconds
Started May 21 02:11:33 PM PDT 24
Finished May 21 02:11:35 PM PDT 24
Peak memory 201728 kb
Host smart-ee30b402-bc91-4b6d-9c3b-7121e71aca98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828661059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3828661059
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3365044257
Short name T812
Test name
Test status
Simulation time 299478316 ps
CPU time 1.37 seconds
Started May 21 02:11:34 PM PDT 24
Finished May 21 02:11:37 PM PDT 24
Peak memory 201676 kb
Host smart-b910d0ad-cbdb-4707-9254-8d806092d678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365044257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3365044257
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.212007236
Short name T839
Test name
Test status
Simulation time 4239986536 ps
CPU time 8.4 seconds
Started May 21 02:11:34 PM PDT 24
Finished May 21 02:11:45 PM PDT 24
Peak memory 201952 kb
Host smart-49ecb08d-46ef-4f82-9bec-0eb392f04c61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212007236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.212007236
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1246514345
Short name T892
Test name
Test status
Simulation time 574522121 ps
CPU time 1.51 seconds
Started May 21 02:11:37 PM PDT 24
Finished May 21 02:11:42 PM PDT 24
Peak memory 202036 kb
Host smart-96c4cd11-7a0e-4184-864f-2fd74a234de1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246514345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1246514345
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2156013189
Short name T861
Test name
Test status
Simulation time 8834872705 ps
CPU time 4.3 seconds
Started May 21 02:11:33 PM PDT 24
Finished May 21 02:11:40 PM PDT 24
Peak memory 201928 kb
Host smart-28943fe0-fb8d-4ae6-b401-a044bead8cae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156013189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2156013189
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3355625464
Short name T866
Test name
Test status
Simulation time 494476835 ps
CPU time 1.09 seconds
Started May 21 02:11:34 PM PDT 24
Finished May 21 02:11:38 PM PDT 24
Peak memory 201724 kb
Host smart-5aa0f103-b226-4340-bf67-03c157b62754
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355625464 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.3355625464
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3624376694
Short name T873
Test name
Test status
Simulation time 358621337 ps
CPU time 1.26 seconds
Started May 21 02:11:35 PM PDT 24
Finished May 21 02:11:39 PM PDT 24
Peak memory 201736 kb
Host smart-5b3953da-f1c8-4eed-86e2-c11c50465226
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624376694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3624376694
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1143063292
Short name T890
Test name
Test status
Simulation time 375390553 ps
CPU time 1.04 seconds
Started May 21 02:11:38 PM PDT 24
Finished May 21 02:11:41 PM PDT 24
Peak memory 201728 kb
Host smart-598eaa66-385f-48ba-8eaf-0e1e98c67af3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143063292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1143063292
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3116983526
Short name T855
Test name
Test status
Simulation time 4626884983 ps
CPU time 10.93 seconds
Started May 21 02:11:35 PM PDT 24
Finished May 21 02:11:49 PM PDT 24
Peak memory 201976 kb
Host smart-cc204bbc-0380-4e0e-9be6-5a0249226e63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116983526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3116983526
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1858141468
Short name T915
Test name
Test status
Simulation time 597534534 ps
CPU time 2.49 seconds
Started May 21 02:11:38 PM PDT 24
Finished May 21 02:11:43 PM PDT 24
Peak memory 201776 kb
Host smart-af39f8e8-d8aa-4431-ab02-94ba9eb5d672
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858141468 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1858141468
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2712365673
Short name T132
Test name
Test status
Simulation time 531448956 ps
CPU time 1.4 seconds
Started May 21 02:11:36 PM PDT 24
Finished May 21 02:11:40 PM PDT 24
Peak memory 201656 kb
Host smart-6ab2baac-3a0b-4681-839d-4190705db22f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712365673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2712365673
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2956263562
Short name T801
Test name
Test status
Simulation time 482236727 ps
CPU time 0.94 seconds
Started May 21 02:11:37 PM PDT 24
Finished May 21 02:11:41 PM PDT 24
Peak memory 201608 kb
Host smart-4b09b912-fa6b-4ed8-8d2c-47d637ac8caa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956263562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2956263562
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.4252262957
Short name T883
Test name
Test status
Simulation time 4298713966 ps
CPU time 3.86 seconds
Started May 21 02:11:37 PM PDT 24
Finished May 21 02:11:43 PM PDT 24
Peak memory 201984 kb
Host smart-198bbd84-270a-42f7-8362-6ad14da9ec22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252262957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.4252262957
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.4030418032
Short name T852
Test name
Test status
Simulation time 736110375 ps
CPU time 3.01 seconds
Started May 21 02:11:36 PM PDT 24
Finished May 21 02:11:42 PM PDT 24
Peak memory 210184 kb
Host smart-9087b9d0-bf89-43f7-9b0b-a4f879b8d2cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030418032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.4030418032
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3921509986
Short name T902
Test name
Test status
Simulation time 8837297023 ps
CPU time 18.32 seconds
Started May 21 02:11:37 PM PDT 24
Finished May 21 02:11:58 PM PDT 24
Peak memory 202012 kb
Host smart-f2901503-afa2-4b11-9469-6714033ebacb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921509986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3921509986
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2233083049
Short name T820
Test name
Test status
Simulation time 376228529 ps
CPU time 1.59 seconds
Started May 21 02:11:39 PM PDT 24
Finished May 21 02:11:44 PM PDT 24
Peak memory 201720 kb
Host smart-ca74c6a7-ada0-46e7-b2a6-7d8451cabe2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233083049 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2233083049
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3346266265
Short name T124
Test name
Test status
Simulation time 337869836 ps
CPU time 1.65 seconds
Started May 21 02:11:37 PM PDT 24
Finished May 21 02:11:42 PM PDT 24
Peak memory 201712 kb
Host smart-38a173d6-9b2e-49d9-ab35-23f74d959b69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346266265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.3346266265
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2493240146
Short name T856
Test name
Test status
Simulation time 503488847 ps
CPU time 1.79 seconds
Started May 21 02:11:38 PM PDT 24
Finished May 21 02:11:42 PM PDT 24
Peak memory 201692 kb
Host smart-dae0e3c5-56bc-4b34-82b5-e33f4ff79a8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493240146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2493240146
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3054570481
Short name T141
Test name
Test status
Simulation time 2249043059 ps
CPU time 2.58 seconds
Started May 21 02:11:38 PM PDT 24
Finished May 21 02:11:43 PM PDT 24
Peak memory 201772 kb
Host smart-d6844352-58a8-4f7e-b671-4e87f5317cbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054570481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3054570481
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3214963521
Short name T831
Test name
Test status
Simulation time 558711405 ps
CPU time 2.72 seconds
Started May 21 02:11:37 PM PDT 24
Finished May 21 02:11:43 PM PDT 24
Peak memory 201944 kb
Host smart-53453fb6-391d-4513-8a2a-10ff83595a17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214963521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3214963521
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.940497902
Short name T909
Test name
Test status
Simulation time 4586465619 ps
CPU time 11.51 seconds
Started May 21 02:11:40 PM PDT 24
Finished May 21 02:11:54 PM PDT 24
Peak memory 201924 kb
Host smart-264ae015-e60b-4399-be66-0e558355f34d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940497902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_in
tg_err.940497902
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2940245542
Short name T884
Test name
Test status
Simulation time 629418691 ps
CPU time 0.94 seconds
Started May 21 02:11:40 PM PDT 24
Finished May 21 02:11:44 PM PDT 24
Peak memory 201712 kb
Host smart-5798212d-5db6-4942-80e4-1b6f8e1ceaf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940245542 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2940245542
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1562150569
Short name T131
Test name
Test status
Simulation time 329896269 ps
CPU time 1.63 seconds
Started May 21 02:11:39 PM PDT 24
Finished May 21 02:11:44 PM PDT 24
Peak memory 201708 kb
Host smart-6a8b9ea0-5d12-46a9-b0e6-b8d0163af182
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562150569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1562150569
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1136055032
Short name T798
Test name
Test status
Simulation time 538325578 ps
CPU time 0.91 seconds
Started May 21 02:11:38 PM PDT 24
Finished May 21 02:11:42 PM PDT 24
Peak memory 201716 kb
Host smart-cf23b2ee-f9ec-4eaf-9955-8ff04aca24df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136055032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1136055032
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.940704841
Short name T907
Test name
Test status
Simulation time 5174163533 ps
CPU time 2.55 seconds
Started May 21 02:11:41 PM PDT 24
Finished May 21 02:11:46 PM PDT 24
Peak memory 201936 kb
Host smart-6ac8e24d-01cd-4c9d-a644-038dd77e0be0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940704841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.940704841
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1704484338
Short name T808
Test name
Test status
Simulation time 466755385 ps
CPU time 1.53 seconds
Started May 21 02:11:41 PM PDT 24
Finished May 21 02:11:45 PM PDT 24
Peak memory 201960 kb
Host smart-3dbcead9-cb59-4fa6-b0c5-0a4424eae844
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704484338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1704484338
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2632931752
Short name T339
Test name
Test status
Simulation time 8463202016 ps
CPU time 12.49 seconds
Started May 21 02:11:40 PM PDT 24
Finished May 21 02:11:56 PM PDT 24
Peak memory 201932 kb
Host smart-cb23a98b-6a10-4445-b63c-38e3e22fc54a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632931752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2632931752
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3861792783
Short name T83
Test name
Test status
Simulation time 569263152 ps
CPU time 1.07 seconds
Started May 21 02:11:45 PM PDT 24
Finished May 21 02:11:46 PM PDT 24
Peak memory 201740 kb
Host smart-682f99e4-b5cc-4ae1-a13a-6e4198c9a7bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861792783 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3861792783
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.727616247
Short name T136
Test name
Test status
Simulation time 330291731 ps
CPU time 0.94 seconds
Started May 21 02:11:46 PM PDT 24
Finished May 21 02:11:48 PM PDT 24
Peak memory 201700 kb
Host smart-120ec942-ede4-41f0-b8ba-c600e59d6e74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727616247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.727616247
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1236090335
Short name T917
Test name
Test status
Simulation time 290806853 ps
CPU time 1 seconds
Started May 21 02:11:39 PM PDT 24
Finished May 21 02:11:43 PM PDT 24
Peak memory 201696 kb
Host smart-d5d6eb64-e424-46f0-9ea3-f967d12ee141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236090335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1236090335
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.335330258
Short name T830
Test name
Test status
Simulation time 4436933668 ps
CPU time 3.41 seconds
Started May 21 02:11:44 PM PDT 24
Finished May 21 02:11:49 PM PDT 24
Peak memory 201980 kb
Host smart-086f4b82-66d4-46fa-9dc5-723d2b2571e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335330258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.335330258
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2497149346
Short name T86
Test name
Test status
Simulation time 467829303 ps
CPU time 2.81 seconds
Started May 21 02:11:40 PM PDT 24
Finished May 21 02:11:46 PM PDT 24
Peak memory 211228 kb
Host smart-cca1a495-d5e8-492d-9caf-e37e4190d942
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497149346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2497149346
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3070715159
Short name T862
Test name
Test status
Simulation time 4286974175 ps
CPU time 8.14 seconds
Started May 21 02:11:38 PM PDT 24
Finished May 21 02:11:50 PM PDT 24
Peak memory 201948 kb
Host smart-7f14fc81-5530-493f-9623-d8a465fdc71e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070715159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3070715159
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2064294942
Short name T854
Test name
Test status
Simulation time 496791650 ps
CPU time 1.16 seconds
Started May 21 02:11:43 PM PDT 24
Finished May 21 02:11:45 PM PDT 24
Peak memory 201744 kb
Host smart-396970fd-bed9-412f-94e6-8e0e6bd2058e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064294942 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2064294942
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2914880265
Short name T126
Test name
Test status
Simulation time 549131017 ps
CPU time 1.12 seconds
Started May 21 02:11:44 PM PDT 24
Finished May 21 02:11:46 PM PDT 24
Peak memory 201720 kb
Host smart-1243a082-5c40-4eb5-a916-d4a2780c834e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914880265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2914880265
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1070638733
Short name T849
Test name
Test status
Simulation time 331799177 ps
CPU time 1.05 seconds
Started May 21 02:11:44 PM PDT 24
Finished May 21 02:11:46 PM PDT 24
Peak memory 201644 kb
Host smart-7be0321c-490d-4397-8c94-9406b0f875e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070638733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1070638733
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.151979317
Short name T825
Test name
Test status
Simulation time 2377588199 ps
CPU time 1.51 seconds
Started May 21 02:11:47 PM PDT 24
Finished May 21 02:11:50 PM PDT 24
Peak memory 201768 kb
Host smart-e631d138-e2fd-408c-9a17-3686a2a394e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151979317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.151979317
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1674178354
Short name T813
Test name
Test status
Simulation time 419602018 ps
CPU time 1.93 seconds
Started May 21 02:11:48 PM PDT 24
Finished May 21 02:11:51 PM PDT 24
Peak memory 217796 kb
Host smart-1ea48754-b9ff-454c-af19-ac3f3c781fcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674178354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1674178354
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.4160583721
Short name T853
Test name
Test status
Simulation time 4315892220 ps
CPU time 11.16 seconds
Started May 21 02:11:44 PM PDT 24
Finished May 21 02:11:56 PM PDT 24
Peak memory 201948 kb
Host smart-ee0ab72b-942a-4778-82ed-e3d14f9b0445
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160583721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.4160583721
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1858589110
Short name T822
Test name
Test status
Simulation time 512051778 ps
CPU time 1.87 seconds
Started May 21 02:11:42 PM PDT 24
Finished May 21 02:11:46 PM PDT 24
Peak memory 201780 kb
Host smart-365309d2-62f2-45d2-950e-1956410934a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858589110 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1858589110
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.403089561
Short name T910
Test name
Test status
Simulation time 390084745 ps
CPU time 1.57 seconds
Started May 21 02:11:45 PM PDT 24
Finished May 21 02:11:47 PM PDT 24
Peak memory 201668 kb
Host smart-b9197053-63d7-428f-9d45-0116794a8966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403089561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.403089561
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.692952349
Short name T836
Test name
Test status
Simulation time 4607123456 ps
CPU time 10.03 seconds
Started May 21 02:11:45 PM PDT 24
Finished May 21 02:11:56 PM PDT 24
Peak memory 201920 kb
Host smart-f8f9e4b8-67b7-48e7-89be-69132f1987f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692952349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.692952349
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.345200118
Short name T90
Test name
Test status
Simulation time 466815257 ps
CPU time 2.55 seconds
Started May 21 02:11:47 PM PDT 24
Finished May 21 02:11:52 PM PDT 24
Peak memory 202020 kb
Host smart-bf5fb49a-68bb-4e5a-9c38-bc84f4d98817
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345200118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.345200118
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1471112999
Short name T896
Test name
Test status
Simulation time 4519633852 ps
CPU time 4.5 seconds
Started May 21 02:11:47 PM PDT 24
Finished May 21 02:11:53 PM PDT 24
Peak memory 202008 kb
Host smart-fa8c185c-697c-428d-809c-589f0ec611cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471112999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1471112999
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1619507374
Short name T809
Test name
Test status
Simulation time 610195821 ps
CPU time 1.75 seconds
Started May 21 02:11:50 PM PDT 24
Finished May 21 02:11:55 PM PDT 24
Peak memory 201748 kb
Host smart-67504ec0-52f5-404c-aec1-287805501be2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619507374 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1619507374
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3033849145
Short name T870
Test name
Test status
Simulation time 560455394 ps
CPU time 1.1 seconds
Started May 21 02:11:50 PM PDT 24
Finished May 21 02:11:54 PM PDT 24
Peak memory 201640 kb
Host smart-d3b9a86b-3e39-4d2a-9126-b9844c99539e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033849145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3033849145
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3885478399
Short name T897
Test name
Test status
Simulation time 485975558 ps
CPU time 0.93 seconds
Started May 21 02:11:49 PM PDT 24
Finished May 21 02:11:53 PM PDT 24
Peak memory 201700 kb
Host smart-032f69e1-7b8a-4c39-ab9a-d2c34c33aa61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885478399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3885478399
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.276438254
Short name T877
Test name
Test status
Simulation time 4177832311 ps
CPU time 3.71 seconds
Started May 21 02:11:54 PM PDT 24
Finished May 21 02:11:59 PM PDT 24
Peak memory 201868 kb
Host smart-e2ea46f9-6cdc-4285-90af-1cb22f30fdd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276438254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.276438254
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2745618222
Short name T85
Test name
Test status
Simulation time 874158226 ps
CPU time 2.83 seconds
Started May 21 02:11:48 PM PDT 24
Finished May 21 02:11:52 PM PDT 24
Peak memory 201984 kb
Host smart-faf4d1ea-9554-4498-9f2c-f379239d48d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745618222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2745618222
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3534215759
Short name T341
Test name
Test status
Simulation time 4430245893 ps
CPU time 6.56 seconds
Started May 21 02:11:50 PM PDT 24
Finished May 21 02:12:00 PM PDT 24
Peak memory 201896 kb
Host smart-7be67dcd-4b37-4174-b8ae-afdde22bb2af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534215759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3534215759
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3554480020
Short name T133
Test name
Test status
Simulation time 533518613 ps
CPU time 2.66 seconds
Started May 21 02:11:24 PM PDT 24
Finished May 21 02:11:28 PM PDT 24
Peak memory 201844 kb
Host smart-2bdffe6b-1a93-4dbf-b2cd-a2e8640cfe67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554480020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3554480020
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.790996326
Short name T127
Test name
Test status
Simulation time 12470417704 ps
CPU time 44.16 seconds
Started May 21 02:11:24 PM PDT 24
Finished May 21 02:12:10 PM PDT 24
Peak memory 201880 kb
Host smart-8d26653d-db6d-45d3-9b96-56e62d9dd2bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790996326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.790996326
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.951349476
Short name T871
Test name
Test status
Simulation time 886452024 ps
CPU time 2.72 seconds
Started May 21 02:11:20 PM PDT 24
Finished May 21 02:11:25 PM PDT 24
Peak memory 201712 kb
Host smart-ba2d68ba-30c3-4f7e-a479-36c3a89847d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951349476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.951349476
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3256710548
Short name T888
Test name
Test status
Simulation time 626395682 ps
CPU time 1.17 seconds
Started May 21 02:11:20 PM PDT 24
Finished May 21 02:11:23 PM PDT 24
Peak memory 201748 kb
Host smart-47d77792-dc9c-4546-b6eb-fa53f485ced6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256710548 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3256710548
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1498620459
Short name T893
Test name
Test status
Simulation time 340349425 ps
CPU time 0.94 seconds
Started May 21 02:11:20 PM PDT 24
Finished May 21 02:11:23 PM PDT 24
Peak memory 201668 kb
Host smart-0602e55c-15ec-49fc-a6b1-3b15ed70443e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498620459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1498620459
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.855671024
Short name T860
Test name
Test status
Simulation time 512826193 ps
CPU time 1.92 seconds
Started May 21 02:11:21 PM PDT 24
Finished May 21 02:11:25 PM PDT 24
Peak memory 201604 kb
Host smart-2aa6eba4-ae57-4ff6-9023-e6eb1af4b1d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855671024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.855671024
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.33225235
Short name T70
Test name
Test status
Simulation time 4508358568 ps
CPU time 2.7 seconds
Started May 21 02:11:23 PM PDT 24
Finished May 21 02:11:27 PM PDT 24
Peak memory 201924 kb
Host smart-b999184d-9017-40e0-adf3-5f5e2e488a59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33225235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctr
l_same_csr_outstanding.33225235
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1493646207
Short name T91
Test name
Test status
Simulation time 548866647 ps
CPU time 2.82 seconds
Started May 21 02:11:21 PM PDT 24
Finished May 21 02:11:26 PM PDT 24
Peak memory 211184 kb
Host smart-cf31ec9d-220a-4c7f-a945-408e69998f0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493646207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1493646207
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1529703639
Short name T846
Test name
Test status
Simulation time 501839265 ps
CPU time 0.93 seconds
Started May 21 02:11:50 PM PDT 24
Finished May 21 02:11:54 PM PDT 24
Peak memory 201660 kb
Host smart-38b5e8a4-46b2-4373-a656-2bb9f50e7b7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529703639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1529703639
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1340710020
Short name T906
Test name
Test status
Simulation time 401888326 ps
CPU time 1.14 seconds
Started May 21 02:11:51 PM PDT 24
Finished May 21 02:11:55 PM PDT 24
Peak memory 201704 kb
Host smart-e388fa93-9f1a-4049-a25a-79533d451d16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340710020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1340710020
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1949490082
Short name T891
Test name
Test status
Simulation time 320738150 ps
CPU time 0.84 seconds
Started May 21 02:11:48 PM PDT 24
Finished May 21 02:11:51 PM PDT 24
Peak memory 201628 kb
Host smart-b3299c96-dbfd-4987-ad27-f5ac8b496098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949490082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1949490082
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1327405185
Short name T875
Test name
Test status
Simulation time 518533192 ps
CPU time 1.87 seconds
Started May 21 02:11:51 PM PDT 24
Finished May 21 02:11:55 PM PDT 24
Peak memory 201696 kb
Host smart-de01f7e3-a2d4-4d67-81ae-8f455f92cd12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327405185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1327405185
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3406713771
Short name T863
Test name
Test status
Simulation time 474031676 ps
CPU time 1.67 seconds
Started May 21 02:11:50 PM PDT 24
Finished May 21 02:11:54 PM PDT 24
Peak memory 201688 kb
Host smart-2d719530-302a-49c8-801e-28d57b687c09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406713771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3406713771
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3206447786
Short name T806
Test name
Test status
Simulation time 354704928 ps
CPU time 1.05 seconds
Started May 21 02:11:51 PM PDT 24
Finished May 21 02:11:54 PM PDT 24
Peak memory 201676 kb
Host smart-16db40e8-87a6-4fcc-85af-12b25b4d82dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206447786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3206447786
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3737702728
Short name T802
Test name
Test status
Simulation time 429608019 ps
CPU time 0.75 seconds
Started May 21 02:11:50 PM PDT 24
Finished May 21 02:11:53 PM PDT 24
Peak memory 201724 kb
Host smart-c652ae0a-2856-4b87-873a-36eb41755fc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737702728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3737702728
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2115094819
Short name T838
Test name
Test status
Simulation time 397185388 ps
CPU time 1.12 seconds
Started May 21 02:11:50 PM PDT 24
Finished May 21 02:11:54 PM PDT 24
Peak memory 201680 kb
Host smart-6399327b-f7fd-41cb-8026-5aba0950334d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115094819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2115094819
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3393277032
Short name T797
Test name
Test status
Simulation time 437170294 ps
CPU time 1.1 seconds
Started May 21 02:11:50 PM PDT 24
Finished May 21 02:11:54 PM PDT 24
Peak memory 201700 kb
Host smart-12eab2fa-496f-4f0a-a9e2-d2c17beece44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393277032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3393277032
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2290446784
Short name T857
Test name
Test status
Simulation time 430912294 ps
CPU time 0.91 seconds
Started May 21 02:11:51 PM PDT 24
Finished May 21 02:11:54 PM PDT 24
Peak memory 201684 kb
Host smart-5c963382-c41f-4d48-a602-7003959f8133
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290446784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2290446784
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3048944603
Short name T916
Test name
Test status
Simulation time 1034487879 ps
CPU time 2.44 seconds
Started May 21 02:11:21 PM PDT 24
Finished May 21 02:11:25 PM PDT 24
Peak memory 201868 kb
Host smart-ed5d940e-3cac-4332-a41c-d86772c27913
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048944603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3048944603
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3996120992
Short name T827
Test name
Test status
Simulation time 26980607399 ps
CPU time 46.71 seconds
Started May 21 02:11:24 PM PDT 24
Finished May 21 02:12:12 PM PDT 24
Peak memory 201908 kb
Host smart-6edaf932-3aa2-458b-b7f2-8bf0f05245fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996120992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3996120992
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1863461497
Short name T903
Test name
Test status
Simulation time 1026559830 ps
CPU time 1.17 seconds
Started May 21 02:11:21 PM PDT 24
Finished May 21 02:11:24 PM PDT 24
Peak memory 201712 kb
Host smart-2d4792e5-9a92-4e10-b810-553731e556e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863461497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1863461497
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.91459149
Short name T900
Test name
Test status
Simulation time 472732394 ps
CPU time 1.96 seconds
Started May 21 02:11:21 PM PDT 24
Finished May 21 02:11:25 PM PDT 24
Peak memory 201756 kb
Host smart-dd728c83-1a04-4721-80d2-423c78bb301f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91459149 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.91459149
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2000015870
Short name T908
Test name
Test status
Simulation time 639497645 ps
CPU time 0.95 seconds
Started May 21 02:11:20 PM PDT 24
Finished May 21 02:11:23 PM PDT 24
Peak memory 201692 kb
Host smart-5075e6ff-4b3b-4ff3-81c9-e6fd94dfbaf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000015870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2000015870
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2797545819
Short name T811
Test name
Test status
Simulation time 430841635 ps
CPU time 0.93 seconds
Started May 21 02:11:24 PM PDT 24
Finished May 21 02:11:27 PM PDT 24
Peak memory 201656 kb
Host smart-d7d89e83-88a9-453b-aafc-cb3b27c9fcd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797545819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2797545819
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1775556940
Short name T71
Test name
Test status
Simulation time 2369131519 ps
CPU time 3.75 seconds
Started May 21 02:11:23 PM PDT 24
Finished May 21 02:11:28 PM PDT 24
Peak memory 201744 kb
Host smart-a2cc6bb4-5fcc-490c-9dc3-416d78b1396c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775556940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1775556940
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1257476470
Short name T876
Test name
Test status
Simulation time 653581670 ps
CPU time 1.73 seconds
Started May 21 02:11:21 PM PDT 24
Finished May 21 02:11:25 PM PDT 24
Peak memory 202016 kb
Host smart-260f626c-688c-446e-b1d5-f0b7bc1ea5e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257476470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1257476470
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3798824034
Short name T894
Test name
Test status
Simulation time 4687772656 ps
CPU time 7.35 seconds
Started May 21 02:11:24 PM PDT 24
Finished May 21 02:11:33 PM PDT 24
Peak memory 202040 kb
Host smart-4c09d0e0-f9a0-4e3f-a1d3-9a0a5509bf65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798824034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3798824034
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.4194948987
Short name T912
Test name
Test status
Simulation time 423062041 ps
CPU time 1.11 seconds
Started May 21 02:11:51 PM PDT 24
Finished May 21 02:11:54 PM PDT 24
Peak memory 201696 kb
Host smart-9d37a903-7e2c-4f60-8bca-b5a7667bfa98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194948987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.4194948987
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3602927318
Short name T850
Test name
Test status
Simulation time 505985800 ps
CPU time 1.77 seconds
Started May 21 02:11:48 PM PDT 24
Finished May 21 02:11:51 PM PDT 24
Peak memory 201692 kb
Host smart-40361521-2579-4157-8530-528472d64a18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602927318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3602927318
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1995536546
Short name T817
Test name
Test status
Simulation time 413466354 ps
CPU time 1.11 seconds
Started May 21 02:11:50 PM PDT 24
Finished May 21 02:11:54 PM PDT 24
Peak memory 201700 kb
Host smart-ed4e7a2e-d7ba-4fc1-869d-9f1d60c430a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995536546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1995536546
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1757142260
Short name T804
Test name
Test status
Simulation time 363878494 ps
CPU time 1.03 seconds
Started May 21 02:11:49 PM PDT 24
Finished May 21 02:11:53 PM PDT 24
Peak memory 201676 kb
Host smart-6a0bb9aa-4283-49a2-b5c5-3e1b7388f7db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757142260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1757142260
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3551957824
Short name T824
Test name
Test status
Simulation time 442385194 ps
CPU time 1.69 seconds
Started May 21 02:11:50 PM PDT 24
Finished May 21 02:11:54 PM PDT 24
Peak memory 201704 kb
Host smart-df84ed23-a38a-4456-94f5-caa106a7cce5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551957824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3551957824
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1460945382
Short name T803
Test name
Test status
Simulation time 378051717 ps
CPU time 0.85 seconds
Started May 21 02:11:50 PM PDT 24
Finished May 21 02:11:53 PM PDT 24
Peak memory 201672 kb
Host smart-c0f17e1b-1214-47ad-8dd2-79e0bde35efa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460945382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1460945382
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.180923898
Short name T828
Test name
Test status
Simulation time 525389789 ps
CPU time 1.22 seconds
Started May 21 02:11:51 PM PDT 24
Finished May 21 02:11:55 PM PDT 24
Peak memory 201720 kb
Host smart-49b18963-55ea-4bf8-b281-55a5371e041b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180923898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.180923898
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3704696536
Short name T848
Test name
Test status
Simulation time 500856093 ps
CPU time 1.22 seconds
Started May 21 02:11:55 PM PDT 24
Finished May 21 02:11:58 PM PDT 24
Peak memory 201628 kb
Host smart-c84e08cb-1f91-488f-8a02-6d52d656e71a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704696536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3704696536
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3445164897
Short name T844
Test name
Test status
Simulation time 343326234 ps
CPU time 0.86 seconds
Started May 21 02:11:50 PM PDT 24
Finished May 21 02:11:54 PM PDT 24
Peak memory 201692 kb
Host smart-0b10bb7f-c8bb-4f21-a949-908903f5a284
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445164897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3445164897
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2225063223
Short name T807
Test name
Test status
Simulation time 505374137 ps
CPU time 1.69 seconds
Started May 21 02:11:54 PM PDT 24
Finished May 21 02:11:58 PM PDT 24
Peak memory 201616 kb
Host smart-7517c440-0d36-41b1-aa08-25f7cbff6fb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225063223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2225063223
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1768173665
Short name T819
Test name
Test status
Simulation time 970873968 ps
CPU time 1.93 seconds
Started May 21 02:11:21 PM PDT 24
Finished May 21 02:11:24 PM PDT 24
Peak memory 201948 kb
Host smart-15abb650-14c9-4df5-8ebc-057c884a88ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768173665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1768173665
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3853082816
Short name T134
Test name
Test status
Simulation time 26550225973 ps
CPU time 7.18 seconds
Started May 21 02:11:23 PM PDT 24
Finished May 21 02:11:31 PM PDT 24
Peak memory 201972 kb
Host smart-acf3d353-e953-492d-b5a4-248fd4602c53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853082816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3853082816
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1971709462
Short name T834
Test name
Test status
Simulation time 792205177 ps
CPU time 2.58 seconds
Started May 21 02:11:21 PM PDT 24
Finished May 21 02:11:25 PM PDT 24
Peak memory 201660 kb
Host smart-503daffe-8442-48ee-aa68-d97574dff2f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971709462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1971709462
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3076902927
Short name T867
Test name
Test status
Simulation time 609304615 ps
CPU time 2.39 seconds
Started May 21 02:11:31 PM PDT 24
Finished May 21 02:11:35 PM PDT 24
Peak memory 201952 kb
Host smart-2179fb63-ac80-418b-b718-c5a36acdcfe0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076902927 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3076902927
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1266364743
Short name T138
Test name
Test status
Simulation time 301786260 ps
CPU time 1.49 seconds
Started May 21 02:11:22 PM PDT 24
Finished May 21 02:11:25 PM PDT 24
Peak memory 201684 kb
Host smart-4a7db306-4da7-4f80-bcc1-905d36e410ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266364743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1266364743
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3984663062
Short name T816
Test name
Test status
Simulation time 529777510 ps
CPU time 1.86 seconds
Started May 21 02:11:21 PM PDT 24
Finished May 21 02:11:25 PM PDT 24
Peak memory 201684 kb
Host smart-a6f309cd-ca5b-4cfe-8217-0fabf787e73a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984663062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3984663062
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.652107737
Short name T859
Test name
Test status
Simulation time 2419459061 ps
CPU time 6.12 seconds
Started May 21 02:11:23 PM PDT 24
Finished May 21 02:11:31 PM PDT 24
Peak memory 201752 kb
Host smart-94b7a31d-9be0-4d6e-8ef2-c78a0ae2b5b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652107737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.652107737
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3341978437
Short name T84
Test name
Test status
Simulation time 408723721 ps
CPU time 2.47 seconds
Started May 21 02:11:20 PM PDT 24
Finished May 21 02:11:24 PM PDT 24
Peak memory 218272 kb
Host smart-2cb9d2a8-6aaf-4177-afb7-e4a2584a3d93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341978437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3341978437
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3160599285
Short name T75
Test name
Test status
Simulation time 4448395894 ps
CPU time 11.74 seconds
Started May 21 02:11:23 PM PDT 24
Finished May 21 02:11:36 PM PDT 24
Peak memory 201968 kb
Host smart-3e1e9ecd-d720-403e-b829-db9e645f3f31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160599285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3160599285
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3836066356
Short name T869
Test name
Test status
Simulation time 529260748 ps
CPU time 0.96 seconds
Started May 21 02:11:49 PM PDT 24
Finished May 21 02:11:53 PM PDT 24
Peak memory 201700 kb
Host smart-0b7782fe-5ab2-43af-86ca-5c6284196ca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836066356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3836066356
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.844661600
Short name T865
Test name
Test status
Simulation time 305698906 ps
CPU time 0.83 seconds
Started May 21 02:11:51 PM PDT 24
Finished May 21 02:11:55 PM PDT 24
Peak memory 201720 kb
Host smart-112bb04d-9a5d-4785-a94e-9089a66b3a86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844661600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.844661600
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1115833779
Short name T864
Test name
Test status
Simulation time 285904600 ps
CPU time 1.3 seconds
Started May 21 02:11:51 PM PDT 24
Finished May 21 02:11:55 PM PDT 24
Peak memory 201732 kb
Host smart-c11570d2-f457-4ac7-8aa5-623eb95eb3d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115833779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1115833779
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1347093175
Short name T911
Test name
Test status
Simulation time 294745109 ps
CPU time 1.44 seconds
Started May 21 02:11:54 PM PDT 24
Finished May 21 02:11:57 PM PDT 24
Peak memory 201612 kb
Host smart-bb1bbda0-13db-4e47-a2da-cd1b5599a9a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347093175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1347093175
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2447799331
Short name T858
Test name
Test status
Simulation time 429151316 ps
CPU time 0.78 seconds
Started May 21 02:11:49 PM PDT 24
Finished May 21 02:11:53 PM PDT 24
Peak memory 201700 kb
Host smart-355af750-fa31-4de3-9a3d-15cabaa7b094
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447799331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2447799331
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.394889583
Short name T800
Test name
Test status
Simulation time 414864497 ps
CPU time 1.67 seconds
Started May 21 02:11:55 PM PDT 24
Finished May 21 02:11:59 PM PDT 24
Peak memory 201712 kb
Host smart-5f181f8d-29ef-4a57-91d2-c25a4129743e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394889583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.394889583
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3879400287
Short name T815
Test name
Test status
Simulation time 431826981 ps
CPU time 0.79 seconds
Started May 21 02:11:54 PM PDT 24
Finished May 21 02:11:57 PM PDT 24
Peak memory 201676 kb
Host smart-451cee28-7064-4c2a-a913-6c2ab24a21d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879400287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3879400287
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.973807883
Short name T899
Test name
Test status
Simulation time 280446825 ps
CPU time 1.33 seconds
Started May 21 02:11:57 PM PDT 24
Finished May 21 02:12:01 PM PDT 24
Peak memory 201700 kb
Host smart-e21816fa-ddd2-4e72-9999-55cbed1bd871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973807883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.973807883
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2123455692
Short name T814
Test name
Test status
Simulation time 601972278 ps
CPU time 0.69 seconds
Started May 21 02:11:56 PM PDT 24
Finished May 21 02:11:59 PM PDT 24
Peak memory 201696 kb
Host smart-01caaa91-f009-46b8-b7ff-ee5f5773af4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123455692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2123455692
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2226702354
Short name T810
Test name
Test status
Simulation time 322969394 ps
CPU time 1.35 seconds
Started May 21 02:11:53 PM PDT 24
Finished May 21 02:11:56 PM PDT 24
Peak memory 201696 kb
Host smart-659cd986-8a37-4bf4-a826-3daec04d33c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226702354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2226702354
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2957137637
Short name T886
Test name
Test status
Simulation time 444516069 ps
CPU time 1.14 seconds
Started May 21 02:11:25 PM PDT 24
Finished May 21 02:11:28 PM PDT 24
Peak memory 201752 kb
Host smart-b1f36f33-83f5-4da8-aeb1-7f85ad16d23e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957137637 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2957137637
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2501246419
Short name T882
Test name
Test status
Simulation time 541524821 ps
CPU time 1.88 seconds
Started May 21 02:11:27 PM PDT 24
Finished May 21 02:11:31 PM PDT 24
Peak memory 201724 kb
Host smart-3ed53fff-f23c-4782-9509-fd35d2c5c214
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501246419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2501246419
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2134300029
Short name T796
Test name
Test status
Simulation time 510567637 ps
CPU time 1.86 seconds
Started May 21 02:11:31 PM PDT 24
Finished May 21 02:11:35 PM PDT 24
Peak memory 201688 kb
Host smart-82103bf3-15bd-43b3-83b6-2b6fcba2cbdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134300029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2134300029
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2734659648
Short name T879
Test name
Test status
Simulation time 2026846318 ps
CPU time 1.65 seconds
Started May 21 02:11:32 PM PDT 24
Finished May 21 02:11:35 PM PDT 24
Peak memory 201688 kb
Host smart-17d240f2-3352-4760-9cbc-1e7e08edb7fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734659648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2734659648
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4186278711
Short name T874
Test name
Test status
Simulation time 347373386 ps
CPU time 2.31 seconds
Started May 21 02:11:27 PM PDT 24
Finished May 21 02:11:31 PM PDT 24
Peak memory 210192 kb
Host smart-ed2334af-d02e-4fb6-9c47-bdbfc426ece3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186278711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.4186278711
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3328915205
Short name T901
Test name
Test status
Simulation time 678295046 ps
CPU time 1.33 seconds
Started May 21 02:11:27 PM PDT 24
Finished May 21 02:11:30 PM PDT 24
Peak memory 201752 kb
Host smart-5d16852d-5653-4ec6-84df-553de9e401fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328915205 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3328915205
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3195805390
Short name T137
Test name
Test status
Simulation time 461274847 ps
CPU time 1.91 seconds
Started May 21 02:11:26 PM PDT 24
Finished May 21 02:11:30 PM PDT 24
Peak memory 201716 kb
Host smart-ba4058ef-9942-4bd0-9400-d2684e871589
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195805390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3195805390
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2794345644
Short name T837
Test name
Test status
Simulation time 287935357 ps
CPU time 0.97 seconds
Started May 21 02:11:26 PM PDT 24
Finished May 21 02:11:29 PM PDT 24
Peak memory 201732 kb
Host smart-22e4260b-4482-4e51-b8d1-97adde156e2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794345644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2794345644
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3696143300
Short name T139
Test name
Test status
Simulation time 1992775043 ps
CPU time 2.93 seconds
Started May 21 02:11:26 PM PDT 24
Finished May 21 02:11:31 PM PDT 24
Peak memory 201696 kb
Host smart-e0afa2f3-fa20-449d-bf1d-0b352a26c48e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696143300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3696143300
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2833992113
Short name T833
Test name
Test status
Simulation time 477690503 ps
CPU time 3.76 seconds
Started May 21 02:11:27 PM PDT 24
Finished May 21 02:11:32 PM PDT 24
Peak memory 201936 kb
Host smart-a5dd9932-211f-4492-930a-5197c272642f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833992113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2833992113
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1756582638
Short name T93
Test name
Test status
Simulation time 4288954812 ps
CPU time 3.85 seconds
Started May 21 02:11:25 PM PDT 24
Finished May 21 02:11:31 PM PDT 24
Peak memory 201976 kb
Host smart-fd9ca899-070b-4e74-9e04-c698289bbea7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756582638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1756582638
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4117009416
Short name T872
Test name
Test status
Simulation time 566555671 ps
CPU time 1.12 seconds
Started May 21 02:11:30 PM PDT 24
Finished May 21 02:11:33 PM PDT 24
Peak memory 201740 kb
Host smart-7e88ea2f-900f-4398-b0df-787f5afd3dc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117009416 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.4117009416
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2173419595
Short name T918
Test name
Test status
Simulation time 345501387 ps
CPU time 1.62 seconds
Started May 21 02:11:30 PM PDT 24
Finished May 21 02:11:34 PM PDT 24
Peak memory 201896 kb
Host smart-c205c359-dab3-4ae7-9d3b-03d118a26f6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173419595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2173419595
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2784971957
Short name T835
Test name
Test status
Simulation time 474391665 ps
CPU time 1.75 seconds
Started May 21 02:11:29 PM PDT 24
Finished May 21 02:11:32 PM PDT 24
Peak memory 201704 kb
Host smart-15fc7176-a906-4ccc-bda0-671012d34c7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784971957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2784971957
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1048082915
Short name T887
Test name
Test status
Simulation time 4264645986 ps
CPU time 16.67 seconds
Started May 21 02:11:31 PM PDT 24
Finished May 21 02:11:49 PM PDT 24
Peak memory 202140 kb
Host smart-49d303be-8481-4a74-b21a-03ebf692f71e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048082915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1048082915
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.554805086
Short name T878
Test name
Test status
Simulation time 559491006 ps
CPU time 3.07 seconds
Started May 21 02:11:27 PM PDT 24
Finished May 21 02:11:32 PM PDT 24
Peak memory 201972 kb
Host smart-33fdec32-137f-463b-b576-3712d9f1a601
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554805086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.554805086
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.76461723
Short name T340
Test name
Test status
Simulation time 4096409138 ps
CPU time 6.89 seconds
Started May 21 02:11:26 PM PDT 24
Finished May 21 02:11:35 PM PDT 24
Peak memory 201976 kb
Host smart-5f84f650-da97-4983-8830-64389b5d17e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76461723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_intg
_err.76461723
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1967603934
Short name T841
Test name
Test status
Simulation time 479181878 ps
CPU time 2.12 seconds
Started May 21 02:11:26 PM PDT 24
Finished May 21 02:11:30 PM PDT 24
Peak memory 201724 kb
Host smart-7d266452-9835-4cd6-aac2-a529f88c1d7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967603934 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1967603934
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.424607308
Short name T843
Test name
Test status
Simulation time 514032699 ps
CPU time 1 seconds
Started May 21 02:11:29 PM PDT 24
Finished May 21 02:11:31 PM PDT 24
Peak memory 201716 kb
Host smart-210e80cf-2f56-4dd0-994b-d7ae00073fa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424607308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.424607308
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1086464300
Short name T799
Test name
Test status
Simulation time 354773515 ps
CPU time 1.45 seconds
Started May 21 02:11:25 PM PDT 24
Finished May 21 02:11:28 PM PDT 24
Peak memory 201728 kb
Host smart-81d899ac-c960-4cb0-87cf-ed73afdeb101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086464300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1086464300
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.293103912
Short name T895
Test name
Test status
Simulation time 2833751669 ps
CPU time 6.86 seconds
Started May 21 02:11:32 PM PDT 24
Finished May 21 02:11:40 PM PDT 24
Peak memory 202164 kb
Host smart-b3f29688-8052-4b7a-b465-a8fbb4baaffc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293103912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.293103912
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2843191561
Short name T898
Test name
Test status
Simulation time 716145750 ps
CPU time 2.86 seconds
Started May 21 02:11:27 PM PDT 24
Finished May 21 02:11:32 PM PDT 24
Peak memory 217816 kb
Host smart-d1908e07-657c-4ea2-bcbb-766a880ad76c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843191561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2843191561
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1023711779
Short name T76
Test name
Test status
Simulation time 4884644513 ps
CPU time 4.42 seconds
Started May 21 02:11:28 PM PDT 24
Finished May 21 02:11:33 PM PDT 24
Peak memory 201936 kb
Host smart-b1829eb1-5833-407c-a86e-f8776d0580ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023711779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1023711779
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.390369284
Short name T805
Test name
Test status
Simulation time 537600226 ps
CPU time 1.58 seconds
Started May 21 02:11:35 PM PDT 24
Finished May 21 02:11:39 PM PDT 24
Peak memory 201744 kb
Host smart-ce27627c-41d0-4f49-bbb1-d6b624addb2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390369284 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.390369284
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2630659382
Short name T914
Test name
Test status
Simulation time 422902110 ps
CPU time 1.01 seconds
Started May 21 02:11:25 PM PDT 24
Finished May 21 02:11:28 PM PDT 24
Peak memory 201704 kb
Host smart-7661f236-758d-4638-861a-a08ae1d5aae8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630659382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2630659382
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3054272063
Short name T913
Test name
Test status
Simulation time 380954991 ps
CPU time 1.51 seconds
Started May 21 02:11:26 PM PDT 24
Finished May 21 02:11:30 PM PDT 24
Peak memory 201708 kb
Host smart-f88684a6-62a1-4a0d-93ab-c484f7c4daaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054272063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3054272063
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.607173144
Short name T832
Test name
Test status
Simulation time 4112500897 ps
CPU time 6.88 seconds
Started May 21 02:11:29 PM PDT 24
Finished May 21 02:11:37 PM PDT 24
Peak memory 202000 kb
Host smart-2b65d9e2-44a2-4fe0-803d-8ced744899d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607173144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.607173144
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3368407630
Short name T89
Test name
Test status
Simulation time 447221808 ps
CPU time 1.48 seconds
Started May 21 02:11:27 PM PDT 24
Finished May 21 02:11:30 PM PDT 24
Peak memory 201904 kb
Host smart-c682c366-42a3-4e55-af79-417bfca54731
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368407630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3368407630
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2172741655
Short name T881
Test name
Test status
Simulation time 7833113364 ps
CPU time 19.02 seconds
Started May 21 02:11:30 PM PDT 24
Finished May 21 02:11:51 PM PDT 24
Peak memory 201956 kb
Host smart-23065911-48c9-44e0-8195-ca8631fd1825
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172741655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2172741655
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3280440670
Short name T713
Test name
Test status
Simulation time 162368417942 ps
CPU time 410.2 seconds
Started May 21 02:39:43 PM PDT 24
Finished May 21 02:46:53 PM PDT 24
Peak memory 201820 kb
Host smart-2ed16f83-fd80-438c-913c-0a87d6a407e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280440670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3280440670
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.565828367
Short name T151
Test name
Test status
Simulation time 488681399160 ps
CPU time 752.19 seconds
Started May 21 02:39:42 PM PDT 24
Finished May 21 02:52:34 PM PDT 24
Peak memory 201848 kb
Host smart-39fa62b4-568b-4c83-8593-45e1fcb73afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565828367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.565828367
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2002885214
Short name T485
Test name
Test status
Simulation time 165385896761 ps
CPU time 187.92 seconds
Started May 21 02:39:43 PM PDT 24
Finished May 21 02:43:11 PM PDT 24
Peak memory 201732 kb
Host smart-4c69e2aa-0ee2-420e-8f57-09ac9079988f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002885214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2002885214
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.632973268
Short name T337
Test name
Test status
Simulation time 168527704020 ps
CPU time 109.45 seconds
Started May 21 02:39:42 PM PDT 24
Finished May 21 02:41:52 PM PDT 24
Peak memory 201840 kb
Host smart-5838e1c0-8b63-4992-9de3-8afb8aa330b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632973268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.632973268
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.299917632
Short name T539
Test name
Test status
Simulation time 200185133353 ps
CPU time 446.51 seconds
Started May 21 02:39:42 PM PDT 24
Finished May 21 02:47:28 PM PDT 24
Peak memory 201736 kb
Host smart-15256a9b-0fc3-495f-a179-8e3897d9e92c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299917632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.299917632
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3246766666
Short name T343
Test name
Test status
Simulation time 72096117978 ps
CPU time 370.3 seconds
Started May 21 02:39:43 PM PDT 24
Finished May 21 02:46:13 PM PDT 24
Peak memory 202128 kb
Host smart-0be21fe4-eedd-43e8-9e0c-cb6c1eaaa3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246766666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3246766666
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1450418643
Short name T711
Test name
Test status
Simulation time 38929745042 ps
CPU time 91.9 seconds
Started May 21 02:39:43 PM PDT 24
Finished May 21 02:41:35 PM PDT 24
Peak memory 201680 kb
Host smart-895de3ca-3f21-41e6-95e5-73fb7b0966ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450418643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1450418643
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.18396015
Short name T69
Test name
Test status
Simulation time 2891195110 ps
CPU time 8.15 seconds
Started May 21 02:41:06 PM PDT 24
Finished May 21 02:41:29 PM PDT 24
Peak memory 201568 kb
Host smart-a11c3232-f471-43b0-9952-fe1846ebb181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18396015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.18396015
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1427033252
Short name T403
Test name
Test status
Simulation time 6110737207 ps
CPU time 4.83 seconds
Started May 21 02:39:41 PM PDT 24
Finished May 21 02:40:06 PM PDT 24
Peak memory 201632 kb
Host smart-65070290-a897-466f-8c18-2236520007fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427033252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1427033252
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1312631538
Short name T677
Test name
Test status
Simulation time 34767915897 ps
CPU time 34.91 seconds
Started May 21 02:39:42 PM PDT 24
Finished May 21 02:40:37 PM PDT 24
Peak memory 201680 kb
Host smart-6265e2f6-4b9c-4be3-bf95-a88ba94a1b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312631538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1312631538
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2344111276
Short name T721
Test name
Test status
Simulation time 443583907 ps
CPU time 0.93 seconds
Started May 21 02:39:48 PM PDT 24
Finished May 21 02:40:07 PM PDT 24
Peak memory 201528 kb
Host smart-e24f9881-bdcf-431d-86d8-9eb9464cf6d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344111276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2344111276
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3399034275
Short name T321
Test name
Test status
Simulation time 529182242972 ps
CPU time 991.35 seconds
Started May 21 02:41:06 PM PDT 24
Finished May 21 02:57:52 PM PDT 24
Peak memory 201820 kb
Host smart-20691e5d-ccb1-4aff-aa47-b3fa20e91d37
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399034275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3399034275
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1462161
Short name T592
Test name
Test status
Simulation time 166189837759 ps
CPU time 207.59 seconds
Started May 21 02:39:49 PM PDT 24
Finished May 21 02:43:35 PM PDT 24
Peak memory 201812 kb
Host smart-599db536-1484-49cd-b746-3bdcb6c05b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1462161
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2278066949
Short name T325
Test name
Test status
Simulation time 491651600490 ps
CPU time 616.19 seconds
Started May 21 02:41:09 PM PDT 24
Finished May 21 02:51:39 PM PDT 24
Peak memory 201856 kb
Host smart-d9060a30-856e-4d89-b258-d772a2897ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278066949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2278066949
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.4264409834
Short name T210
Test name
Test status
Simulation time 489519508702 ps
CPU time 1129.71 seconds
Started May 21 02:39:47 PM PDT 24
Finished May 21 02:58:56 PM PDT 24
Peak memory 201880 kb
Host smart-3540c70d-d785-4297-ad27-2e3ecf75bf39
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264409834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.4264409834
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.178372374
Short name T660
Test name
Test status
Simulation time 164496008217 ps
CPU time 389.84 seconds
Started May 21 02:39:51 PM PDT 24
Finished May 21 02:46:38 PM PDT 24
Peak memory 201820 kb
Host smart-972dd7cd-0532-4032-aab7-7cc76f08ed41
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=178372374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed
.178372374
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2176868146
Short name T685
Test name
Test status
Simulation time 188853934394 ps
CPU time 393.2 seconds
Started May 21 02:39:49 PM PDT 24
Finished May 21 02:46:40 PM PDT 24
Peak memory 202040 kb
Host smart-54be9ed1-7cd8-4bd2-b3b3-2c8bbe128207
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176868146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2176868146
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2706411383
Short name T743
Test name
Test status
Simulation time 405451759484 ps
CPU time 243.39 seconds
Started May 21 02:39:48 PM PDT 24
Finished May 21 02:44:10 PM PDT 24
Peak memory 201848 kb
Host smart-a814e72d-b955-4377-9701-d576e64f9158
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706411383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2706411383
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2497794452
Short name T731
Test name
Test status
Simulation time 125917896161 ps
CPU time 577.76 seconds
Started May 21 02:39:48 PM PDT 24
Finished May 21 02:49:44 PM PDT 24
Peak memory 202184 kb
Host smart-269815e6-df7d-4dd7-99cc-a7db538ce9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497794452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2497794452
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1752288648
Short name T427
Test name
Test status
Simulation time 34960662130 ps
CPU time 20.49 seconds
Started May 21 02:39:49 PM PDT 24
Finished May 21 02:40:27 PM PDT 24
Peak memory 201656 kb
Host smart-4192619e-500c-45cf-89fb-b3a6dfafdcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752288648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1752288648
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1305781657
Short name T112
Test name
Test status
Simulation time 3132043374 ps
CPU time 8.11 seconds
Started May 21 02:39:51 PM PDT 24
Finished May 21 02:40:16 PM PDT 24
Peak memory 201572 kb
Host smart-fdcb006c-2b02-4619-a2c3-1ed3e931ad04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305781657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1305781657
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.389808807
Short name T81
Test name
Test status
Simulation time 8411414790 ps
CPU time 2.55 seconds
Started May 21 02:39:48 PM PDT 24
Finished May 21 02:40:09 PM PDT 24
Peak memory 218456 kb
Host smart-7e1cad41-9824-4671-87fb-d68d87480911
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389808807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.389808807
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2072385586
Short name T722
Test name
Test status
Simulation time 6066534804 ps
CPU time 15.75 seconds
Started May 21 02:39:47 PM PDT 24
Finished May 21 02:40:22 PM PDT 24
Peak memory 201620 kb
Host smart-fd10af20-751f-45c1-8500-9f55e8d53a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072385586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2072385586
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.65805192
Short name T16
Test name
Test status
Simulation time 36014367315 ps
CPU time 38.91 seconds
Started May 21 02:39:51 PM PDT 24
Finished May 21 02:40:47 PM PDT 24
Peak memory 210200 kb
Host smart-36e6b050-b2a6-46a4-af2b-a5beafce0d51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65805192 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.65805192
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3352246739
Short name T729
Test name
Test status
Simulation time 354998160 ps
CPU time 1.42 seconds
Started May 21 02:40:50 PM PDT 24
Finished May 21 02:41:06 PM PDT 24
Peak memory 201576 kb
Host smart-d3ea126c-52b3-438f-87f4-7c2d7d2ca131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352246739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3352246739
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3612411918
Short name T293
Test name
Test status
Simulation time 328641876303 ps
CPU time 468.37 seconds
Started May 21 02:40:38 PM PDT 24
Finished May 21 02:48:30 PM PDT 24
Peak memory 201832 kb
Host smart-f1c9f7c8-39e5-4a4b-9c7d-951864e56345
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612411918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3612411918
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2258746645
Short name T761
Test name
Test status
Simulation time 338257373040 ps
CPU time 328.76 seconds
Started May 21 02:40:41 PM PDT 24
Finished May 21 02:46:16 PM PDT 24
Peak memory 201872 kb
Host smart-93c93e49-739a-4b71-bc15-048b8d461eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258746645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2258746645
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.591063432
Short name T30
Test name
Test status
Simulation time 487445026330 ps
CPU time 1078 seconds
Started May 21 02:40:39 PM PDT 24
Finished May 21 02:58:43 PM PDT 24
Peak memory 201840 kb
Host smart-8d7b6c18-ed8b-4add-be38-b1b3245bc533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591063432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.591063432
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3302570497
Short name T620
Test name
Test status
Simulation time 325050157799 ps
CPU time 684.52 seconds
Started May 21 02:40:41 PM PDT 24
Finished May 21 02:52:11 PM PDT 24
Peak memory 201852 kb
Host smart-50094fc0-624f-44f6-b7b0-8bb9bc7cc3e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302570497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3302570497
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.640017624
Short name T473
Test name
Test status
Simulation time 163226067499 ps
CPU time 344.97 seconds
Started May 21 02:40:39 PM PDT 24
Finished May 21 02:46:30 PM PDT 24
Peak memory 201888 kb
Host smart-5f1414eb-b9a3-4a79-bd71-32c6734df6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640017624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.640017624
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3306976895
Short name T419
Test name
Test status
Simulation time 321348211673 ps
CPU time 134.54 seconds
Started May 21 02:40:37 PM PDT 24
Finished May 21 02:42:56 PM PDT 24
Peak memory 201816 kb
Host smart-fc45a119-5c16-447f-acfe-8f5bd09c7000
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306976895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3306976895
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2100462383
Short name T780
Test name
Test status
Simulation time 199817418597 ps
CPU time 232.63 seconds
Started May 21 02:40:37 PM PDT 24
Finished May 21 02:44:33 PM PDT 24
Peak memory 201772 kb
Host smart-0a57905f-d6af-44de-aa98-1a83ecee90a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100462383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2100462383
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2007697451
Short name T727
Test name
Test status
Simulation time 91047719238 ps
CPU time 384.26 seconds
Started May 21 02:40:52 PM PDT 24
Finished May 21 02:47:32 PM PDT 24
Peak memory 202156 kb
Host smart-dfde90ff-bfbe-4fcb-b921-7dd7c9f1911d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007697451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2007697451
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1884433231
Short name T532
Test name
Test status
Simulation time 36278189990 ps
CPU time 82.7 seconds
Started May 21 02:40:46 PM PDT 24
Finished May 21 02:42:20 PM PDT 24
Peak memory 201652 kb
Host smart-43e7a1f2-9499-4be5-8ad1-fd81c85dbd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884433231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1884433231
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.651997950
Short name T778
Test name
Test status
Simulation time 3153650984 ps
CPU time 2.42 seconds
Started May 21 02:40:40 PM PDT 24
Finished May 21 02:40:48 PM PDT 24
Peak memory 201644 kb
Host smart-0ad0f900-1949-465f-83b5-f753a6f5d106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651997950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.651997950
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3074812985
Short name T157
Test name
Test status
Simulation time 5841651599 ps
CPU time 14.83 seconds
Started May 21 02:40:38 PM PDT 24
Finished May 21 02:40:58 PM PDT 24
Peak memory 201600 kb
Host smart-eb3c43b9-7419-4983-a28e-4e81589c8fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074812985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3074812985
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.686400538
Short name T464
Test name
Test status
Simulation time 209199220602 ps
CPU time 495.22 seconds
Started May 21 02:40:48 PM PDT 24
Finished May 21 02:49:15 PM PDT 24
Peak memory 201872 kb
Host smart-9afcfbf6-2206-4758-982e-eaf544fb0d05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686400538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
686400538
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3848286096
Short name T322
Test name
Test status
Simulation time 154149260399 ps
CPU time 175.2 seconds
Started May 21 02:40:46 PM PDT 24
Finished May 21 02:43:52 PM PDT 24
Peak memory 210496 kb
Host smart-5962ffb6-f248-457c-8dbe-e2fdfd6d0f70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848286096 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3848286096
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3639491353
Short name T450
Test name
Test status
Simulation time 476486385 ps
CPU time 0.92 seconds
Started May 21 02:40:43 PM PDT 24
Finished May 21 02:40:52 PM PDT 24
Peak memory 201576 kb
Host smart-b73179ef-5293-4b5d-b5b2-af8194dd494b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639491353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3639491353
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1734253315
Short name T318
Test name
Test status
Simulation time 326963118642 ps
CPU time 209.91 seconds
Started May 21 02:40:50 PM PDT 24
Finished May 21 02:44:33 PM PDT 24
Peak memory 201840 kb
Host smart-c41bba7e-6c07-4128-9a0f-e1b55896d3c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734253315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1734253315
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2742845191
Short name T174
Test name
Test status
Simulation time 164007881481 ps
CPU time 402.22 seconds
Started May 21 02:40:49 PM PDT 24
Finished May 21 02:47:45 PM PDT 24
Peak memory 201836 kb
Host smart-5fc0fea0-b4b6-418c-a447-c598a49ff3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742845191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2742845191
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3266223234
Short name T484
Test name
Test status
Simulation time 166459041736 ps
CPU time 73.17 seconds
Started May 21 02:41:09 PM PDT 24
Finished May 21 02:42:36 PM PDT 24
Peak memory 201852 kb
Host smart-d849773b-4c13-4d24-b464-39832338f445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266223234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3266223234
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1801459374
Short name T470
Test name
Test status
Simulation time 323789981078 ps
CPU time 213.56 seconds
Started May 21 02:40:44 PM PDT 24
Finished May 21 02:44:25 PM PDT 24
Peak memory 201836 kb
Host smart-f430cb5b-8f18-4613-bf9d-3d9e90d5b35c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801459374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1801459374
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.4014189036
Short name T386
Test name
Test status
Simulation time 497761701369 ps
CPU time 296.48 seconds
Started May 21 02:40:44 PM PDT 24
Finished May 21 02:45:49 PM PDT 24
Peak memory 201892 kb
Host smart-b0775d42-fc7a-4163-a1ed-2ec465b02e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014189036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.4014189036
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2620578905
Short name T627
Test name
Test status
Simulation time 167739346607 ps
CPU time 93.74 seconds
Started May 21 02:40:45 PM PDT 24
Finished May 21 02:42:28 PM PDT 24
Peak memory 201804 kb
Host smart-393b75b4-c4a6-4bba-82ac-024c2236bded
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620578905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2620578905
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3320028796
Short name T168
Test name
Test status
Simulation time 181969057758 ps
CPU time 459.03 seconds
Started May 21 02:40:46 PM PDT 24
Finished May 21 02:48:36 PM PDT 24
Peak memory 201944 kb
Host smart-0fb524ad-0105-4c26-9f52-8b77a3ed4f1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320028796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3320028796
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2575532714
Short name T432
Test name
Test status
Simulation time 125110448024 ps
CPU time 483.15 seconds
Started May 21 02:41:09 PM PDT 24
Finished May 21 02:49:26 PM PDT 24
Peak memory 202232 kb
Host smart-d89bfe3c-4a73-4ccc-b4b0-9a1fc6795878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575532714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2575532714
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.970392309
Short name T647
Test name
Test status
Simulation time 30697491336 ps
CPU time 19.23 seconds
Started May 21 02:40:44 PM PDT 24
Finished May 21 02:41:12 PM PDT 24
Peak memory 201596 kb
Host smart-0f0ca515-f6bd-4ce7-b48e-e8ac3b2a57ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970392309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.970392309
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.523699403
Short name T9
Test name
Test status
Simulation time 3666279782 ps
CPU time 9.57 seconds
Started May 21 02:40:47 PM PDT 24
Finished May 21 02:41:08 PM PDT 24
Peak memory 201604 kb
Host smart-00a96d5f-5fb9-44bf-9378-f627dce4e1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523699403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.523699403
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.1874544930
Short name T33
Test name
Test status
Simulation time 5672144484 ps
CPU time 14.39 seconds
Started May 21 02:40:45 PM PDT 24
Finished May 21 02:41:09 PM PDT 24
Peak memory 201700 kb
Host smart-cf8d29f5-e64c-4cfc-a008-308543eaadd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874544930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1874544930
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1220764654
Short name T420
Test name
Test status
Simulation time 103972860831 ps
CPU time 96.25 seconds
Started May 21 02:40:46 PM PDT 24
Finished May 21 02:42:33 PM PDT 24
Peak memory 210516 kb
Host smart-7341072f-3f85-4f19-9552-ce34f2c0a4c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220764654 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1220764654
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.146796637
Short name T497
Test name
Test status
Simulation time 499261531 ps
CPU time 1.75 seconds
Started May 21 02:40:45 PM PDT 24
Finished May 21 02:40:55 PM PDT 24
Peak memory 201484 kb
Host smart-238a3bbc-151c-452e-b39a-6bb76c90f212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146796637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.146796637
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3722127315
Short name T150
Test name
Test status
Simulation time 160969447927 ps
CPU time 29.51 seconds
Started May 21 02:40:52 PM PDT 24
Finished May 21 02:41:37 PM PDT 24
Peak memory 201844 kb
Host smart-a987cc15-3eb4-4d4c-9c7d-6e8c2137f80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722127315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3722127315
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1592504502
Short name T447
Test name
Test status
Simulation time 161739030817 ps
CPU time 34.87 seconds
Started May 21 02:40:48 PM PDT 24
Finished May 21 02:41:35 PM PDT 24
Peak memory 201844 kb
Host smart-7d33351f-3a3f-4b99-a63b-3456446d91fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592504502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1592504502
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2422642606
Short name T595
Test name
Test status
Simulation time 165888807608 ps
CPU time 360.24 seconds
Started May 21 02:40:52 PM PDT 24
Finished May 21 02:47:08 PM PDT 24
Peak memory 201872 kb
Host smart-00a4dd32-800d-4ba9-bc84-f098d951b82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422642606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2422642606
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1607651754
Short name T98
Test name
Test status
Simulation time 321466193968 ps
CPU time 367.83 seconds
Started May 21 02:40:52 PM PDT 24
Finished May 21 02:47:15 PM PDT 24
Peak memory 201860 kb
Host smart-026cdd0b-2c58-444e-a800-4b1e3ab6c371
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607651754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1607651754
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2989388076
Short name T361
Test name
Test status
Simulation time 196545102055 ps
CPU time 502.41 seconds
Started May 21 02:40:44 PM PDT 24
Finished May 21 02:49:15 PM PDT 24
Peak memory 202044 kb
Host smart-d9747125-3d5d-467c-bb30-f7d7a385ea5e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989388076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.2989388076
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2422538254
Short name T757
Test name
Test status
Simulation time 37604358450 ps
CPU time 22.81 seconds
Started May 21 02:40:45 PM PDT 24
Finished May 21 02:41:16 PM PDT 24
Peak memory 201684 kb
Host smart-b1670b62-a373-49d1-b620-d8e620d9e03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422538254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2422538254
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2904222292
Short name T787
Test name
Test status
Simulation time 5251386083 ps
CPU time 13.38 seconds
Started May 21 02:40:47 PM PDT 24
Finished May 21 02:41:12 PM PDT 24
Peak memory 201680 kb
Host smart-4a262e0b-4700-4bc7-b24e-bec0ccd3f121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904222292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2904222292
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1991537418
Short name T469
Test name
Test status
Simulation time 6031018007 ps
CPU time 4.16 seconds
Started May 21 02:40:44 PM PDT 24
Finished May 21 02:40:56 PM PDT 24
Peak memory 201676 kb
Host smart-cb619b79-fa1d-425d-a6ae-4c64747d1f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991537418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1991537418
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1724006594
Short name T735
Test name
Test status
Simulation time 178491625881 ps
CPU time 57.73 seconds
Started May 21 02:40:52 PM PDT 24
Finished May 21 02:42:05 PM PDT 24
Peak memory 210188 kb
Host smart-53370289-c2d4-494a-9d44-cf1a4d0a9131
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724006594 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1724006594
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.244715955
Short name T479
Test name
Test status
Simulation time 501862927 ps
CPU time 0.9 seconds
Started May 21 02:40:46 PM PDT 24
Finished May 21 02:40:57 PM PDT 24
Peak memory 201496 kb
Host smart-bb05f30a-1b6a-4190-a3dd-a94d731f0799
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244715955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.244715955
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3620181471
Short name T279
Test name
Test status
Simulation time 462846412766 ps
CPU time 823.78 seconds
Started May 21 02:40:49 PM PDT 24
Finished May 21 02:54:47 PM PDT 24
Peak memory 201836 kb
Host smart-a005dcf1-22d4-4be4-bf94-a3754bf952ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620181471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3620181471
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3021803621
Short name T509
Test name
Test status
Simulation time 164527519464 ps
CPU time 179.64 seconds
Started May 21 02:40:46 PM PDT 24
Finished May 21 02:43:56 PM PDT 24
Peak memory 201884 kb
Host smart-6108eb4a-f439-4e87-8641-9e3a413a51cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021803621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3021803621
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3500065329
Short name T144
Test name
Test status
Simulation time 496000797991 ps
CPU time 196.68 seconds
Started May 21 02:40:48 PM PDT 24
Finished May 21 02:44:17 PM PDT 24
Peak memory 201940 kb
Host smart-975d6b05-989c-4b08-a373-7cc857832921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500065329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3500065329
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.37813987
Short name T594
Test name
Test status
Simulation time 494546271159 ps
CPU time 310.97 seconds
Started May 21 02:40:46 PM PDT 24
Finished May 21 02:46:09 PM PDT 24
Peak memory 201860 kb
Host smart-f9491ba6-0618-4802-b437-0e85075a0371
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=37813987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt
_fixed.37813987
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1761110357
Short name T298
Test name
Test status
Simulation time 492143391742 ps
CPU time 290.91 seconds
Started May 21 02:40:46 PM PDT 24
Finished May 21 02:45:47 PM PDT 24
Peak memory 201784 kb
Host smart-debc8fc6-e1fe-47ad-861a-e55f6350a2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761110357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1761110357
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2503439346
Short name T737
Test name
Test status
Simulation time 493754175769 ps
CPU time 1097.64 seconds
Started May 21 02:40:52 PM PDT 24
Finished May 21 02:59:25 PM PDT 24
Peak memory 201840 kb
Host smart-13dfa959-c1d0-414c-b4de-47a575195f11
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503439346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2503439346
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.877074043
Short name T739
Test name
Test status
Simulation time 181466928981 ps
CPU time 196.86 seconds
Started May 21 02:40:52 PM PDT 24
Finished May 21 02:44:24 PM PDT 24
Peak memory 201944 kb
Host smart-b5011df4-7ffe-4a17-9fc4-ba62e0b0425d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877074043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.877074043
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1185755329
Short name T503
Test name
Test status
Simulation time 386313466488 ps
CPU time 961.31 seconds
Started May 21 02:40:49 PM PDT 24
Finished May 21 02:57:04 PM PDT 24
Peak memory 201848 kb
Host smart-55eeec48-62c4-4d29-a29b-7233bc4d7ea2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185755329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1185755329
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3715396847
Short name T346
Test name
Test status
Simulation time 96781755127 ps
CPU time 390.72 seconds
Started May 21 02:40:45 PM PDT 24
Finished May 21 02:47:25 PM PDT 24
Peak memory 202184 kb
Host smart-22b5748c-10fb-4a04-9cc4-b583e0621dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715396847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3715396847
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2975627775
Short name T458
Test name
Test status
Simulation time 44510371238 ps
CPU time 13.07 seconds
Started May 21 02:40:46 PM PDT 24
Finished May 21 02:41:08 PM PDT 24
Peak memory 201620 kb
Host smart-9dea3dc1-9515-4c04-bd13-97a7230bd552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975627775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2975627775
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.741783696
Short name T406
Test name
Test status
Simulation time 3087584134 ps
CPU time 5.27 seconds
Started May 21 02:41:08 PM PDT 24
Finished May 21 02:41:27 PM PDT 24
Peak memory 201612 kb
Host smart-9124a372-474f-4d3e-8da0-9e398cbd9d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741783696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.741783696
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2664067456
Short name T209
Test name
Test status
Simulation time 5584986942 ps
CPU time 7.3 seconds
Started May 21 02:40:46 PM PDT 24
Finished May 21 02:41:04 PM PDT 24
Peak memory 201672 kb
Host smart-6541f384-be44-44b2-ba5f-fed8794a303c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664067456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2664067456
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.57962893
Short name T312
Test name
Test status
Simulation time 281606617652 ps
CPU time 287.11 seconds
Started May 21 02:40:45 PM PDT 24
Finished May 21 02:45:40 PM PDT 24
Peak memory 210428 kb
Host smart-4972dcbf-8071-4ce7-9416-cc940c9a1ab2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57962893 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.57962893
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3863815146
Short name T121
Test name
Test status
Simulation time 421672432 ps
CPU time 1.13 seconds
Started May 21 02:40:53 PM PDT 24
Finished May 21 02:41:10 PM PDT 24
Peak memory 201548 kb
Host smart-bb85d0cb-a030-4e9d-bb13-b79dd713b088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863815146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3863815146
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1171641122
Short name T192
Test name
Test status
Simulation time 355322454066 ps
CPU time 130.9 seconds
Started May 21 02:40:52 PM PDT 24
Finished May 21 02:43:19 PM PDT 24
Peak memory 201852 kb
Host smart-5c35bd07-a175-4306-97f6-6b7d04b7158c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171641122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1171641122
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3014136239
Short name T231
Test name
Test status
Simulation time 535219291299 ps
CPU time 1200.28 seconds
Started May 21 02:40:55 PM PDT 24
Finished May 21 03:01:11 PM PDT 24
Peak memory 201868 kb
Host smart-af95ff24-385d-4e54-8410-eb012ce501e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014136239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3014136239
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3268729383
Short name T675
Test name
Test status
Simulation time 489349366674 ps
CPU time 569.46 seconds
Started May 21 02:40:52 PM PDT 24
Finished May 21 02:50:37 PM PDT 24
Peak memory 201856 kb
Host smart-a25ccd13-1a31-4e6a-b5e9-ce7248e176b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268729383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3268729383
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.151982436
Short name T360
Test name
Test status
Simulation time 329552846453 ps
CPU time 203.01 seconds
Started May 21 02:41:07 PM PDT 24
Finished May 21 02:44:45 PM PDT 24
Peak memory 201808 kb
Host smart-02e0de78-6c16-4d32-bcec-00a8f9b35038
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=151982436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.151982436
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2957728217
Short name T274
Test name
Test status
Simulation time 490072898609 ps
CPU time 1177.75 seconds
Started May 21 02:40:54 PM PDT 24
Finished May 21 03:00:47 PM PDT 24
Peak memory 201896 kb
Host smart-475a9b58-2ad7-40f9-944a-30dd345aff91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957728217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2957728217
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2981153360
Short name T425
Test name
Test status
Simulation time 495068020123 ps
CPU time 325.31 seconds
Started May 21 02:40:52 PM PDT 24
Finished May 21 02:46:33 PM PDT 24
Peak memory 201892 kb
Host smart-6d86f2ef-c999-4864-9278-308308ec92c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981153360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2981153360
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2971422042
Short name T258
Test name
Test status
Simulation time 371850380928 ps
CPU time 409.35 seconds
Started May 21 02:40:56 PM PDT 24
Finished May 21 02:48:01 PM PDT 24
Peak memory 201876 kb
Host smart-9480039a-6d3e-4a7d-89d5-1d34f446159a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971422042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2971422042
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2336719215
Short name T637
Test name
Test status
Simulation time 597862108032 ps
CPU time 381.28 seconds
Started May 21 02:40:52 PM PDT 24
Finished May 21 02:47:29 PM PDT 24
Peak memory 201812 kb
Host smart-726d13af-51d6-4d1e-a005-e059b63f26fc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336719215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2336719215
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3185047358
Short name T626
Test name
Test status
Simulation time 28114800856 ps
CPU time 5.5 seconds
Started May 21 02:40:54 PM PDT 24
Finished May 21 02:41:15 PM PDT 24
Peak memory 201708 kb
Host smart-5462db0f-dea2-47cc-a5a9-3ffb5eae0ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185047358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3185047358
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.736425839
Short name T777
Test name
Test status
Simulation time 3095757071 ps
CPU time 2.35 seconds
Started May 21 02:40:50 PM PDT 24
Finished May 21 02:41:07 PM PDT 24
Peak memory 201604 kb
Host smart-c6a9d980-318e-4912-878e-601b420cbae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736425839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.736425839
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2433317218
Short name T7
Test name
Test status
Simulation time 5814854113 ps
CPU time 7.54 seconds
Started May 21 02:40:53 PM PDT 24
Finished May 21 02:41:16 PM PDT 24
Peak memory 201656 kb
Host smart-00cd2438-5394-4be9-beca-92c35a95106a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433317218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2433317218
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2782839323
Short name T88
Test name
Test status
Simulation time 432372310 ps
CPU time 1.54 seconds
Started May 21 02:40:53 PM PDT 24
Finished May 21 02:41:10 PM PDT 24
Peak memory 201740 kb
Host smart-9012d3b8-c5eb-4488-81fb-08204e276e0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782839323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2782839323
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2067191364
Short name T233
Test name
Test status
Simulation time 333631311507 ps
CPU time 229.98 seconds
Started May 21 02:40:55 PM PDT 24
Finished May 21 02:45:01 PM PDT 24
Peak memory 201884 kb
Host smart-b8578e2c-ac84-4a7c-b42f-03d87a1e80ac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067191364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2067191364
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.4160284320
Short name T740
Test name
Test status
Simulation time 172603737911 ps
CPU time 186.17 seconds
Started May 21 02:41:09 PM PDT 24
Finished May 21 02:44:29 PM PDT 24
Peak memory 201840 kb
Host smart-5c50f1b2-12b8-4250-90fa-69ce75e48916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160284320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.4160284320
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.714431739
Short name T628
Test name
Test status
Simulation time 491034443542 ps
CPU time 1193.16 seconds
Started May 21 02:40:51 PM PDT 24
Finished May 21 03:00:58 PM PDT 24
Peak memory 201864 kb
Host smart-5dd89ee5-aeaa-47b2-bc42-ac30bc3c0ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714431739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.714431739
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.276986638
Short name T577
Test name
Test status
Simulation time 161609535082 ps
CPU time 85.63 seconds
Started May 21 02:40:53 PM PDT 24
Finished May 21 02:42:34 PM PDT 24
Peak memory 201836 kb
Host smart-75a883fe-ad7e-44fc-9d9b-1ec2af56ef2d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=276986638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrup
t_fixed.276986638
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2003453094
Short name T668
Test name
Test status
Simulation time 490965500664 ps
CPU time 1077.73 seconds
Started May 21 02:40:49 PM PDT 24
Finished May 21 02:59:01 PM PDT 24
Peak memory 201904 kb
Host smart-8c2d1d0e-065a-4d4d-bb5d-029ca2491fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003453094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2003453094
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2024254407
Short name T443
Test name
Test status
Simulation time 165124589386 ps
CPU time 30.8 seconds
Started May 21 02:40:51 PM PDT 24
Finished May 21 02:41:38 PM PDT 24
Peak memory 201820 kb
Host smart-caf74227-977e-4044-877e-aef7f24363da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024254407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2024254407
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3286133860
Short name T333
Test name
Test status
Simulation time 527844721946 ps
CPU time 225.61 seconds
Started May 21 02:40:55 PM PDT 24
Finished May 21 02:44:56 PM PDT 24
Peak memory 201932 kb
Host smart-608fa663-852e-4dbb-a99b-51027cc2d5cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286133860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3286133860
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2649256919
Short name T642
Test name
Test status
Simulation time 614781109544 ps
CPU time 358.34 seconds
Started May 21 02:40:53 PM PDT 24
Finished May 21 02:47:07 PM PDT 24
Peak memory 201916 kb
Host smart-0076f881-e44e-45d3-8485-bff53b669cf5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649256919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2649256919
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.462788599
Short name T496
Test name
Test status
Simulation time 38986560758 ps
CPU time 13.28 seconds
Started May 21 02:40:56 PM PDT 24
Finished May 21 02:41:25 PM PDT 24
Peak memory 201700 kb
Host smart-04b6f610-a212-4890-9a83-e611360f29db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462788599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.462788599
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2232427252
Short name T549
Test name
Test status
Simulation time 3989816829 ps
CPU time 3.21 seconds
Started May 21 02:40:53 PM PDT 24
Finished May 21 02:41:12 PM PDT 24
Peak memory 201632 kb
Host smart-e82785fa-126e-4f97-9af0-1d9351605281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232427252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2232427252
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3722850220
Short name T575
Test name
Test status
Simulation time 6069085656 ps
CPU time 14.04 seconds
Started May 21 02:40:52 PM PDT 24
Finished May 21 02:41:22 PM PDT 24
Peak memory 201660 kb
Host smart-5c0cfdeb-9be0-4cfa-9e68-18c657d7583c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722850220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3722850220
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1912263330
Short name T278
Test name
Test status
Simulation time 327912489071 ps
CPU time 791.83 seconds
Started May 21 02:40:54 PM PDT 24
Finished May 21 02:54:21 PM PDT 24
Peak memory 201936 kb
Host smart-d5acadf3-3487-42e3-9e8e-3904a99fe2c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912263330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1912263330
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3694415029
Short name T508
Test name
Test status
Simulation time 455395717 ps
CPU time 1.33 seconds
Started May 21 02:40:57 PM PDT 24
Finished May 21 02:41:15 PM PDT 24
Peak memory 201576 kb
Host smart-94e5165e-f4e3-4377-a072-24fe7ace7a47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694415029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3694415029
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2759702109
Short name T747
Test name
Test status
Simulation time 378978825626 ps
CPU time 420.94 seconds
Started May 21 02:40:51 PM PDT 24
Finished May 21 02:48:06 PM PDT 24
Peak memory 201768 kb
Host smart-2e333f61-3640-4c48-acf8-0b71240b4851
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759702109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2759702109
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2786552876
Short name T149
Test name
Test status
Simulation time 166115826454 ps
CPU time 101.86 seconds
Started May 21 02:40:55 PM PDT 24
Finished May 21 02:42:53 PM PDT 24
Peak memory 201876 kb
Host smart-555d86aa-755a-4b79-be07-9bdbd139db6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786552876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2786552876
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2629657529
Short name T399
Test name
Test status
Simulation time 335242026583 ps
CPU time 706.38 seconds
Started May 21 02:40:52 PM PDT 24
Finished May 21 02:52:54 PM PDT 24
Peak memory 201768 kb
Host smart-f743575d-7e43-4e0d-b8d4-c0ff1af5c11d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629657529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2629657529
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3703499568
Short name T271
Test name
Test status
Simulation time 498134876048 ps
CPU time 1095.59 seconds
Started May 21 02:41:07 PM PDT 24
Finished May 21 02:59:37 PM PDT 24
Peak memory 201808 kb
Host smart-97b2529f-d5eb-4fb2-9c12-71b9c807877d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703499568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3703499568
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2068551119
Short name T371
Test name
Test status
Simulation time 330975548178 ps
CPU time 377.16 seconds
Started May 21 02:40:55 PM PDT 24
Finished May 21 02:47:27 PM PDT 24
Peak memory 201828 kb
Host smart-a5245e35-464d-4c40-9433-e1c2b2e73f44
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068551119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2068551119
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2657470608
Short name T120
Test name
Test status
Simulation time 189689027316 ps
CPU time 106.29 seconds
Started May 21 02:40:50 PM PDT 24
Finished May 21 02:42:51 PM PDT 24
Peak memory 201856 kb
Host smart-0b5b516e-a163-40f7-b8e1-37d5efbab9ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657470608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2657470608
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.165327209
Short name T491
Test name
Test status
Simulation time 198356961209 ps
CPU time 163.8 seconds
Started May 21 02:41:09 PM PDT 24
Finished May 21 02:44:06 PM PDT 24
Peak memory 201824 kb
Host smart-6dcf54a9-3a6a-4896-8fb5-ce1f69277f9e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165327209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.165327209
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.544899867
Short name T495
Test name
Test status
Simulation time 44215069007 ps
CPU time 102.68 seconds
Started May 21 02:40:59 PM PDT 24
Finished May 21 02:42:58 PM PDT 24
Peak memory 201668 kb
Host smart-d0b30c1c-c2ea-42f9-aedf-b8baf448ffc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544899867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.544899867
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.3046650343
Short name T630
Test name
Test status
Simulation time 3705320556 ps
CPU time 5.33 seconds
Started May 21 02:40:53 PM PDT 24
Finished May 21 02:41:14 PM PDT 24
Peak memory 201608 kb
Host smart-31ab24c1-2612-446c-bee0-1ccb1f57f37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046650343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3046650343
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.4030427481
Short name T763
Test name
Test status
Simulation time 5912362877 ps
CPU time 8.54 seconds
Started May 21 02:40:51 PM PDT 24
Finished May 21 02:41:14 PM PDT 24
Peak memory 201664 kb
Host smart-9286f72b-7418-456c-a464-204c735c4884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030427481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.4030427481
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2951481927
Short name T116
Test name
Test status
Simulation time 420674959445 ps
CPU time 59.03 seconds
Started May 21 02:40:57 PM PDT 24
Finished May 21 02:42:12 PM PDT 24
Peak memory 201872 kb
Host smart-4252a0a7-2415-467b-afa2-5a6b685a2ddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951481927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2951481927
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.412830228
Short name T533
Test name
Test status
Simulation time 415096094 ps
CPU time 0.9 seconds
Started May 21 02:40:59 PM PDT 24
Finished May 21 02:41:15 PM PDT 24
Peak memory 201552 kb
Host smart-d84b6cbc-69cc-420b-a5e4-a384cc49d416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412830228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.412830228
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.297285245
Short name T173
Test name
Test status
Simulation time 348115768767 ps
CPU time 423.3 seconds
Started May 21 02:40:56 PM PDT 24
Finished May 21 02:48:17 PM PDT 24
Peak memory 201824 kb
Host smart-54668f08-1f6c-45c3-93be-6503eb5036a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297285245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.297285245
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1193367298
Short name T109
Test name
Test status
Simulation time 185243860593 ps
CPU time 36.49 seconds
Started May 21 02:40:55 PM PDT 24
Finished May 21 02:41:49 PM PDT 24
Peak memory 201780 kb
Host smart-623d03e8-4704-41c9-904b-e32313bd8527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193367298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1193367298
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3733748314
Short name T616
Test name
Test status
Simulation time 165066097230 ps
CPU time 187.18 seconds
Started May 21 02:40:55 PM PDT 24
Finished May 21 02:44:19 PM PDT 24
Peak memory 201788 kb
Host smart-a19e74c0-4323-43c6-8ca2-c437247e60f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733748314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3733748314
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.49929228
Short name T409
Test name
Test status
Simulation time 163725414425 ps
CPU time 101.1 seconds
Started May 21 02:40:58 PM PDT 24
Finished May 21 02:42:55 PM PDT 24
Peak memory 201836 kb
Host smart-094c1fb5-50e2-404b-b793-2fb49c774c3c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=49929228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt
_fixed.49929228
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2422423608
Short name T42
Test name
Test status
Simulation time 486694589956 ps
CPU time 1158.97 seconds
Started May 21 02:40:56 PM PDT 24
Finished May 21 03:00:33 PM PDT 24
Peak memory 201804 kb
Host smart-b5077189-d275-49cd-8529-6fa1f39aebc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422423608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2422423608
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.958746495
Short name T410
Test name
Test status
Simulation time 503533561266 ps
CPU time 1149.96 seconds
Started May 21 02:40:57 PM PDT 24
Finished May 21 03:00:23 PM PDT 24
Peak memory 201848 kb
Host smart-3bd802c4-1f71-4994-8bd5-98e1cfd8ed0d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=958746495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.958746495
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.340808326
Short name T203
Test name
Test status
Simulation time 365494201071 ps
CPU time 201.43 seconds
Started May 21 02:40:57 PM PDT 24
Finished May 21 02:44:35 PM PDT 24
Peak memory 202040 kb
Host smart-62c7a551-7de4-42b3-a3a7-221f9ee34c1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340808326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.340808326
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.647705568
Short name T666
Test name
Test status
Simulation time 406814389428 ps
CPU time 783.89 seconds
Started May 21 02:40:55 PM PDT 24
Finished May 21 02:54:16 PM PDT 24
Peak memory 201876 kb
Host smart-eb43fdd4-6cd3-4855-bcf1-3f32e2a62950
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647705568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.647705568
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.69544852
Short name T215
Test name
Test status
Simulation time 102914043515 ps
CPU time 382.59 seconds
Started May 21 02:41:00 PM PDT 24
Finished May 21 02:47:38 PM PDT 24
Peak memory 202228 kb
Host smart-4151319c-f280-4304-86e3-d7cec7696cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69544852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.69544852
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.2168909866
Short name T604
Test name
Test status
Simulation time 38251054646 ps
CPU time 24.01 seconds
Started May 21 02:40:56 PM PDT 24
Finished May 21 02:41:38 PM PDT 24
Peak memory 201660 kb
Host smart-759b7122-0c3b-47af-852e-18fdec13c6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168909866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.2168909866
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.739884530
Short name T354
Test name
Test status
Simulation time 4304704535 ps
CPU time 10.52 seconds
Started May 21 02:40:56 PM PDT 24
Finished May 21 02:41:23 PM PDT 24
Peak memory 201656 kb
Host smart-e64c22f2-0373-4222-9480-f41217dd1019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739884530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.739884530
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1314605165
Short name T8
Test name
Test status
Simulation time 5491473046 ps
CPU time 13.55 seconds
Started May 21 02:41:07 PM PDT 24
Finished May 21 02:41:35 PM PDT 24
Peak memory 201656 kb
Host smart-6806e8a2-a767-4aed-971f-4f322ee34f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314605165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1314605165
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.356643697
Short name T391
Test name
Test status
Simulation time 255095517569 ps
CPU time 443.76 seconds
Started May 21 02:40:56 PM PDT 24
Finished May 21 02:48:36 PM PDT 24
Peak memory 210464 kb
Host smart-fbdfe717-c691-449a-8833-dc90c1dad3f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356643697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
356643697
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1827358087
Short name T77
Test name
Test status
Simulation time 170290624411 ps
CPU time 213.15 seconds
Started May 21 02:41:09 PM PDT 24
Finished May 21 02:44:56 PM PDT 24
Peak memory 211560 kb
Host smart-c334d5ce-5170-4dc5-b10f-04378064d34b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827358087 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1827358087
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.2761648881
Short name T623
Test name
Test status
Simulation time 503923291 ps
CPU time 1.22 seconds
Started May 21 02:41:22 PM PDT 24
Finished May 21 02:41:32 PM PDT 24
Peak memory 201552 kb
Host smart-5842bf77-35c4-4b21-ae68-1a097f7bbf85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761648881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2761648881
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2705472058
Short name T102
Test name
Test status
Simulation time 162845297703 ps
CPU time 107.46 seconds
Started May 21 02:41:10 PM PDT 24
Finished May 21 02:43:11 PM PDT 24
Peak memory 201852 kb
Host smart-a4556f3b-fd1a-412f-b366-be00bee05d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705472058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2705472058
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3966111045
Short name T697
Test name
Test status
Simulation time 329335774596 ps
CPU time 753.64 seconds
Started May 21 02:41:02 PM PDT 24
Finished May 21 02:53:51 PM PDT 24
Peak memory 201832 kb
Host smart-aab14bba-642a-4e03-a776-bd1cf9168c25
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966111045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3966111045
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3337505715
Short name T300
Test name
Test status
Simulation time 499619599448 ps
CPU time 462.24 seconds
Started May 21 02:41:02 PM PDT 24
Finished May 21 02:49:00 PM PDT 24
Peak memory 201880 kb
Host smart-9555ef9f-c518-4725-9757-b920f3d7f1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337505715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3337505715
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3866585438
Short name T436
Test name
Test status
Simulation time 496212998058 ps
CPU time 1260.7 seconds
Started May 21 02:41:09 PM PDT 24
Finished May 21 03:02:24 PM PDT 24
Peak memory 201808 kb
Host smart-d20f3645-1417-48c0-b460-2ccca530c1ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866585438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3866585438
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3597619684
Short name T738
Test name
Test status
Simulation time 527498170053 ps
CPU time 227.46 seconds
Started May 21 02:41:03 PM PDT 24
Finished May 21 02:45:06 PM PDT 24
Peak memory 201860 kb
Host smart-59e6e1c6-e73a-401d-b707-c8dab5fe6d18
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597619684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3597619684
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2025773210
Short name T452
Test name
Test status
Simulation time 403723134586 ps
CPU time 977.16 seconds
Started May 21 02:41:10 PM PDT 24
Finished May 21 02:57:40 PM PDT 24
Peak memory 201836 kb
Host smart-283b92fe-9e20-4020-9a44-99fdad53dc97
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025773210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2025773210
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3003513650
Short name T691
Test name
Test status
Simulation time 72998146563 ps
CPU time 286.76 seconds
Started May 21 02:41:10 PM PDT 24
Finished May 21 02:46:11 PM PDT 24
Peak memory 202248 kb
Host smart-617b0f52-81df-4313-ae1d-190ceeeacdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003513650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3003513650
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3310757720
Short name T511
Test name
Test status
Simulation time 42543351254 ps
CPU time 95.88 seconds
Started May 21 02:41:10 PM PDT 24
Finished May 21 02:43:00 PM PDT 24
Peak memory 201676 kb
Host smart-482bb57e-6a3e-4be0-9c08-425208164e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310757720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3310757720
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3012632319
Short name T674
Test name
Test status
Simulation time 3880737185 ps
CPU time 5.49 seconds
Started May 21 02:41:03 PM PDT 24
Finished May 21 02:41:23 PM PDT 24
Peak memory 201640 kb
Host smart-fda04fac-b1d0-4974-9350-f600dbb318e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012632319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3012632319
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3819937537
Short name T401
Test name
Test status
Simulation time 6133925635 ps
CPU time 7.67 seconds
Started May 21 02:41:03 PM PDT 24
Finished May 21 02:41:26 PM PDT 24
Peak memory 201676 kb
Host smart-5af663a1-64be-46bb-ad61-6c14e5e45629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819937537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3819937537
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1736303860
Short name T645
Test name
Test status
Simulation time 37697966336 ps
CPU time 88.65 seconds
Started May 21 02:41:13 PM PDT 24
Finished May 21 02:42:54 PM PDT 24
Peak memory 201676 kb
Host smart-5b2b1942-4748-4da2-b9a1-e139a0109adf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736303860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1736303860
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2456949738
Short name T35
Test name
Test status
Simulation time 28251467085 ps
CPU time 47.48 seconds
Started May 21 02:41:11 PM PDT 24
Finished May 21 02:42:12 PM PDT 24
Peak memory 210452 kb
Host smart-3e801848-e4f9-44dc-b235-9048e5cb2c04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456949738 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2456949738
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1013630452
Short name T698
Test name
Test status
Simulation time 382611377 ps
CPU time 1.44 seconds
Started May 21 02:41:15 PM PDT 24
Finished May 21 02:41:28 PM PDT 24
Peak memory 201496 kb
Host smart-1fd75c5e-a9af-402d-af77-5e062372ef92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013630452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1013630452
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1457618446
Short name T255
Test name
Test status
Simulation time 348552218513 ps
CPU time 864.98 seconds
Started May 21 02:41:22 PM PDT 24
Finished May 21 02:55:56 PM PDT 24
Peak memory 201852 kb
Host smart-69270005-cf73-4ed0-8416-0536079d4984
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457618446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1457618446
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2807438346
Short name T297
Test name
Test status
Simulation time 341416783622 ps
CPU time 716.43 seconds
Started May 21 02:41:22 PM PDT 24
Finished May 21 02:53:28 PM PDT 24
Peak memory 201916 kb
Host smart-0875fa8f-4ebd-43af-b388-8c5f3f52ddd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807438346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2807438346
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.4067914693
Short name T238
Test name
Test status
Simulation time 488565215712 ps
CPU time 324.02 seconds
Started May 21 02:41:13 PM PDT 24
Finished May 21 02:46:49 PM PDT 24
Peak memory 201824 kb
Host smart-5c69880b-9fad-471c-9c4c-b409d1ad606c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067914693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.4067914693
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2295633010
Short name T523
Test name
Test status
Simulation time 166680488368 ps
CPU time 99.49 seconds
Started May 21 02:41:13 PM PDT 24
Finished May 21 02:43:04 PM PDT 24
Peak memory 201828 kb
Host smart-9d47d63c-368b-47be-bda5-990729242d85
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295633010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2295633010
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.4142689587
Short name T43
Test name
Test status
Simulation time 500035740734 ps
CPU time 991.37 seconds
Started May 21 02:41:11 PM PDT 24
Finished May 21 02:57:56 PM PDT 24
Peak memory 201852 kb
Host smart-10a53360-90fa-4f8c-9f90-dabc824d37d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142689587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.4142689587
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2277681404
Short name T468
Test name
Test status
Simulation time 332659025969 ps
CPU time 483.56 seconds
Started May 21 02:41:13 PM PDT 24
Finished May 21 02:49:29 PM PDT 24
Peak memory 201828 kb
Host smart-13042a27-3628-4e38-8c4d-eaee20a9d595
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277681404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2277681404
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3836252535
Short name T10
Test name
Test status
Simulation time 403573497908 ps
CPU time 961.04 seconds
Started May 21 02:41:16 PM PDT 24
Finished May 21 02:57:29 PM PDT 24
Peak memory 201928 kb
Host smart-47592871-f2d0-4385-9c01-ec30d8fd1e4b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836252535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3836252535
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1002016558
Short name T742
Test name
Test status
Simulation time 74347408845 ps
CPU time 382.06 seconds
Started May 21 02:41:23 PM PDT 24
Finished May 21 02:47:54 PM PDT 24
Peak memory 202156 kb
Host smart-42e1b349-f1af-4217-b1de-c7a10628455c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002016558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1002016558
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2356465800
Short name T680
Test name
Test status
Simulation time 38653284661 ps
CPU time 41.62 seconds
Started May 21 02:41:15 PM PDT 24
Finished May 21 02:42:08 PM PDT 24
Peak memory 201668 kb
Host smart-02b5140b-fede-43fb-aea5-1299f2684f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356465800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2356465800
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2106356647
Short name T456
Test name
Test status
Simulation time 5016224387 ps
CPU time 1.87 seconds
Started May 21 02:41:17 PM PDT 24
Finished May 21 02:41:30 PM PDT 24
Peak memory 201588 kb
Host smart-1aa04737-2ee3-4ea0-86fc-4c02af8bc9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106356647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2106356647
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1884285428
Short name T28
Test name
Test status
Simulation time 5971290756 ps
CPU time 7.99 seconds
Started May 21 02:41:13 PM PDT 24
Finished May 21 02:41:33 PM PDT 24
Peak memory 201700 kb
Host smart-5e4991e3-d979-435f-a4f6-54bd9fcca2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884285428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1884285428
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2824050815
Short name T310
Test name
Test status
Simulation time 657955247375 ps
CPU time 538.34 seconds
Started May 21 02:41:15 PM PDT 24
Finished May 21 02:50:25 PM PDT 24
Peak memory 210384 kb
Host smart-8fd6054a-f32d-4002-8502-a82411f6bbc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824050815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2824050815
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.250353210
Short name T59
Test name
Test status
Simulation time 21303746415 ps
CPU time 16.9 seconds
Started May 21 02:41:23 PM PDT 24
Finished May 21 02:41:48 PM PDT 24
Peak memory 201960 kb
Host smart-0b42dfef-647d-477c-bfbc-b49bb0f3c146
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250353210 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.250353210
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.638959899
Short name T541
Test name
Test status
Simulation time 322518162 ps
CPU time 0.73 seconds
Started May 21 02:40:01 PM PDT 24
Finished May 21 02:40:14 PM PDT 24
Peak memory 201544 kb
Host smart-f4fba0d1-de04-418e-a73a-25d2730aa2f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638959899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.638959899
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1565442887
Short name T717
Test name
Test status
Simulation time 173130378557 ps
CPU time 149.75 seconds
Started May 21 02:39:55 PM PDT 24
Finished May 21 02:42:40 PM PDT 24
Peak memory 201840 kb
Host smart-bbc4bd88-beda-44e4-a815-9153a206158f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565442887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1565442887
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1467053643
Short name T155
Test name
Test status
Simulation time 352411061846 ps
CPU time 212.68 seconds
Started May 21 02:39:54 PM PDT 24
Finished May 21 02:43:42 PM PDT 24
Peak memory 201912 kb
Host smart-83e00781-fdfa-4f74-a034-2d5ae04c2850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467053643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1467053643
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2875086935
Short name T292
Test name
Test status
Simulation time 483446913692 ps
CPU time 1082.36 seconds
Started May 21 02:39:55 PM PDT 24
Finished May 21 02:58:13 PM PDT 24
Peak memory 201840 kb
Host smart-1fcbac32-f328-47b6-bf7c-c767c4881df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875086935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2875086935
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.4037276392
Short name T202
Test name
Test status
Simulation time 501566356505 ps
CPU time 298.4 seconds
Started May 21 02:41:08 PM PDT 24
Finished May 21 02:46:21 PM PDT 24
Peak memory 201804 kb
Host smart-e7b97040-99de-4853-8d6e-df245a7bbf1c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037276392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.4037276392
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.454561318
Short name T724
Test name
Test status
Simulation time 165052117235 ps
CPU time 356.85 seconds
Started May 21 02:39:57 PM PDT 24
Finished May 21 02:46:09 PM PDT 24
Peak memory 201764 kb
Host smart-78b95634-468c-43d5-915f-ae4e91a0f8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454561318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.454561318
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3087934239
Short name T632
Test name
Test status
Simulation time 499509968752 ps
CPU time 590.76 seconds
Started May 21 02:39:56 PM PDT 24
Finished May 21 02:50:02 PM PDT 24
Peak memory 201908 kb
Host smart-7ade7ae4-b864-4dd5-9f90-e9a55aa22b44
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087934239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3087934239
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2870874055
Short name T375
Test name
Test status
Simulation time 396826347966 ps
CPU time 940.34 seconds
Started May 21 02:39:57 PM PDT 24
Finished May 21 02:55:52 PM PDT 24
Peak memory 201860 kb
Host smart-719c6f8f-15d9-45f8-be48-8376dc74ae83
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870874055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2870874055
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3646403912
Short name T44
Test name
Test status
Simulation time 121895348041 ps
CPU time 595.21 seconds
Started May 21 02:39:57 PM PDT 24
Finished May 21 02:50:07 PM PDT 24
Peak memory 202160 kb
Host smart-c0271014-36b2-4946-8f69-757b2bed3f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646403912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3646403912
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.389778650
Short name T672
Test name
Test status
Simulation time 41289035290 ps
CPU time 93.28 seconds
Started May 21 02:39:56 PM PDT 24
Finished May 21 02:41:44 PM PDT 24
Peak memory 201708 kb
Host smart-6f10368d-2617-467b-9031-be5c38520379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389778650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.389778650
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.430564993
Short name T517
Test name
Test status
Simulation time 4437354986 ps
CPU time 6.67 seconds
Started May 21 02:39:57 PM PDT 24
Finished May 21 02:40:18 PM PDT 24
Peak memory 201704 kb
Host smart-1b103430-8310-403a-8c97-d8314a11bae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430564993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.430564993
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2215193406
Short name T95
Test name
Test status
Simulation time 4350083131 ps
CPU time 3.12 seconds
Started May 21 02:39:56 PM PDT 24
Finished May 21 02:40:14 PM PDT 24
Peak memory 217392 kb
Host smart-3ea2844e-fd28-41ec-be78-9bce1bc5bc39
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215193406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2215193406
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.4232571198
Short name T562
Test name
Test status
Simulation time 5720158229 ps
CPU time 14.83 seconds
Started May 21 02:39:49 PM PDT 24
Finished May 21 02:40:22 PM PDT 24
Peak memory 201680 kb
Host smart-bbbd1725-f650-4400-a1fa-fe09197df9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232571198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.4232571198
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1321982340
Short name T40
Test name
Test status
Simulation time 6241557576 ps
CPU time 14.11 seconds
Started May 21 02:39:56 PM PDT 24
Finished May 21 02:40:25 PM PDT 24
Peak memory 201668 kb
Host smart-376565e1-f17a-45ea-ac1f-e2ed92bd6256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321982340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1321982340
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.4155603061
Short name T707
Test name
Test status
Simulation time 74055338005 ps
CPU time 77.89 seconds
Started May 21 02:39:58 PM PDT 24
Finished May 21 02:41:30 PM PDT 24
Peak memory 210436 kb
Host smart-4d98c366-6a6b-4dd1-bc43-f67bd96d75cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155603061 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.4155603061
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2307155788
Short name T370
Test name
Test status
Simulation time 463931972 ps
CPU time 1.67 seconds
Started May 21 02:41:21 PM PDT 24
Finished May 21 02:41:32 PM PDT 24
Peak memory 201584 kb
Host smart-5bf78ee8-2eb7-47eb-8306-a1aab4f56a56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307155788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2307155788
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.67563182
Short name T619
Test name
Test status
Simulation time 165076550638 ps
CPU time 96.1 seconds
Started May 21 02:41:21 PM PDT 24
Finished May 21 02:43:06 PM PDT 24
Peak memory 201924 kb
Host smart-f763c3de-c3f7-4d45-a287-b3d69e40b0b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67563182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gatin
g.67563182
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.247316530
Short name T178
Test name
Test status
Simulation time 506000721536 ps
CPU time 294.8 seconds
Started May 21 02:41:23 PM PDT 24
Finished May 21 02:46:26 PM PDT 24
Peak memory 201828 kb
Host smart-5a70c746-69a3-41f4-847b-0dbc39f20a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247316530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.247316530
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3487187265
Short name T246
Test name
Test status
Simulation time 491863623509 ps
CPU time 279.7 seconds
Started May 21 02:41:18 PM PDT 24
Finished May 21 02:46:08 PM PDT 24
Peak memory 201864 kb
Host smart-52f1cbfe-df51-4e74-a123-758ad7eba2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487187265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3487187265
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2705141310
Short name T559
Test name
Test status
Simulation time 493345874596 ps
CPU time 204.16 seconds
Started May 21 02:41:15 PM PDT 24
Finished May 21 02:44:51 PM PDT 24
Peak memory 201880 kb
Host smart-48e7d3a7-5b00-4d79-86f2-613a418caa76
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705141310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2705141310
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.403620618
Short name T152
Test name
Test status
Simulation time 492650599541 ps
CPU time 535.43 seconds
Started May 21 02:41:23 PM PDT 24
Finished May 21 02:50:27 PM PDT 24
Peak memory 201920 kb
Host smart-154cfbb5-58b7-404a-9661-ca33fc3a65af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403620618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.403620618
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2190148321
Short name T505
Test name
Test status
Simulation time 482897499204 ps
CPU time 772.83 seconds
Started May 21 02:41:17 PM PDT 24
Finished May 21 02:54:21 PM PDT 24
Peak memory 201908 kb
Host smart-04cdf89c-9bdd-44f8-8c0e-f75cba4626bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190148321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2190148321
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2654891513
Short name T544
Test name
Test status
Simulation time 186831191743 ps
CPU time 438.99 seconds
Started May 21 02:41:22 PM PDT 24
Finished May 21 02:48:50 PM PDT 24
Peak memory 201916 kb
Host smart-dd312114-246b-4622-a751-7ed2164a486b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654891513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2654891513
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2296545812
Short name T442
Test name
Test status
Simulation time 200804842688 ps
CPU time 242.09 seconds
Started May 21 02:41:23 PM PDT 24
Finished May 21 02:45:34 PM PDT 24
Peak memory 201808 kb
Host smart-f0240d74-e72e-4933-91de-2cd7b6bfe4b4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296545812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2296545812
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1701168543
Short name T66
Test name
Test status
Simulation time 83431090877 ps
CPU time 439.31 seconds
Started May 21 02:41:22 PM PDT 24
Finished May 21 02:48:50 PM PDT 24
Peak memory 202144 kb
Host smart-581a3027-1da4-434d-8391-3745868721a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701168543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1701168543
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1613836826
Short name T550
Test name
Test status
Simulation time 34052753357 ps
CPU time 85.81 seconds
Started May 21 02:41:22 PM PDT 24
Finished May 21 02:42:57 PM PDT 24
Peak memory 201856 kb
Host smart-46d71538-409c-4fd1-b0be-cb4954b5cb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613836826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1613836826
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2913722184
Short name T454
Test name
Test status
Simulation time 3139303370 ps
CPU time 2.41 seconds
Started May 21 02:41:24 PM PDT 24
Finished May 21 02:41:34 PM PDT 24
Peak memory 201548 kb
Host smart-77bc1fde-6c09-464d-908d-d80a56507c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913722184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2913722184
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3153900241
Short name T158
Test name
Test status
Simulation time 5654769296 ps
CPU time 15.23 seconds
Started May 21 02:41:16 PM PDT 24
Finished May 21 02:41:43 PM PDT 24
Peak memory 201644 kb
Host smart-f7345880-2ad1-4c39-b2cd-76e011b0e2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153900241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3153900241
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.90971669
Short name T296
Test name
Test status
Simulation time 223186525190 ps
CPU time 57.96 seconds
Started May 21 02:41:21 PM PDT 24
Finished May 21 02:42:28 PM PDT 24
Peak memory 210484 kb
Host smart-5d202698-7659-4a4e-816e-efb7aff505ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90971669 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.90971669
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1480830817
Short name T423
Test name
Test status
Simulation time 523383827 ps
CPU time 0.97 seconds
Started May 21 02:41:35 PM PDT 24
Finished May 21 02:41:40 PM PDT 24
Peak memory 201564 kb
Host smart-a854f3a5-83c4-44cb-ab57-8c2423601067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480830817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1480830817
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2018336168
Short name T191
Test name
Test status
Simulation time 339211934751 ps
CPU time 100.28 seconds
Started May 21 02:41:33 PM PDT 24
Finished May 21 02:43:18 PM PDT 24
Peak memory 201776 kb
Host smart-5041fc0f-74af-49f2-add5-04a15a8a37c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018336168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2018336168
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.4158857583
Short name T705
Test name
Test status
Simulation time 324160610795 ps
CPU time 185.68 seconds
Started May 21 02:41:34 PM PDT 24
Finished May 21 02:44:44 PM PDT 24
Peak memory 201808 kb
Host smart-d8d306d8-b26a-4b4e-9646-a8a3e7ffa4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158857583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.4158857583
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.4178425014
Short name T15
Test name
Test status
Simulation time 164487086805 ps
CPU time 398.4 seconds
Started May 21 02:41:29 PM PDT 24
Finished May 21 02:48:13 PM PDT 24
Peak memory 201948 kb
Host smart-b400e48b-866d-440c-87ef-0886d8767c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178425014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.4178425014
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.4224581669
Short name T712
Test name
Test status
Simulation time 320041590109 ps
CPU time 356.37 seconds
Started May 21 02:41:27 PM PDT 24
Finished May 21 02:47:30 PM PDT 24
Peak memory 201868 kb
Host smart-d6a5416a-f926-46b6-a187-0826815b215d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224581669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.4224581669
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2316764439
Short name T270
Test name
Test status
Simulation time 333557773144 ps
CPU time 117.18 seconds
Started May 21 02:41:21 PM PDT 24
Finished May 21 02:43:27 PM PDT 24
Peak memory 201860 kb
Host smart-842e2079-5afc-4d88-8a8a-06b8a00cdadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316764439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2316764439
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.4219444608
Short name T476
Test name
Test status
Simulation time 164448840669 ps
CPU time 185.69 seconds
Started May 21 02:41:25 PM PDT 24
Finished May 21 02:44:38 PM PDT 24
Peak memory 201840 kb
Host smart-2e1e2d21-0159-4b13-b94e-4cdf1074756c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219444608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.4219444608
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2933000905
Short name T708
Test name
Test status
Simulation time 600457309147 ps
CPU time 1015.66 seconds
Started May 21 02:41:33 PM PDT 24
Finished May 21 02:58:33 PM PDT 24
Peak memory 201760 kb
Host smart-478cd8ca-c162-4e6f-a591-1a1863807671
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933000905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2933000905
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.4048311000
Short name T213
Test name
Test status
Simulation time 91992639842 ps
CPU time 347 seconds
Started May 21 02:41:33 PM PDT 24
Finished May 21 02:47:25 PM PDT 24
Peak memory 202184 kb
Host smart-b9e9c97f-cb83-45a0-baf0-3ab4141050f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048311000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.4048311000
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.727285813
Short name T648
Test name
Test status
Simulation time 27114363172 ps
CPU time 30.95 seconds
Started May 21 02:41:34 PM PDT 24
Finished May 21 02:42:09 PM PDT 24
Peak memory 201688 kb
Host smart-429fd9e5-6711-4db4-9939-89ec4f7cfaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727285813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.727285813
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.614287895
Short name T413
Test name
Test status
Simulation time 4396396051 ps
CPU time 10.42 seconds
Started May 21 02:41:33 PM PDT 24
Finished May 21 02:41:48 PM PDT 24
Peak memory 201664 kb
Host smart-68dde71f-70d9-4033-b6f2-f35ac19e3f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614287895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.614287895
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1768682456
Short name T692
Test name
Test status
Simulation time 6173150978 ps
CPU time 6.41 seconds
Started May 21 02:41:22 PM PDT 24
Finished May 21 02:41:37 PM PDT 24
Peak memory 201640 kb
Host smart-c0b61a2d-d0d1-4ab5-ae35-75c9b815adc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768682456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1768682456
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3448579047
Short name T294
Test name
Test status
Simulation time 735871464337 ps
CPU time 508.67 seconds
Started May 21 02:41:34 PM PDT 24
Finished May 21 02:50:07 PM PDT 24
Peak memory 212680 kb
Host smart-546e28a2-f561-48f3-822d-f3d887a30481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448579047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3448579047
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.4284521033
Short name T793
Test name
Test status
Simulation time 104337928032 ps
CPU time 106.04 seconds
Started May 21 02:41:37 PM PDT 24
Finished May 21 02:43:26 PM PDT 24
Peak memory 210412 kb
Host smart-35d5f7a3-30ee-4980-bf21-77485f82b453
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284521033 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.4284521033
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3038945537
Short name T382
Test name
Test status
Simulation time 521893587 ps
CPU time 1.15 seconds
Started May 21 02:41:45 PM PDT 24
Finished May 21 02:41:49 PM PDT 24
Peak memory 201544 kb
Host smart-7d75e31b-51d4-4ba6-8230-0ef7bdfd4863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038945537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3038945537
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.715869402
Short name T510
Test name
Test status
Simulation time 167105157036 ps
CPU time 363.96 seconds
Started May 21 02:41:52 PM PDT 24
Finished May 21 02:47:58 PM PDT 24
Peak memory 201780 kb
Host smart-023eb6d3-2e2d-44b0-8ed6-a7335b032b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715869402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.715869402
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1466606941
Short name T673
Test name
Test status
Simulation time 495575261050 ps
CPU time 1149.85 seconds
Started May 21 02:41:42 PM PDT 24
Finished May 21 03:00:54 PM PDT 24
Peak memory 201900 kb
Host smart-d01ff0d4-cb56-4d58-92b2-40aef13e2ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466606941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1466606941
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2618170836
Short name T644
Test name
Test status
Simulation time 164858839358 ps
CPU time 386.88 seconds
Started May 21 02:41:42 PM PDT 24
Finished May 21 02:48:11 PM PDT 24
Peak memory 201820 kb
Host smart-7aca3331-325f-4704-ab7e-4de3d3dc692b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618170836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2618170836
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2413980581
Short name T669
Test name
Test status
Simulation time 485148773176 ps
CPU time 561.47 seconds
Started May 21 02:41:41 PM PDT 24
Finished May 21 02:51:04 PM PDT 24
Peak memory 201908 kb
Host smart-7c544498-5932-4cd8-ac93-b93d6f53c4ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413980581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2413980581
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3697326091
Short name T574
Test name
Test status
Simulation time 178632381247 ps
CPU time 210.58 seconds
Started May 21 02:41:39 PM PDT 24
Finished May 21 02:45:11 PM PDT 24
Peak memory 201976 kb
Host smart-4e262a28-aeb7-4bbf-af21-6d18b40f2ffb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697326091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3697326091
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3997984913
Short name T163
Test name
Test status
Simulation time 193836351367 ps
CPU time 35.07 seconds
Started May 21 02:41:58 PM PDT 24
Finished May 21 02:42:37 PM PDT 24
Peak memory 201940 kb
Host smart-2e3f1470-604d-4577-883d-316ce2415d15
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997984913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3997984913
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.10650531
Short name T546
Test name
Test status
Simulation time 94543381170 ps
CPU time 452.71 seconds
Started May 21 02:41:46 PM PDT 24
Finished May 21 02:49:22 PM PDT 24
Peak memory 202152 kb
Host smart-e3d67ac6-47fa-4605-b1bb-e35819b983f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10650531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.10650531
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.181413215
Short name T606
Test name
Test status
Simulation time 37039677500 ps
CPU time 84.46 seconds
Started May 21 02:41:53 PM PDT 24
Finished May 21 02:43:21 PM PDT 24
Peak memory 201660 kb
Host smart-267c7efd-4e94-4e85-9543-37647201bce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181413215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.181413215
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3422676623
Short name T750
Test name
Test status
Simulation time 4122263777 ps
CPU time 11.03 seconds
Started May 21 02:41:52 PM PDT 24
Finished May 21 02:42:06 PM PDT 24
Peak memory 201592 kb
Host smart-224d65b5-f0e1-42b5-813a-076e817637bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422676623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3422676623
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1091008077
Short name T388
Test name
Test status
Simulation time 5744314237 ps
CPU time 2.92 seconds
Started May 21 02:41:40 PM PDT 24
Finished May 21 02:41:44 PM PDT 24
Peak memory 201656 kb
Host smart-ff937023-336f-40d7-92eb-73ef5dcc4309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091008077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1091008077
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3257454621
Short name T326
Test name
Test status
Simulation time 621993601551 ps
CPU time 728.97 seconds
Started May 21 02:41:53 PM PDT 24
Finished May 21 02:54:05 PM PDT 24
Peak memory 201960 kb
Host smart-140bbde9-bf2a-4a1c-82d5-181829fea9b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257454621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3257454621
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1524581639
Short name T23
Test name
Test status
Simulation time 128649369660 ps
CPU time 75.05 seconds
Started May 21 02:41:55 PM PDT 24
Finished May 21 02:43:15 PM PDT 24
Peak memory 201936 kb
Host smart-38cf282b-a62d-4eb4-80d9-a23400e9485b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524581639 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1524581639
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.511197515
Short name T665
Test name
Test status
Simulation time 481661677 ps
CPU time 1.17 seconds
Started May 21 02:41:51 PM PDT 24
Finished May 21 02:41:54 PM PDT 24
Peak memory 201532 kb
Host smart-54108a25-c9dd-451c-9660-14e9cef8f2bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511197515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.511197515
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1123929284
Short name T751
Test name
Test status
Simulation time 329248869963 ps
CPU time 161.29 seconds
Started May 21 02:41:51 PM PDT 24
Finished May 21 02:44:34 PM PDT 24
Peak memory 202052 kb
Host smart-fe35b30a-7bc4-41ed-9e23-0680bf12e65e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123929284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1123929284
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.906926005
Short name T516
Test name
Test status
Simulation time 164516942138 ps
CPU time 114.75 seconds
Started May 21 02:41:53 PM PDT 24
Finished May 21 02:43:52 PM PDT 24
Peak memory 201852 kb
Host smart-5557ecfe-17a0-4b68-a0e4-aa1a677e1194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906926005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.906926005
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.4249558251
Short name T723
Test name
Test status
Simulation time 491978403096 ps
CPU time 231.81 seconds
Started May 21 02:41:54 PM PDT 24
Finished May 21 02:45:51 PM PDT 24
Peak memory 201872 kb
Host smart-a9b960f3-7d97-4458-a00d-9afc7d42f00e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249558251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.4249558251
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3009921066
Short name T170
Test name
Test status
Simulation time 482693444934 ps
CPU time 1173.99 seconds
Started May 21 02:41:52 PM PDT 24
Finished May 21 03:01:29 PM PDT 24
Peak memory 201840 kb
Host smart-d139a746-72e1-4dfc-b95c-0b6d3cd451de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009921066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3009921066
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3010648140
Short name T118
Test name
Test status
Simulation time 327715923225 ps
CPU time 377.7 seconds
Started May 21 02:41:52 PM PDT 24
Finished May 21 02:48:13 PM PDT 24
Peak memory 201756 kb
Host smart-54e024db-ec14-4956-9ae6-ba110a580022
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010648140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3010648140
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.2012050368
Short name T176
Test name
Test status
Simulation time 511702517330 ps
CPU time 97.59 seconds
Started May 21 02:41:54 PM PDT 24
Finished May 21 02:43:36 PM PDT 24
Peak memory 201880 kb
Host smart-70ebaabf-e51d-4242-8dc4-fece4be84d8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012050368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.2012050368
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2084111551
Short name T676
Test name
Test status
Simulation time 393456657052 ps
CPU time 223.54 seconds
Started May 21 02:41:55 PM PDT 24
Finished May 21 02:45:43 PM PDT 24
Peak memory 201880 kb
Host smart-65bb45da-0817-4246-88c7-4a69809f7e9a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084111551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2084111551
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.4130999244
Short name T659
Test name
Test status
Simulation time 94695935874 ps
CPU time 446.11 seconds
Started May 21 02:41:52 PM PDT 24
Finished May 21 02:49:22 PM PDT 24
Peak memory 202152 kb
Host smart-1b5c4547-a61d-4472-bb9b-39253b42c731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130999244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.4130999244
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3630739834
Short name T159
Test name
Test status
Simulation time 28610355079 ps
CPU time 23.56 seconds
Started May 21 02:41:57 PM PDT 24
Finished May 21 02:42:25 PM PDT 24
Peak memory 201692 kb
Host smart-186b6f3b-5017-4342-b99c-43f1e5002508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630739834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3630739834
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.345726637
Short name T535
Test name
Test status
Simulation time 4073562765 ps
CPU time 5.81 seconds
Started May 21 02:41:56 PM PDT 24
Finished May 21 02:42:06 PM PDT 24
Peak memory 201644 kb
Host smart-2a89017c-543c-4727-8dfc-0db1a9700f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345726637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.345726637
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.458535546
Short name T396
Test name
Test status
Simulation time 5995028893 ps
CPU time 4.39 seconds
Started May 21 02:41:52 PM PDT 24
Finished May 21 02:41:59 PM PDT 24
Peak memory 201660 kb
Host smart-9273dd15-0ef6-4019-beb9-705feda9af23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458535546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.458535546
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.396268619
Short name T563
Test name
Test status
Simulation time 204193698343 ps
CPU time 79.16 seconds
Started May 21 02:41:52 PM PDT 24
Finished May 21 02:43:15 PM PDT 24
Peak memory 201840 kb
Host smart-4a377fc3-ee83-4e61-aff8-f09d9465c9a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396268619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
396268619
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2170166552
Short name T269
Test name
Test status
Simulation time 578027773710 ps
CPU time 183.16 seconds
Started May 21 02:41:54 PM PDT 24
Finished May 21 02:45:02 PM PDT 24
Peak memory 218108 kb
Host smart-cb51cee0-4e31-45e6-bbdb-4aab6307aaa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170166552 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2170166552
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2685068105
Short name T638
Test name
Test status
Simulation time 349108347 ps
CPU time 0.79 seconds
Started May 21 02:42:13 PM PDT 24
Finished May 21 02:42:15 PM PDT 24
Peak memory 201576 kb
Host smart-566d33cc-9438-461f-98f1-8459af6e6c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685068105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2685068105
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1922203492
Short name T316
Test name
Test status
Simulation time 195052924262 ps
CPU time 87.68 seconds
Started May 21 02:42:12 PM PDT 24
Finished May 21 02:43:42 PM PDT 24
Peak memory 201876 kb
Host smart-3e4af910-0f39-4eac-af28-be4ec1674a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922203492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1922203492
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3192148420
Short name T635
Test name
Test status
Simulation time 164941008600 ps
CPU time 211.35 seconds
Started May 21 02:42:00 PM PDT 24
Finished May 21 02:45:35 PM PDT 24
Peak memory 201936 kb
Host smart-9cb3c3ae-f2cc-4e31-93ec-019204f9a609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192148420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3192148420
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.1164639891
Short name T501
Test name
Test status
Simulation time 492500673742 ps
CPU time 233.51 seconds
Started May 21 02:41:58 PM PDT 24
Finished May 21 02:45:56 PM PDT 24
Peak memory 201920 kb
Host smart-ebbd66d9-f588-4229-b031-1a4b7d963f85
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164639891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.1164639891
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.37865906
Short name T299
Test name
Test status
Simulation time 168554325904 ps
CPU time 98.98 seconds
Started May 21 02:41:59 PM PDT 24
Finished May 21 02:43:42 PM PDT 24
Peak memory 201820 kb
Host smart-560cecd5-6e02-4269-a175-beae8e08ca1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37865906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.37865906
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.4255432689
Short name T172
Test name
Test status
Simulation time 494903779320 ps
CPU time 1185.81 seconds
Started May 21 02:42:00 PM PDT 24
Finished May 21 03:01:50 PM PDT 24
Peak memory 201864 kb
Host smart-de9ca3f1-8606-43ab-8a3f-15feff3c280a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255432689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.4255432689
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.685169689
Short name T771
Test name
Test status
Simulation time 588891485416 ps
CPU time 333.57 seconds
Started May 21 02:41:58 PM PDT 24
Finished May 21 02:47:36 PM PDT 24
Peak memory 201884 kb
Host smart-7d4d5f0a-bb28-4e90-b013-99a0a3b02d40
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685169689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.685169689
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1083003922
Short name T433
Test name
Test status
Simulation time 200849072827 ps
CPU time 124.84 seconds
Started May 21 02:41:59 PM PDT 24
Finished May 21 02:44:08 PM PDT 24
Peak memory 201828 kb
Host smart-b6e4fa38-5cf4-49d7-87c8-334aa2252d7e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083003922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1083003922
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.502271612
Short name T767
Test name
Test status
Simulation time 119683103688 ps
CPU time 386.57 seconds
Started May 21 02:42:08 PM PDT 24
Finished May 21 02:48:37 PM PDT 24
Peak memory 202076 kb
Host smart-45eb2847-be4c-4a5d-adab-d3d03a026296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502271612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.502271612
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2659408895
Short name T356
Test name
Test status
Simulation time 26556266072 ps
CPU time 14.86 seconds
Started May 21 02:42:07 PM PDT 24
Finished May 21 02:42:25 PM PDT 24
Peak memory 201652 kb
Host smart-da49cecb-741d-4540-bdb4-a152ff6dfe14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659408895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2659408895
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.846201271
Short name T548
Test name
Test status
Simulation time 4875158582 ps
CPU time 11.85 seconds
Started May 21 02:42:06 PM PDT 24
Finished May 21 02:42:21 PM PDT 24
Peak memory 201692 kb
Host smart-a0d797b4-4706-4207-be1c-1f3944eff9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846201271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.846201271
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.646974170
Short name T524
Test name
Test status
Simulation time 6017839956 ps
CPU time 14.33 seconds
Started May 21 02:41:52 PM PDT 24
Finished May 21 02:42:11 PM PDT 24
Peak memory 201636 kb
Host smart-698fe07a-59ef-46d8-bdf0-ab1e77be0fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646974170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.646974170
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.864048348
Short name T587
Test name
Test status
Simulation time 240028841109 ps
CPU time 579.24 seconds
Started May 21 02:42:08 PM PDT 24
Finished May 21 02:51:49 PM PDT 24
Peak memory 201840 kb
Host smart-a27c99e5-8a70-4ec6-9aa1-9060076ae49d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864048348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
864048348
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2844120225
Short name T18
Test name
Test status
Simulation time 48429733162 ps
CPU time 109.33 seconds
Started May 21 02:42:06 PM PDT 24
Finished May 21 02:43:58 PM PDT 24
Peak memory 210540 kb
Host smart-97ab08e4-92b9-4d85-ab45-d9c2dabf77d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844120225 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2844120225
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.4014670223
Short name T50
Test name
Test status
Simulation time 505759288 ps
CPU time 0.68 seconds
Started May 21 02:42:12 PM PDT 24
Finished May 21 02:42:14 PM PDT 24
Peak memory 201740 kb
Host smart-231f6569-438d-48ef-943b-45fa3e8a9927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014670223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.4014670223
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.230430524
Short name T709
Test name
Test status
Simulation time 169223543220 ps
CPU time 46.46 seconds
Started May 21 02:42:13 PM PDT 24
Finished May 21 02:43:02 PM PDT 24
Peak memory 201880 kb
Host smart-1020cde8-a1c9-425a-92ad-8bb87c595914
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230430524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.230430524
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1611810210
Short name T283
Test name
Test status
Simulation time 495413022165 ps
CPU time 1215.79 seconds
Started May 21 02:42:07 PM PDT 24
Finished May 21 03:02:26 PM PDT 24
Peak memory 201836 kb
Host smart-1ea09137-8b1b-46ad-8b6b-0ce36e5c4de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611810210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1611810210
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2300148545
Short name T183
Test name
Test status
Simulation time 168215621362 ps
CPU time 39.22 seconds
Started May 21 02:42:07 PM PDT 24
Finished May 21 02:42:49 PM PDT 24
Peak memory 201824 kb
Host smart-bf9ba802-881a-41f0-a20a-7961ef2ca321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300148545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2300148545
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2537210973
Short name T695
Test name
Test status
Simulation time 166439113839 ps
CPU time 149.69 seconds
Started May 21 02:42:08 PM PDT 24
Finished May 21 02:44:40 PM PDT 24
Peak memory 201936 kb
Host smart-e4f28428-4114-40b7-b794-606830d74c15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537210973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2537210973
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1102950177
Short name T520
Test name
Test status
Simulation time 494342842272 ps
CPU time 254.71 seconds
Started May 21 02:42:07 PM PDT 24
Finished May 21 02:46:24 PM PDT 24
Peak memory 201780 kb
Host smart-091c3aaa-9619-4119-a6d2-af9c0f9d8e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102950177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1102950177
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2094945075
Short name T449
Test name
Test status
Simulation time 172463716833 ps
CPU time 406.94 seconds
Started May 21 02:42:12 PM PDT 24
Finished May 21 02:49:01 PM PDT 24
Peak memory 201860 kb
Host smart-cc996840-9c4d-46a3-8bd0-05027c324943
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094945075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2094945075
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.838839990
Short name T314
Test name
Test status
Simulation time 519983885241 ps
CPU time 1100.84 seconds
Started May 21 02:42:07 PM PDT 24
Finished May 21 03:00:30 PM PDT 24
Peak memory 201812 kb
Host smart-3e9405b2-c287-4b13-adcd-e3a567ee4bb8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838839990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.838839990
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3060859030
Short name T791
Test name
Test status
Simulation time 397213451320 ps
CPU time 224.96 seconds
Started May 21 02:42:08 PM PDT 24
Finished May 21 02:45:55 PM PDT 24
Peak memory 201824 kb
Host smart-f39f0bc3-1da4-4cdb-ae42-5c7af339fac1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060859030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3060859030
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.836738481
Short name T543
Test name
Test status
Simulation time 86518444063 ps
CPU time 503.17 seconds
Started May 21 02:42:05 PM PDT 24
Finished May 21 02:50:30 PM PDT 24
Peak memory 202156 kb
Host smart-dac00fab-d1ea-4ea0-966f-89b7a0464c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836738481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.836738481
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3085880553
Short name T457
Test name
Test status
Simulation time 35448264518 ps
CPU time 31.24 seconds
Started May 21 02:42:07 PM PDT 24
Finished May 21 02:42:41 PM PDT 24
Peak memory 201688 kb
Host smart-0ed74a4a-0be2-4db0-b074-1c1fde713929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085880553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3085880553
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.960635338
Short name T699
Test name
Test status
Simulation time 5085623564 ps
CPU time 6.67 seconds
Started May 21 02:42:07 PM PDT 24
Finished May 21 02:42:16 PM PDT 24
Peak memory 201708 kb
Host smart-c4998cf3-2992-45f7-94f0-2efa0c94b0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960635338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.960635338
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1828911473
Short name T350
Test name
Test status
Simulation time 5809452761 ps
CPU time 7.43 seconds
Started May 21 02:42:06 PM PDT 24
Finished May 21 02:42:16 PM PDT 24
Peak memory 201600 kb
Host smart-f5a321fd-3b6e-41c8-a9df-b74173f76711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828911473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1828911473
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2496088719
Short name T41
Test name
Test status
Simulation time 454156639488 ps
CPU time 622.4 seconds
Started May 21 02:42:13 PM PDT 24
Finished May 21 02:52:38 PM PDT 24
Peak memory 210344 kb
Host smart-ae73baab-7276-4333-9e9d-94cea723f456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496088719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2496088719
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3623341130
Short name T305
Test name
Test status
Simulation time 180434692083 ps
CPU time 138.95 seconds
Started May 21 02:42:12 PM PDT 24
Finished May 21 02:44:33 PM PDT 24
Peak memory 218536 kb
Host smart-5cd4c967-07a2-45df-bd50-c10f142ed7ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623341130 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3623341130
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.4136241324
Short name T353
Test name
Test status
Simulation time 406736070 ps
CPU time 0.68 seconds
Started May 21 02:42:16 PM PDT 24
Finished May 21 02:42:18 PM PDT 24
Peak memory 201556 kb
Host smart-8028ff4d-77c5-47e8-8c65-25dbddff7063
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136241324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.4136241324
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2274353968
Short name T788
Test name
Test status
Simulation time 184103672634 ps
CPU time 418.63 seconds
Started May 21 02:42:17 PM PDT 24
Finished May 21 02:49:17 PM PDT 24
Peak memory 201856 kb
Host smart-526ee3aa-5d8b-48a7-8cff-d4815ec840d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274353968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2274353968
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3526283180
Short name T781
Test name
Test status
Simulation time 161051556038 ps
CPU time 111.17 seconds
Started May 21 02:42:15 PM PDT 24
Finished May 21 02:44:08 PM PDT 24
Peak memory 201864 kb
Host smart-ecb0b71e-c808-4015-b4b0-1f9d17b74c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526283180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3526283180
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2954943141
Short name T784
Test name
Test status
Simulation time 166170356139 ps
CPU time 180.24 seconds
Started May 21 02:42:13 PM PDT 24
Finished May 21 02:45:15 PM PDT 24
Peak memory 201840 kb
Host smart-48223648-cf2e-4495-8592-830b510e7d04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954943141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2954943141
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2197503592
Short name T725
Test name
Test status
Simulation time 493381007802 ps
CPU time 1042.32 seconds
Started May 21 02:42:16 PM PDT 24
Finished May 21 02:59:40 PM PDT 24
Peak memory 201788 kb
Host smart-5e85d9fe-095a-43d7-88f8-14351a0cf7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197503592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2197503592
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1334377092
Short name T636
Test name
Test status
Simulation time 162039760261 ps
CPU time 384.2 seconds
Started May 21 02:42:17 PM PDT 24
Finished May 21 02:48:42 PM PDT 24
Peak memory 201880 kb
Host smart-4fac1f24-aaa7-4719-a8cb-5efc86f410e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334377092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1334377092
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3729005493
Short name T605
Test name
Test status
Simulation time 171720513158 ps
CPU time 246.52 seconds
Started May 21 02:42:15 PM PDT 24
Finished May 21 02:46:23 PM PDT 24
Peak memory 201812 kb
Host smart-4ae15002-0a5f-425c-b0df-c4be5ed8915b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729005493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3729005493
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3154512849
Short name T782
Test name
Test status
Simulation time 415089390093 ps
CPU time 968.07 seconds
Started May 21 02:42:14 PM PDT 24
Finished May 21 02:58:24 PM PDT 24
Peak memory 201788 kb
Host smart-357074f7-a46c-405c-bb21-ac8d1cf24641
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154512849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3154512849
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2399930900
Short name T567
Test name
Test status
Simulation time 76306593559 ps
CPU time 322.24 seconds
Started May 21 02:42:14 PM PDT 24
Finished May 21 02:47:38 PM PDT 24
Peak memory 201960 kb
Host smart-3787c712-bf5e-49ed-9791-e11acb89698c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399930900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2399930900
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3076073639
Short name T114
Test name
Test status
Simulation time 32632091625 ps
CPU time 80.16 seconds
Started May 21 02:42:14 PM PDT 24
Finished May 21 02:43:36 PM PDT 24
Peak memory 201668 kb
Host smart-e43f41c8-d3c3-4ae6-a6a5-2f0f18076249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076073639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3076073639
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1296180947
Short name T609
Test name
Test status
Simulation time 4355813985 ps
CPU time 5.76 seconds
Started May 21 02:42:13 PM PDT 24
Finished May 21 02:42:20 PM PDT 24
Peak memory 201672 kb
Host smart-6c6f6e6f-3eca-4436-8211-b05a14b3bdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296180947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1296180947
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.239639401
Short name T372
Test name
Test status
Simulation time 6002852516 ps
CPU time 4.54 seconds
Started May 21 02:42:13 PM PDT 24
Finished May 21 02:42:19 PM PDT 24
Peak memory 201620 kb
Host smart-e1f86cbd-b697-4394-bcd8-022aa31dfdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239639401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.239639401
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1695409300
Short name T681
Test name
Test status
Simulation time 544897267 ps
CPU time 0.92 seconds
Started May 21 02:42:19 PM PDT 24
Finished May 21 02:42:22 PM PDT 24
Peak memory 201528 kb
Host smart-b782d709-316b-4928-ba3c-230bc0257235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695409300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1695409300
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2818923797
Short name T690
Test name
Test status
Simulation time 354755834681 ps
CPU time 222.5 seconds
Started May 21 02:42:19 PM PDT 24
Finished May 21 02:46:03 PM PDT 24
Peak memory 201880 kb
Host smart-ffdccc02-c588-4544-935c-9fceec781399
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818923797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2818923797
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1237997632
Short name T324
Test name
Test status
Simulation time 163049107577 ps
CPU time 143 seconds
Started May 21 02:42:16 PM PDT 24
Finished May 21 02:44:41 PM PDT 24
Peak memory 201828 kb
Host smart-ae9af80c-f6b6-47e7-b1fd-3e7fd3d62474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237997632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1237997632
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2485019198
Short name T733
Test name
Test status
Simulation time 324244211604 ps
CPU time 296.48 seconds
Started May 21 02:42:16 PM PDT 24
Finished May 21 02:47:14 PM PDT 24
Peak memory 201856 kb
Host smart-f77c2912-ba6b-4827-a6f4-f4c06ed6f118
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485019198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2485019198
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.2394838160
Short name T670
Test name
Test status
Simulation time 163196251322 ps
CPU time 92.67 seconds
Started May 21 02:42:14 PM PDT 24
Finished May 21 02:43:49 PM PDT 24
Peak memory 201808 kb
Host smart-317b6a5f-9927-4eaf-8353-8ce84c517dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394838160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2394838160
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1515334992
Short name T514
Test name
Test status
Simulation time 161750001602 ps
CPU time 96.24 seconds
Started May 21 02:42:17 PM PDT 24
Finished May 21 02:43:54 PM PDT 24
Peak memory 201812 kb
Host smart-516d1e77-0ed0-420d-b737-fee1ad30e1d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515334992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1515334992
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3238537902
Short name T189
Test name
Test status
Simulation time 394241594049 ps
CPU time 222.19 seconds
Started May 21 02:42:20 PM PDT 24
Finished May 21 02:46:04 PM PDT 24
Peak memory 201852 kb
Host smart-4a4d9155-0721-4c6e-9db3-5cbf18218bd5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238537902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.3238537902
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2563310463
Short name T344
Test name
Test status
Simulation time 91814219470 ps
CPU time 355.49 seconds
Started May 21 02:42:19 PM PDT 24
Finished May 21 02:48:16 PM PDT 24
Peak memory 202232 kb
Host smart-7ac00ca4-1372-4ece-87f3-d6e65707ba96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563310463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2563310463
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3970044532
Short name T658
Test name
Test status
Simulation time 23946549152 ps
CPU time 51.75 seconds
Started May 21 02:42:20 PM PDT 24
Finished May 21 02:43:13 PM PDT 24
Peak memory 201860 kb
Host smart-006c8a0b-e20a-4752-9a5a-90d5b5238f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970044532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3970044532
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.4046776780
Short name T702
Test name
Test status
Simulation time 3361956473 ps
CPU time 8.97 seconds
Started May 21 02:42:19 PM PDT 24
Finished May 21 02:42:29 PM PDT 24
Peak memory 201644 kb
Host smart-37b1f2b4-12f2-480c-a14a-8b8dc31fd2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046776780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.4046776780
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1062594279
Short name T434
Test name
Test status
Simulation time 5916016257 ps
CPU time 8.04 seconds
Started May 21 02:42:14 PM PDT 24
Finished May 21 02:42:25 PM PDT 24
Peak memory 201612 kb
Host smart-07627746-b242-4d4c-a118-1bf21f8d97d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062594279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1062594279
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.4123466120
Short name T14
Test name
Test status
Simulation time 389345043390 ps
CPU time 242.72 seconds
Started May 21 02:42:19 PM PDT 24
Finished May 21 02:46:22 PM PDT 24
Peak memory 201904 kb
Host smart-4c3005b6-6668-4b0a-822a-1fd3f3d58962
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123466120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.4123466120
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3703260776
Short name T60
Test name
Test status
Simulation time 61790687606 ps
CPU time 30.24 seconds
Started May 21 02:42:19 PM PDT 24
Finished May 21 02:42:50 PM PDT 24
Peak memory 210196 kb
Host smart-41e91cfb-f582-493d-9337-234a2fbad4d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703260776 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3703260776
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3915114688
Short name T545
Test name
Test status
Simulation time 397120884 ps
CPU time 0.96 seconds
Started May 21 02:42:26 PM PDT 24
Finished May 21 02:42:30 PM PDT 24
Peak memory 201556 kb
Host smart-724852b4-0c0e-4546-a1d8-707da5694b2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915114688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3915114688
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2812073116
Short name T197
Test name
Test status
Simulation time 397242398924 ps
CPU time 59.25 seconds
Started May 21 02:42:27 PM PDT 24
Finished May 21 02:43:30 PM PDT 24
Peak memory 201848 kb
Host smart-6edacb2f-cedd-4282-89b9-c3f64bde007b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812073116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2812073116
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2719857052
Short name T327
Test name
Test status
Simulation time 158874729705 ps
CPU time 350.1 seconds
Started May 21 02:42:27 PM PDT 24
Finished May 21 02:48:20 PM PDT 24
Peak memory 201868 kb
Host smart-82549639-eee3-4758-8f05-e73b8ae597ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719857052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2719857052
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2552234432
Short name T643
Test name
Test status
Simulation time 492309661797 ps
CPU time 1107.24 seconds
Started May 21 02:42:27 PM PDT 24
Finished May 21 03:00:57 PM PDT 24
Peak memory 201852 kb
Host smart-15beafbf-e613-4575-b535-e337fc4aab35
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552234432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2552234432
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1745571546
Short name T568
Test name
Test status
Simulation time 506463938936 ps
CPU time 309.44 seconds
Started May 21 02:42:27 PM PDT 24
Finished May 21 02:47:39 PM PDT 24
Peak memory 201924 kb
Host smart-adbb7677-25b0-4808-9bf1-5c03b90efc69
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745571546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1745571546
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1435339861
Short name T590
Test name
Test status
Simulation time 394013634431 ps
CPU time 232.8 seconds
Started May 21 02:42:26 PM PDT 24
Finished May 21 02:46:21 PM PDT 24
Peak memory 201784 kb
Host smart-37ab0b4f-b916-4aba-ab6e-2c7b04dcffc3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435339861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1435339861
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.1254865526
Short name T398
Test name
Test status
Simulation time 76092391144 ps
CPU time 349.05 seconds
Started May 21 02:42:26 PM PDT 24
Finished May 21 02:48:18 PM PDT 24
Peak memory 202252 kb
Host smart-602ed444-8fb4-41ab-b15e-99e083e6e6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254865526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1254865526
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.481925061
Short name T765
Test name
Test status
Simulation time 25776049792 ps
CPU time 59.91 seconds
Started May 21 02:42:25 PM PDT 24
Finished May 21 02:43:27 PM PDT 24
Peak memory 201660 kb
Host smart-a9757ec9-fab2-43e7-9c44-68ddc6926dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481925061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.481925061
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.297200287
Short name T570
Test name
Test status
Simulation time 4984310647 ps
CPU time 3.87 seconds
Started May 21 02:42:28 PM PDT 24
Finished May 21 02:42:34 PM PDT 24
Peak memory 201672 kb
Host smart-ea3a099c-7d8f-40c7-8d99-ada6a576686f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297200287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.297200287
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1344123840
Short name T716
Test name
Test status
Simulation time 5865330311 ps
CPU time 7.06 seconds
Started May 21 02:42:26 PM PDT 24
Finished May 21 02:42:36 PM PDT 24
Peak memory 201704 kb
Host smart-66ca9c00-434c-4915-9b12-4adb8e6b197f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344123840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1344123840
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2349779517
Short name T31
Test name
Test status
Simulation time 284779918986 ps
CPU time 506.95 seconds
Started May 21 02:42:26 PM PDT 24
Finished May 21 02:50:55 PM PDT 24
Peak memory 210348 kb
Host smart-aed868f4-f499-4bce-9c49-e5004145d1cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349779517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2349779517
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3595490675
Short name T368
Test name
Test status
Simulation time 317787534 ps
CPU time 1.32 seconds
Started May 21 02:42:38 PM PDT 24
Finished May 21 02:42:43 PM PDT 24
Peak memory 201596 kb
Host smart-716b517b-b11f-408a-a04b-2764d7fd34ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595490675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3595490675
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1792739907
Short name T329
Test name
Test status
Simulation time 493256499927 ps
CPU time 600.97 seconds
Started May 21 02:42:32 PM PDT 24
Finished May 21 02:52:36 PM PDT 24
Peak memory 201908 kb
Host smart-9a50954a-5314-46ea-99d5-34c09da2dc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792739907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1792739907
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3114591990
Short name T378
Test name
Test status
Simulation time 328327115550 ps
CPU time 535.62 seconds
Started May 21 02:42:32 PM PDT 24
Finished May 21 02:51:31 PM PDT 24
Peak memory 201840 kb
Host smart-e830b27e-a274-43d4-8d72-f43cdb4e1c20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114591990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3114591990
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.747261385
Short name T687
Test name
Test status
Simulation time 498087418376 ps
CPU time 268.59 seconds
Started May 21 02:42:31 PM PDT 24
Finished May 21 02:47:03 PM PDT 24
Peak memory 201844 kb
Host smart-44390551-2c59-47fc-81d0-2bfa2870e345
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=747261385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.747261385
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1212195401
Short name T250
Test name
Test status
Simulation time 516826689416 ps
CPU time 325.12 seconds
Started May 21 02:42:32 PM PDT 24
Finished May 21 02:48:00 PM PDT 24
Peak memory 201844 kb
Host smart-8b02fe1a-d47d-4e78-a2c0-aa25f338d831
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212195401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1212195401
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3269468237
Short name T5
Test name
Test status
Simulation time 218202028780 ps
CPU time 40.96 seconds
Started May 21 02:42:31 PM PDT 24
Finished May 21 02:43:15 PM PDT 24
Peak memory 201820 kb
Host smart-aab3064d-c1a1-4ec6-a154-9fc5c8d89b91
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269468237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3269468237
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1456853031
Short name T63
Test name
Test status
Simulation time 63030499391 ps
CPU time 222.05 seconds
Started May 21 02:42:40 PM PDT 24
Finished May 21 02:46:26 PM PDT 24
Peak memory 202172 kb
Host smart-7224265d-4e62-4736-8aed-f778cf75bd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456853031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1456853031
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.316216600
Short name T363
Test name
Test status
Simulation time 24738385036 ps
CPU time 4.31 seconds
Started May 21 02:42:38 PM PDT 24
Finished May 21 02:42:47 PM PDT 24
Peak memory 201680 kb
Host smart-411014fb-7b6d-411a-9af6-87c469027d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316216600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.316216600
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.300570123
Short name T565
Test name
Test status
Simulation time 3748410875 ps
CPU time 9.07 seconds
Started May 21 02:42:38 PM PDT 24
Finished May 21 02:42:51 PM PDT 24
Peak memory 201572 kb
Host smart-dc945c1a-df01-4a04-bf57-ad166ce364e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300570123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.300570123
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1000692731
Short name T710
Test name
Test status
Simulation time 5947506436 ps
CPU time 4.1 seconds
Started May 21 02:42:31 PM PDT 24
Finished May 21 02:42:38 PM PDT 24
Peak memory 201680 kb
Host smart-1ab8377f-6e3b-47e3-ba42-d23fd93f23c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000692731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1000692731
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1240541482
Short name T518
Test name
Test status
Simulation time 393126228832 ps
CPU time 229.09 seconds
Started May 21 02:42:39 PM PDT 24
Finished May 21 02:46:33 PM PDT 24
Peak memory 201928 kb
Host smart-addb2a67-e7a4-4f38-9b7a-533726555fc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240541482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1240541482
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3615026711
Short name T715
Test name
Test status
Simulation time 22834313598 ps
CPU time 15.42 seconds
Started May 21 02:42:38 PM PDT 24
Finished May 21 02:42:57 PM PDT 24
Peak memory 210144 kb
Host smart-c8ab6b6b-59fa-4855-8728-84d4a81ec228
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615026711 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3615026711
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3789867988
Short name T696
Test name
Test status
Simulation time 482108204 ps
CPU time 1.16 seconds
Started May 21 02:40:09 PM PDT 24
Finished May 21 02:40:19 PM PDT 24
Peak memory 201504 kb
Host smart-ed027b70-0432-4d9a-9de2-7968cda8bc47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789867988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3789867988
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1085161605
Short name T481
Test name
Test status
Simulation time 164549524388 ps
CPU time 90.37 seconds
Started May 21 02:40:08 PM PDT 24
Finished May 21 02:41:48 PM PDT 24
Peak memory 201868 kb
Host smart-0c7eb748-e08e-42ff-9acf-af9b1069c402
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085161605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1085161605
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.919561027
Short name T774
Test name
Test status
Simulation time 340733677636 ps
CPU time 368.97 seconds
Started May 21 02:41:07 PM PDT 24
Finished May 21 02:47:30 PM PDT 24
Peak memory 201884 kb
Host smart-7919e3e0-70bf-468a-944a-13b860621b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919561027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.919561027
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.1924524672
Short name T572
Test name
Test status
Simulation time 168021025256 ps
CPU time 117.69 seconds
Started May 21 02:40:19 PM PDT 24
Finished May 21 02:42:20 PM PDT 24
Peak memory 201844 kb
Host smart-57658aaa-2546-4756-b8e2-96c298d449ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924524672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.1924524672
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.407926423
Short name T200
Test name
Test status
Simulation time 324918997338 ps
CPU time 198.64 seconds
Started May 21 02:40:00 PM PDT 24
Finished May 21 02:43:32 PM PDT 24
Peak memory 201768 kb
Host smart-95c12251-c8e3-41ca-857c-50c2638517fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407926423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.407926423
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3812641542
Short name T397
Test name
Test status
Simulation time 335139712835 ps
CPU time 180.32 seconds
Started May 21 02:40:03 PM PDT 24
Finished May 21 02:43:15 PM PDT 24
Peak memory 201792 kb
Host smart-ab582c9d-bde2-40f8-87ae-2c34dd2157df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812641542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3812641542
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.4208187001
Short name T277
Test name
Test status
Simulation time 365866354840 ps
CPU time 864.02 seconds
Started May 21 02:40:08 PM PDT 24
Finished May 21 02:54:41 PM PDT 24
Peak memory 201916 kb
Host smart-68bb75d0-aeb2-499e-b31b-e264aecad08d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208187001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.4208187001
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.823811554
Short name T662
Test name
Test status
Simulation time 209484788721 ps
CPU time 454.18 seconds
Started May 21 02:40:06 PM PDT 24
Finished May 21 02:47:50 PM PDT 24
Peak memory 201880 kb
Host smart-f5d128ab-d91b-4e52-b783-e853eda2e552
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823811554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.823811554
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3062846320
Short name T214
Test name
Test status
Simulation time 98129962431 ps
CPU time 528.28 seconds
Started May 21 02:40:07 PM PDT 24
Finished May 21 02:49:05 PM PDT 24
Peak memory 202148 kb
Host smart-61dc20d1-90ab-4c5c-bc7d-00bcfd6f9895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062846320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3062846320
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2071722320
Short name T500
Test name
Test status
Simulation time 25493576629 ps
CPU time 57.36 seconds
Started May 21 02:40:07 PM PDT 24
Finished May 21 02:41:14 PM PDT 24
Peak memory 201632 kb
Host smart-432f872b-28cf-406b-b8ac-803e5c2f689b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071722320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2071722320
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3175523135
Short name T693
Test name
Test status
Simulation time 4917078102 ps
CPU time 3.52 seconds
Started May 21 02:40:10 PM PDT 24
Finished May 21 02:40:22 PM PDT 24
Peak memory 201712 kb
Host smart-38270039-f503-40c8-a0a8-14a9c43131cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175523135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3175523135
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3335837266
Short name T96
Test name
Test status
Simulation time 3955728351 ps
CPU time 7.48 seconds
Started May 21 02:40:08 PM PDT 24
Finished May 21 02:40:25 PM PDT 24
Peak memory 217464 kb
Host smart-4ecbaf9a-da18-4af2-816c-52272a240b22
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335837266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3335837266
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.4285613767
Short name T94
Test name
Test status
Simulation time 5689318434 ps
CPU time 2.16 seconds
Started May 21 02:40:08 PM PDT 24
Finished May 21 02:40:20 PM PDT 24
Peak memory 201668 kb
Host smart-d5ec2239-7f8c-44b4-9f73-e1450625a8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285613767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.4285613767
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2040164249
Short name T328
Test name
Test status
Simulation time 247845149454 ps
CPU time 439.11 seconds
Started May 21 02:40:08 PM PDT 24
Finished May 21 02:47:36 PM PDT 24
Peak memory 210356 kb
Host smart-e757b284-fbcc-49fa-95fd-7e40b9ae35c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040164249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2040164249
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1516095389
Short name T19
Test name
Test status
Simulation time 1639412052867 ps
CPU time 160.6 seconds
Started May 21 02:41:07 PM PDT 24
Finished May 21 02:44:02 PM PDT 24
Peak memory 210412 kb
Host smart-38978a9b-2a0e-4979-ae18-f40fb0ce7a21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516095389 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1516095389
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3813344504
Short name T756
Test name
Test status
Simulation time 375621841 ps
CPU time 0.85 seconds
Started May 21 02:42:51 PM PDT 24
Finished May 21 02:42:54 PM PDT 24
Peak memory 201524 kb
Host smart-34947cb1-e60a-490e-b0ae-05c5fdbcdf8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813344504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3813344504
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.991090273
Short name T334
Test name
Test status
Simulation time 166657141025 ps
CPU time 362.31 seconds
Started May 21 02:42:44 PM PDT 24
Finished May 21 02:48:50 PM PDT 24
Peak memory 201868 kb
Host smart-4c3e0538-9a36-403c-b056-3817d9d1848c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991090273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.991090273
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2555948983
Short name T618
Test name
Test status
Simulation time 501584831270 ps
CPU time 362.54 seconds
Started May 21 02:42:46 PM PDT 24
Finished May 21 02:48:52 PM PDT 24
Peak memory 201840 kb
Host smart-84f87dfd-734a-4f77-b259-cfa33f3a7626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555948983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2555948983
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2432356093
Short name T459
Test name
Test status
Simulation time 160925255641 ps
CPU time 192.46 seconds
Started May 21 02:42:43 PM PDT 24
Finished May 21 02:45:59 PM PDT 24
Peak memory 201872 kb
Host smart-f2c12359-a8b1-4737-9ce5-0d5d3b6615ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432356093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2432356093
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.307312339
Short name T175
Test name
Test status
Simulation time 492435025229 ps
CPU time 525.86 seconds
Started May 21 02:42:45 PM PDT 24
Finished May 21 02:51:34 PM PDT 24
Peak memory 201816 kb
Host smart-45303a3e-1f49-4feb-afaa-8bfaf093cd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307312339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.307312339
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1886554348
Short name T602
Test name
Test status
Simulation time 488202397274 ps
CPU time 65.39 seconds
Started May 21 02:42:44 PM PDT 24
Finished May 21 02:43:53 PM PDT 24
Peak memory 201824 kb
Host smart-7c264768-0ca0-4f83-9492-cd74a0f0f9a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886554348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1886554348
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1645260879
Short name T408
Test name
Test status
Simulation time 189642568871 ps
CPU time 119.02 seconds
Started May 21 02:42:45 PM PDT 24
Finished May 21 02:44:47 PM PDT 24
Peak memory 201772 kb
Host smart-4bedf674-db47-4181-8123-2d9d932167b2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645260879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1645260879
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3830909017
Short name T589
Test name
Test status
Simulation time 109548580207 ps
CPU time 574 seconds
Started May 21 02:42:52 PM PDT 24
Finished May 21 02:52:28 PM PDT 24
Peak memory 202212 kb
Host smart-4d388d68-cddc-4e72-9bb9-4505d75ac78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830909017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3830909017
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.485633880
Short name T122
Test name
Test status
Simulation time 39687296062 ps
CPU time 22.61 seconds
Started May 21 02:42:47 PM PDT 24
Finished May 21 02:43:12 PM PDT 24
Peak memory 201664 kb
Host smart-af5bd7d0-4052-45b9-b2bd-36bf054f5c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485633880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.485633880
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2664708118
Short name T573
Test name
Test status
Simulation time 2802164509 ps
CPU time 6.74 seconds
Started May 21 02:42:43 PM PDT 24
Finished May 21 02:42:54 PM PDT 24
Peak memory 201592 kb
Host smart-929e16b4-2bd6-4e5b-ae57-a524f914fb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664708118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2664708118
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2046375597
Short name T651
Test name
Test status
Simulation time 6098815547 ps
CPU time 7.63 seconds
Started May 21 02:42:46 PM PDT 24
Finished May 21 02:42:56 PM PDT 24
Peak memory 201672 kb
Host smart-208ffaf6-dc60-4aba-9317-c4ef7c757c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046375597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2046375597
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1679833513
Short name T39
Test name
Test status
Simulation time 343900041369 ps
CPU time 773.67 seconds
Started May 21 02:42:51 PM PDT 24
Finished May 21 02:55:47 PM PDT 24
Peak memory 201896 kb
Host smart-80431ea6-d79b-4421-8d16-b14bf26dd72e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679833513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1679833513
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.135535423
Short name T25
Test name
Test status
Simulation time 238975659727 ps
CPU time 187.36 seconds
Started May 21 02:42:51 PM PDT 24
Finished May 21 02:46:00 PM PDT 24
Peak memory 210728 kb
Host smart-3c0c5486-f981-42bb-a579-eab45e8124fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135535423 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.135535423
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2800419214
Short name T462
Test name
Test status
Simulation time 339492779 ps
CPU time 1.42 seconds
Started May 21 02:43:01 PM PDT 24
Finished May 21 02:43:06 PM PDT 24
Peak memory 201528 kb
Host smart-be1aa623-a35a-4ee5-badb-5aebf4c1d861
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800419214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2800419214
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.187930704
Short name T186
Test name
Test status
Simulation time 493733864003 ps
CPU time 313.11 seconds
Started May 21 02:42:50 PM PDT 24
Finished May 21 02:48:06 PM PDT 24
Peak memory 201896 kb
Host smart-cfb1ac68-78f0-4064-8f56-026666f39454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187930704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.187930704
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2821472114
Short name T795
Test name
Test status
Simulation time 497674446839 ps
CPU time 1212.9 seconds
Started May 21 02:42:50 PM PDT 24
Finished May 21 03:03:05 PM PDT 24
Peak memory 201860 kb
Host smart-7b176d31-c326-4262-b69b-47fff06acd80
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821472114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2821472114
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.4169846883
Short name T538
Test name
Test status
Simulation time 326953565243 ps
CPU time 793.52 seconds
Started May 21 02:42:51 PM PDT 24
Finished May 21 02:56:07 PM PDT 24
Peak memory 201944 kb
Host smart-b5f71edc-65df-4dec-b59e-9283395b5b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169846883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.4169846883
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3466985223
Short name T428
Test name
Test status
Simulation time 160748373793 ps
CPU time 363.58 seconds
Started May 21 02:42:49 PM PDT 24
Finished May 21 02:48:54 PM PDT 24
Peak memory 202040 kb
Host smart-bbf8904e-6bea-4f7d-ae82-c59227d7c30e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466985223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3466985223
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2524900591
Short name T166
Test name
Test status
Simulation time 356484490577 ps
CPU time 395.91 seconds
Started May 21 02:42:50 PM PDT 24
Finished May 21 02:49:28 PM PDT 24
Peak memory 201844 kb
Host smart-56818cfa-2453-4297-a9fa-c515238c3b1e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524900591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2524900591
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.4093800846
Short name T445
Test name
Test status
Simulation time 207563005486 ps
CPU time 122.26 seconds
Started May 21 02:42:55 PM PDT 24
Finished May 21 02:45:01 PM PDT 24
Peak memory 201844 kb
Host smart-4bc8fa39-59ad-4cce-a42b-5cf13d39d5d2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093800846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.4093800846
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1303556765
Short name T45
Test name
Test status
Simulation time 120337023103 ps
CPU time 437.97 seconds
Started May 21 02:42:55 PM PDT 24
Finished May 21 02:50:17 PM PDT 24
Peak memory 202268 kb
Host smart-12ab5d92-53d0-4f86-bd68-c52819e35dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303556765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1303556765
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1186732814
Short name T438
Test name
Test status
Simulation time 36934311563 ps
CPU time 42.66 seconds
Started May 21 02:42:55 PM PDT 24
Finished May 21 02:43:42 PM PDT 24
Peak memory 201680 kb
Host smart-2a111b50-0526-42c5-9f01-2cece04efb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186732814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1186732814
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1851952566
Short name T351
Test name
Test status
Simulation time 5225531731 ps
CPU time 7.59 seconds
Started May 21 02:42:56 PM PDT 24
Finished May 21 02:43:07 PM PDT 24
Peak memory 201704 kb
Host smart-cdb63dba-c936-407b-9948-89b4739623c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851952566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1851952566
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1812872102
Short name T769
Test name
Test status
Simulation time 5715906412 ps
CPU time 13.82 seconds
Started May 21 02:42:51 PM PDT 24
Finished May 21 02:43:07 PM PDT 24
Peak memory 201660 kb
Host smart-29425500-1212-4af8-910b-2b697c989344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812872102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1812872102
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1104746021
Short name T477
Test name
Test status
Simulation time 33134039241 ps
CPU time 36.74 seconds
Started May 21 02:42:55 PM PDT 24
Finished May 21 02:43:34 PM PDT 24
Peak memory 201608 kb
Host smart-6ecb2255-8378-4c0b-9200-4803637d4866
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104746021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1104746021
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1341763295
Short name T682
Test name
Test status
Simulation time 34335296746 ps
CPU time 40.48 seconds
Started May 21 02:42:54 PM PDT 24
Finished May 21 02:43:38 PM PDT 24
Peak memory 210164 kb
Host smart-5e28f714-4d85-4aeb-8a34-9d4df1c59da1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341763295 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1341763295
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1630244765
Short name T392
Test name
Test status
Simulation time 433316018 ps
CPU time 1.59 seconds
Started May 21 02:43:07 PM PDT 24
Finished May 21 02:43:11 PM PDT 24
Peak memory 201484 kb
Host smart-a4db952b-8083-4ef3-997f-bdea00b56555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630244765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1630244765
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3903605644
Short name T598
Test name
Test status
Simulation time 169377666231 ps
CPU time 27.04 seconds
Started May 21 02:43:09 PM PDT 24
Finished May 21 02:43:38 PM PDT 24
Peak memory 201832 kb
Host smart-48221ef2-c928-420a-bbef-8f8a07898c49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903605644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3903605644
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2949595560
Short name T198
Test name
Test status
Simulation time 342173721725 ps
CPU time 215.39 seconds
Started May 21 02:43:08 PM PDT 24
Finished May 21 02:46:45 PM PDT 24
Peak memory 201824 kb
Host smart-9571f85c-eb5e-4e8f-a4d2-7a7272994ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949595560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2949595560
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3068509719
Short name T205
Test name
Test status
Simulation time 164749992935 ps
CPU time 205.39 seconds
Started May 21 02:43:01 PM PDT 24
Finished May 21 02:46:30 PM PDT 24
Peak memory 201908 kb
Host smart-700667e3-c309-4ac4-8559-8b1e5ce87b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068509719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3068509719
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3390212691
Short name T369
Test name
Test status
Simulation time 328881239679 ps
CPU time 729.59 seconds
Started May 21 02:43:03 PM PDT 24
Finished May 21 02:55:15 PM PDT 24
Peak memory 201860 kb
Host smart-a5fd5751-cff2-41c4-95c7-c6d18776c00f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390212691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3390212691
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.4151421166
Short name T527
Test name
Test status
Simulation time 334747785927 ps
CPU time 388.16 seconds
Started May 21 02:43:00 PM PDT 24
Finished May 21 02:49:32 PM PDT 24
Peak memory 201912 kb
Host smart-2080daf8-c217-4d21-bfaf-dbc17867eb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151421166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.4151421166
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1206031461
Short name T749
Test name
Test status
Simulation time 161856892936 ps
CPU time 383.12 seconds
Started May 21 02:43:02 PM PDT 24
Finished May 21 02:49:28 PM PDT 24
Peak memory 201796 kb
Host smart-5640371d-a5e6-49bc-a9b7-5c6852fcd693
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206031461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1206031461
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3020662909
Short name T182
Test name
Test status
Simulation time 564378187076 ps
CPU time 354.54 seconds
Started May 21 02:43:01 PM PDT 24
Finished May 21 02:48:59 PM PDT 24
Peak memory 201844 kb
Host smart-89e8921f-3b62-4da1-8378-c14913e52163
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020662909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3020662909
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.747890824
Short name T542
Test name
Test status
Simulation time 203977540176 ps
CPU time 245.48 seconds
Started May 21 02:43:02 PM PDT 24
Finished May 21 02:47:11 PM PDT 24
Peak memory 201816 kb
Host smart-0441c04d-9102-41f9-a5b8-badfa31ace30
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747890824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.747890824
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.872541886
Short name T558
Test name
Test status
Simulation time 127247806244 ps
CPU time 434.29 seconds
Started May 21 02:43:08 PM PDT 24
Finished May 21 02:50:25 PM PDT 24
Peak memory 202132 kb
Host smart-ea1cc099-2f96-44f3-9832-d8d06ebb98cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872541886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.872541886
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.549345169
Short name T377
Test name
Test status
Simulation time 36981451418 ps
CPU time 82.88 seconds
Started May 21 02:43:09 PM PDT 24
Finished May 21 02:44:34 PM PDT 24
Peak memory 201656 kb
Host smart-7108c3f6-63c4-4fe2-a8d5-5998f461cb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549345169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.549345169
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3014144201
Short name T764
Test name
Test status
Simulation time 5260678539 ps
CPU time 12.13 seconds
Started May 21 02:43:08 PM PDT 24
Finished May 21 02:43:21 PM PDT 24
Peak memory 201668 kb
Host smart-1693b935-39a7-4a33-9c79-126f95500404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014144201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3014144201
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3883291962
Short name T364
Test name
Test status
Simulation time 5611654059 ps
CPU time 13.65 seconds
Started May 21 02:43:00 PM PDT 24
Finished May 21 02:43:17 PM PDT 24
Peak memory 201688 kb
Host smart-fa774cf3-cb96-44e6-82a1-286c30a9d6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883291962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3883291962
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.471396773
Short name T612
Test name
Test status
Simulation time 324658282 ps
CPU time 0.79 seconds
Started May 21 02:43:22 PM PDT 24
Finished May 21 02:43:26 PM PDT 24
Peak memory 201556 kb
Host smart-c919d149-a3c4-41f3-9511-dda09da504ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471396773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.471396773
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2638518230
Short name T441
Test name
Test status
Simulation time 332839212680 ps
CPU time 733.55 seconds
Started May 21 02:43:14 PM PDT 24
Finished May 21 02:55:30 PM PDT 24
Peak memory 201832 kb
Host smart-f0a100c6-3a07-4c44-98b7-3d8f781b003d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638518230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2638518230
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.4046013575
Short name T564
Test name
Test status
Simulation time 480389710742 ps
CPU time 1120.73 seconds
Started May 21 02:43:15 PM PDT 24
Finished May 21 03:01:59 PM PDT 24
Peak memory 201828 kb
Host smart-75c07d11-1f23-4675-8162-208472dce841
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046013575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.4046013575
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3195130265
Short name T792
Test name
Test status
Simulation time 162971975008 ps
CPU time 383.35 seconds
Started May 21 02:43:08 PM PDT 24
Finished May 21 02:49:34 PM PDT 24
Peak memory 201864 kb
Host smart-3f486f7e-68a7-4b48-a743-7cc3edba3e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195130265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3195130265
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2654335438
Short name T610
Test name
Test status
Simulation time 489964993214 ps
CPU time 1150.89 seconds
Started May 21 02:43:17 PM PDT 24
Finished May 21 03:02:30 PM PDT 24
Peak memory 201852 kb
Host smart-4ed2a69e-65eb-40b2-9666-3cb4ea61c33b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654335438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2654335438
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.6190934
Short name T230
Test name
Test status
Simulation time 174653048580 ps
CPU time 425.67 seconds
Started May 21 02:43:16 PM PDT 24
Finished May 21 02:50:24 PM PDT 24
Peak memory 201872 kb
Host smart-4595d79f-a366-4690-945a-ce3faa72ec5c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6190934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_w
akeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wa
keup.6190934
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2631742486
Short name T745
Test name
Test status
Simulation time 208210959976 ps
CPU time 510.84 seconds
Started May 21 02:43:15 PM PDT 24
Finished May 21 02:51:48 PM PDT 24
Peak memory 201912 kb
Host smart-3c4d3f0a-b010-48a5-a2d4-fa554e146970
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631742486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2631742486
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2464955707
Short name T226
Test name
Test status
Simulation time 114073058489 ps
CPU time 565.9 seconds
Started May 21 02:43:14 PM PDT 24
Finished May 21 02:52:43 PM PDT 24
Peak memory 202148 kb
Host smart-d54b3c53-c00b-4e67-9d4c-7876b1355261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464955707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2464955707
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2751623423
Short name T46
Test name
Test status
Simulation time 44630875394 ps
CPU time 23.33 seconds
Started May 21 02:43:16 PM PDT 24
Finished May 21 02:43:42 PM PDT 24
Peak memory 201680 kb
Host smart-84fd5328-ccea-4351-b9be-2c79bc91a646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751623423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2751623423
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1903348817
Short name T641
Test name
Test status
Simulation time 5240989902 ps
CPU time 3.94 seconds
Started May 21 02:43:15 PM PDT 24
Finished May 21 02:43:22 PM PDT 24
Peak memory 201700 kb
Host smart-3b63ef3f-5da3-4daa-8ac8-618212949c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903348817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1903348817
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1802260334
Short name T512
Test name
Test status
Simulation time 5879641493 ps
CPU time 4.18 seconds
Started May 21 02:43:08 PM PDT 24
Finished May 21 02:43:14 PM PDT 24
Peak memory 201708 kb
Host smart-a268e7c0-d22f-4ac7-9717-f4ce24384edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802260334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1802260334
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3038733579
Short name T222
Test name
Test status
Simulation time 246299551855 ps
CPU time 533.14 seconds
Started May 21 02:43:20 PM PDT 24
Finished May 21 02:52:17 PM PDT 24
Peak memory 218508 kb
Host smart-0a858c3b-433d-4b01-84b2-1fb16bc61fa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038733579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3038733579
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2740101779
Short name T20
Test name
Test status
Simulation time 456295180357 ps
CPU time 857.15 seconds
Started May 21 02:43:13 PM PDT 24
Finished May 21 02:57:31 PM PDT 24
Peak memory 210604 kb
Host smart-c2fc6858-d15e-4cff-9423-68002649666d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740101779 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2740101779
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.4090391679
Short name T207
Test name
Test status
Simulation time 483982921 ps
CPU time 1.7 seconds
Started May 21 02:43:26 PM PDT 24
Finished May 21 02:43:30 PM PDT 24
Peak memory 201512 kb
Host smart-50d6d38b-b790-4748-beeb-a5bacdacdaf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090391679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.4090391679
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.4253560839
Short name T264
Test name
Test status
Simulation time 335064618946 ps
CPU time 77.09 seconds
Started May 21 02:43:32 PM PDT 24
Finished May 21 02:44:50 PM PDT 24
Peak memory 201888 kb
Host smart-beee3dfa-f738-4257-9e2d-5bfa91e7c697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253560839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.4253560839
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.50874518
Short name T266
Test name
Test status
Simulation time 164852727410 ps
CPU time 414.24 seconds
Started May 21 02:43:20 PM PDT 24
Finished May 21 02:50:18 PM PDT 24
Peak memory 201932 kb
Host smart-aa144328-6f01-40e5-bdae-64e2edaf2499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50874518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.50874518
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.718079166
Short name T553
Test name
Test status
Simulation time 331418130033 ps
CPU time 840.45 seconds
Started May 21 02:43:23 PM PDT 24
Finished May 21 02:57:27 PM PDT 24
Peak memory 201852 kb
Host smart-31a7a462-796d-412b-a5f8-674b01e3210c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=718079166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrup
t_fixed.718079166
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1569562712
Short name T759
Test name
Test status
Simulation time 495577269068 ps
CPU time 564.52 seconds
Started May 21 02:43:21 PM PDT 24
Finished May 21 02:52:48 PM PDT 24
Peak memory 201864 kb
Host smart-c2f75f08-3b61-4d07-8420-8b731130aa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569562712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1569562712
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1482741305
Short name T106
Test name
Test status
Simulation time 169142547906 ps
CPU time 97.35 seconds
Started May 21 02:43:20 PM PDT 24
Finished May 21 02:45:00 PM PDT 24
Peak memory 201860 kb
Host smart-6bcd048f-03dc-4cac-bd70-ae85a507ffa2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482741305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1482741305
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.944375023
Short name T146
Test name
Test status
Simulation time 544473199939 ps
CPU time 1262.13 seconds
Started May 21 02:43:28 PM PDT 24
Finished May 21 03:04:32 PM PDT 24
Peak memory 201948 kb
Host smart-e50ca52b-e4db-4e2c-b777-17e20bae1a2a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944375023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.944375023
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1436820647
Short name T551
Test name
Test status
Simulation time 194266798600 ps
CPU time 331.15 seconds
Started May 21 02:43:34 PM PDT 24
Finished May 21 02:49:06 PM PDT 24
Peak memory 201852 kb
Host smart-af903133-d6b1-446e-bd06-83f602a53e92
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436820647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1436820647
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3415061243
Short name T649
Test name
Test status
Simulation time 92733175819 ps
CPU time 343.84 seconds
Started May 21 02:43:31 PM PDT 24
Finished May 21 02:49:15 PM PDT 24
Peak memory 202232 kb
Host smart-0cfe5005-433b-4935-8776-b67bf834e0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415061243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3415061243
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.426514477
Short name T748
Test name
Test status
Simulation time 23278551821 ps
CPU time 42.64 seconds
Started May 21 02:43:27 PM PDT 24
Finished May 21 02:44:12 PM PDT 24
Peak memory 201708 kb
Host smart-042e174e-cd25-4b14-9fd9-5386f18f74dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426514477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.426514477
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.4186071063
Short name T504
Test name
Test status
Simulation time 3638362722 ps
CPU time 1.09 seconds
Started May 21 02:43:25 PM PDT 24
Finished May 21 02:43:29 PM PDT 24
Peak memory 201576 kb
Host smart-7f493d86-39c0-4b30-aaaf-32e95a6368d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186071063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.4186071063
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2345160603
Short name T123
Test name
Test status
Simulation time 5798666355 ps
CPU time 4.64 seconds
Started May 21 02:43:22 PM PDT 24
Finished May 21 02:43:29 PM PDT 24
Peak memory 201704 kb
Host smart-65489432-42d5-4dd7-bb69-24e3718c2336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345160603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2345160603
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2099279246
Short name T667
Test name
Test status
Simulation time 337753625398 ps
CPU time 371.32 seconds
Started May 21 02:43:27 PM PDT 24
Finished May 21 02:49:41 PM PDT 24
Peak memory 201852 kb
Host smart-7de9bb32-954f-4377-bd9e-325625273b39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099279246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2099279246
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2727873019
Short name T581
Test name
Test status
Simulation time 307694492397 ps
CPU time 187.21 seconds
Started May 21 02:43:26 PM PDT 24
Finished May 21 02:46:36 PM PDT 24
Peak memory 210216 kb
Host smart-08227aae-33ab-4ac7-89d4-56b9aea2c286
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727873019 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2727873019
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1191007016
Short name T726
Test name
Test status
Simulation time 359606360 ps
CPU time 1.05 seconds
Started May 21 02:43:37 PM PDT 24
Finished May 21 02:43:39 PM PDT 24
Peak memory 201484 kb
Host smart-fd2802f5-ff7e-4bfd-b19e-702b303bad9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191007016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1191007016
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2136452936
Short name T671
Test name
Test status
Simulation time 164460944734 ps
CPU time 77.91 seconds
Started May 21 02:43:32 PM PDT 24
Finished May 21 02:44:51 PM PDT 24
Peak memory 201900 kb
Host smart-a96afdf2-d257-404b-a5f7-e87bc76f58df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136452936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2136452936
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1448546572
Short name T262
Test name
Test status
Simulation time 393985288479 ps
CPU time 896.61 seconds
Started May 21 02:43:32 PM PDT 24
Finished May 21 02:58:29 PM PDT 24
Peak memory 201856 kb
Host smart-4bf260c8-8433-4ef7-944a-b3006b7ae5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448546572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1448546572
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2154997110
Short name T97
Test name
Test status
Simulation time 334012143039 ps
CPU time 152.69 seconds
Started May 21 02:43:31 PM PDT 24
Finished May 21 02:46:04 PM PDT 24
Peak memory 201904 kb
Host smart-386d18e2-8770-4f62-87b2-2e9c47506359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154997110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2154997110
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.427433349
Short name T254
Test name
Test status
Simulation time 333783961630 ps
CPU time 402.2 seconds
Started May 21 02:43:32 PM PDT 24
Finished May 21 02:50:15 PM PDT 24
Peak memory 201816 kb
Host smart-1da1e8c0-3786-4f35-addf-49358d60a937
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=427433349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.427433349
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.323521304
Short name T147
Test name
Test status
Simulation time 329867454679 ps
CPU time 717.33 seconds
Started May 21 02:43:33 PM PDT 24
Finished May 21 02:55:32 PM PDT 24
Peak memory 201956 kb
Host smart-babe1bea-59f1-4109-92f6-7db9b3ea9d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323521304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.323521304
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.4006021723
Short name T467
Test name
Test status
Simulation time 493119409110 ps
CPU time 1120.03 seconds
Started May 21 02:43:34 PM PDT 24
Finished May 21 03:02:15 PM PDT 24
Peak memory 202112 kb
Host smart-b06ce792-9b93-48eb-8cda-4dde12f3f085
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006021723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.4006021723
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.667227983
Short name T281
Test name
Test status
Simulation time 353738695441 ps
CPU time 828.84 seconds
Started May 21 02:43:35 PM PDT 24
Finished May 21 02:57:25 PM PDT 24
Peak memory 201920 kb
Host smart-0aae35ac-c09b-4a9c-bfa5-2c08ddfdb62b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667227983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.667227983
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3279086375
Short name T357
Test name
Test status
Simulation time 201154817785 ps
CPU time 431.44 seconds
Started May 21 02:43:34 PM PDT 24
Finished May 21 02:50:46 PM PDT 24
Peak memory 201852 kb
Host smart-23fda15f-6f85-48d6-8f38-d3dffb250ac3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279086375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3279086375
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.980155473
Short name T586
Test name
Test status
Simulation time 97270180974 ps
CPU time 412.54 seconds
Started May 21 02:43:38 PM PDT 24
Finished May 21 02:50:32 PM PDT 24
Peak memory 202164 kb
Host smart-2dcc43c3-a0d8-4e3f-8c1f-c3ed77ed2a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980155473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.980155473
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.788568511
Short name T513
Test name
Test status
Simulation time 44893585856 ps
CPU time 50.73 seconds
Started May 21 02:43:39 PM PDT 24
Finished May 21 02:44:31 PM PDT 24
Peak memory 201644 kb
Host smart-06062381-cf10-4406-87a9-4643e005beda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788568511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.788568511
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3290050279
Short name T487
Test name
Test status
Simulation time 4241664959 ps
CPU time 10.22 seconds
Started May 21 02:43:33 PM PDT 24
Finished May 21 02:43:44 PM PDT 24
Peak memory 201640 kb
Host smart-2b7f9b59-7dab-4296-9012-4e6a13ea58ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290050279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3290050279
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2452431315
Short name T664
Test name
Test status
Simulation time 5680546528 ps
CPU time 3.93 seconds
Started May 21 02:43:33 PM PDT 24
Finished May 21 02:43:37 PM PDT 24
Peak memory 201668 kb
Host smart-d89038e4-da1e-425c-86ae-3fcd2b6b8ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452431315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2452431315
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.823208688
Short name T169
Test name
Test status
Simulation time 501042449101 ps
CPU time 1108.12 seconds
Started May 21 02:43:39 PM PDT 24
Finished May 21 03:02:08 PM PDT 24
Peak memory 201884 kb
Host smart-0d8435bb-c96c-4fa7-9926-2c38604f7433
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823208688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
823208688
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1073036305
Short name T654
Test name
Test status
Simulation time 423895512 ps
CPU time 1.65 seconds
Started May 21 02:43:52 PM PDT 24
Finished May 21 02:43:56 PM PDT 24
Peak memory 201584 kb
Host smart-5fce7d2c-9054-4d03-8a6d-6bb5df8d9336
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073036305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1073036305
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2580228695
Short name T320
Test name
Test status
Simulation time 528453669824 ps
CPU time 313.71 seconds
Started May 21 02:43:45 PM PDT 24
Finished May 21 02:49:00 PM PDT 24
Peak memory 201776 kb
Host smart-1ec2e8e7-0997-4ade-a9b6-83271e817017
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580228695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2580228695
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.4042257324
Short name T156
Test name
Test status
Simulation time 328188546788 ps
CPU time 202.46 seconds
Started May 21 02:43:45 PM PDT 24
Finished May 21 02:47:09 PM PDT 24
Peak memory 201824 kb
Host smart-aa3be0c1-06a8-4977-9626-0fb5635d1678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042257324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.4042257324
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3642153445
Short name T746
Test name
Test status
Simulation time 166610229185 ps
CPU time 375.59 seconds
Started May 21 02:43:43 PM PDT 24
Finished May 21 02:50:01 PM PDT 24
Peak memory 201836 kb
Host smart-b0e843df-4308-49be-997d-ba12e4a49492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642153445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3642153445
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2903936134
Short name T404
Test name
Test status
Simulation time 335759730956 ps
CPU time 98.47 seconds
Started May 21 02:43:43 PM PDT 24
Finished May 21 02:45:23 PM PDT 24
Peak memory 201864 kb
Host smart-c8f02652-34c8-4647-9f0a-537aa47b84eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903936134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2903936134
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3623324569
Short name T374
Test name
Test status
Simulation time 330224464153 ps
CPU time 657.2 seconds
Started May 21 02:43:43 PM PDT 24
Finished May 21 02:54:42 PM PDT 24
Peak memory 201884 kb
Host smart-1e8c5e30-13a1-4cf9-86ee-a1c89bb936d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623324569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3623324569
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1757851612
Short name T348
Test name
Test status
Simulation time 397018217225 ps
CPU time 240.26 seconds
Started May 21 02:43:45 PM PDT 24
Finished May 21 02:47:47 PM PDT 24
Peak memory 201816 kb
Host smart-dd9c4668-ad26-4626-a546-4a8682f467a1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757851612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1757851612
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1085853505
Short name T67
Test name
Test status
Simulation time 94436327510 ps
CPU time 312.23 seconds
Started May 21 02:43:51 PM PDT 24
Finished May 21 02:49:05 PM PDT 24
Peak memory 202232 kb
Host smart-1280d19e-3aa6-47f9-9a0c-c65bc433e498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085853505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1085853505
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.441968909
Short name T455
Test name
Test status
Simulation time 26342786708 ps
CPU time 58.11 seconds
Started May 21 02:43:51 PM PDT 24
Finished May 21 02:44:51 PM PDT 24
Peak memory 201708 kb
Host smart-e981b260-97a5-4505-84d3-d9a6b3850390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441968909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.441968909
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1990729979
Short name T768
Test name
Test status
Simulation time 3122458677 ps
CPU time 2.01 seconds
Started May 21 02:43:44 PM PDT 24
Finished May 21 02:43:48 PM PDT 24
Peak memory 201616 kb
Host smart-b750614c-d184-4f07-af86-283f6c2b6c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990729979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1990729979
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2961518879
Short name T529
Test name
Test status
Simulation time 5589046826 ps
CPU time 3.94 seconds
Started May 21 02:43:45 PM PDT 24
Finished May 21 02:43:50 PM PDT 24
Peak memory 201688 kb
Host smart-8f1b226c-ffbd-440f-91bc-1e2e66307292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961518879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2961518879
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1478923736
Short name T730
Test name
Test status
Simulation time 206504258089 ps
CPU time 120.47 seconds
Started May 21 02:43:51 PM PDT 24
Finished May 21 02:45:53 PM PDT 24
Peak memory 202048 kb
Host smart-fd2756b7-97ab-4ae4-9491-2d0036ea34cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478923736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1478923736
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2028745633
Short name T734
Test name
Test status
Simulation time 189925086666 ps
CPU time 119.46 seconds
Started May 21 02:43:52 PM PDT 24
Finished May 21 02:45:53 PM PDT 24
Peak memory 210456 kb
Host smart-da7b34c2-200b-48dd-ae92-f16e618270a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028745633 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2028745633
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3004922231
Short name T607
Test name
Test status
Simulation time 349648936 ps
CPU time 1.42 seconds
Started May 21 02:44:05 PM PDT 24
Finished May 21 02:44:09 PM PDT 24
Peak memory 201548 kb
Host smart-3066216c-8423-42ab-bd26-445ae530e623
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004922231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3004922231
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2172611756
Short name T73
Test name
Test status
Simulation time 541181585730 ps
CPU time 331.92 seconds
Started May 21 02:43:59 PM PDT 24
Finished May 21 02:49:33 PM PDT 24
Peak memory 201880 kb
Host smart-0e3763f6-38a1-4900-92dd-d5edf11a416b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172611756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2172611756
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3165687198
Short name T313
Test name
Test status
Simulation time 496935390401 ps
CPU time 307.4 seconds
Started May 21 02:43:51 PM PDT 24
Finished May 21 02:49:00 PM PDT 24
Peak memory 201796 kb
Host smart-7f52b430-f676-42f5-8144-2ac60c86ac46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165687198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3165687198
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1661078291
Short name T430
Test name
Test status
Simulation time 168245639561 ps
CPU time 104.15 seconds
Started May 21 02:43:52 PM PDT 24
Finished May 21 02:45:38 PM PDT 24
Peak memory 201868 kb
Host smart-57b03e65-4037-4b40-81de-e70d1d51b5d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661078291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1661078291
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.4004076701
Short name T600
Test name
Test status
Simulation time 495059589328 ps
CPU time 566.49 seconds
Started May 21 02:43:51 PM PDT 24
Finished May 21 02:53:19 PM PDT 24
Peak memory 201836 kb
Host smart-a70b5bca-46b4-42a8-b085-626bc7b0f289
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004076701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.4004076701
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3270718204
Short name T260
Test name
Test status
Simulation time 605509542565 ps
CPU time 518.59 seconds
Started May 21 02:43:52 PM PDT 24
Finished May 21 02:52:32 PM PDT 24
Peak memory 201876 kb
Host smart-1f7c15cb-9211-4aca-be68-5f97006c4d1c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270718204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3270718204
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.758866763
Short name T576
Test name
Test status
Simulation time 405692999653 ps
CPU time 181.55 seconds
Started May 21 02:43:58 PM PDT 24
Finished May 21 02:47:02 PM PDT 24
Peak memory 201788 kb
Host smart-aee6f677-b74c-420d-89c8-578852b5d10d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758866763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.758866763
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3231411493
Short name T779
Test name
Test status
Simulation time 106888119405 ps
CPU time 549.77 seconds
Started May 21 02:44:07 PM PDT 24
Finished May 21 02:53:20 PM PDT 24
Peak memory 202172 kb
Host smart-7d28841c-7833-46a9-8e09-18f6d9484440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231411493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3231411493
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1635018021
Short name T414
Test name
Test status
Simulation time 33992218799 ps
CPU time 41.41 seconds
Started May 21 02:43:58 PM PDT 24
Finished May 21 02:44:42 PM PDT 24
Peak memory 201676 kb
Host smart-a5816827-2e10-4efd-9102-c88ab41f2e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635018021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1635018021
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3394424759
Short name T526
Test name
Test status
Simulation time 2879637460 ps
CPU time 4.3 seconds
Started May 21 02:43:58 PM PDT 24
Finished May 21 02:44:05 PM PDT 24
Peak memory 201604 kb
Host smart-4862ace9-8715-4ae1-9d30-bfe683e9d4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394424759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3394424759
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3430887424
Short name T393
Test name
Test status
Simulation time 5758655973 ps
CPU time 14.84 seconds
Started May 21 02:43:50 PM PDT 24
Finished May 21 02:44:05 PM PDT 24
Peak memory 201664 kb
Host smart-eca47c8f-e613-4ef1-b58c-5d688cdca906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430887424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3430887424
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.726874112
Short name T439
Test name
Test status
Simulation time 295666206851 ps
CPU time 447.13 seconds
Started May 21 02:44:06 PM PDT 24
Finished May 21 02:51:35 PM PDT 24
Peak memory 218552 kb
Host smart-1895dc4a-2b72-43a5-9d6e-f971cea6ee60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726874112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
726874112
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1574779267
Short name T507
Test name
Test status
Simulation time 79431173879 ps
CPU time 93.06 seconds
Started May 21 02:44:05 PM PDT 24
Finished May 21 02:45:39 PM PDT 24
Peak memory 201988 kb
Host smart-188d5bb5-9552-48da-bb55-9a35500da48a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574779267 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1574779267
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3066482229
Short name T421
Test name
Test status
Simulation time 361891684 ps
CPU time 0.8 seconds
Started May 21 02:44:12 PM PDT 24
Finished May 21 02:44:14 PM PDT 24
Peak memory 201552 kb
Host smart-4a68c0b6-66e4-4c97-aed5-28c122289a66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066482229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3066482229
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1006390271
Short name T335
Test name
Test status
Simulation time 194610487785 ps
CPU time 454.41 seconds
Started May 21 02:44:05 PM PDT 24
Finished May 21 02:51:42 PM PDT 24
Peak memory 201824 kb
Host smart-5c851eb7-54e6-4106-bc01-ec9ab30f3641
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006390271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1006390271
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.4102757924
Short name T540
Test name
Test status
Simulation time 561853692563 ps
CPU time 1358.37 seconds
Started May 21 02:44:06 PM PDT 24
Finished May 21 03:06:48 PM PDT 24
Peak memory 201896 kb
Host smart-11dcc75a-3be8-440b-ac6b-042f58f4aef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102757924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.4102757924
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1198061583
Short name T389
Test name
Test status
Simulation time 477872040701 ps
CPU time 510.2 seconds
Started May 21 02:44:05 PM PDT 24
Finished May 21 02:52:38 PM PDT 24
Peak memory 201832 kb
Host smart-1a984b0e-19b9-4fce-a07f-a069f19cc865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198061583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1198061583
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.4030684742
Short name T663
Test name
Test status
Simulation time 325585466494 ps
CPU time 404.26 seconds
Started May 21 02:44:05 PM PDT 24
Finished May 21 02:50:52 PM PDT 24
Peak memory 201876 kb
Host smart-0d4f6ec7-b70f-49a8-b8c6-135fc4458cdf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030684742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.4030684742
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1662269694
Short name T1
Test name
Test status
Simulation time 324575892549 ps
CPU time 113.91 seconds
Started May 21 02:44:06 PM PDT 24
Finished May 21 02:46:03 PM PDT 24
Peak memory 201812 kb
Host smart-2bf9c4b8-de52-47aa-887a-bc1b797e41e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662269694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1662269694
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1538130035
Short name T488
Test name
Test status
Simulation time 166548205514 ps
CPU time 393.87 seconds
Started May 21 02:44:05 PM PDT 24
Finished May 21 02:50:42 PM PDT 24
Peak memory 201960 kb
Host smart-cdc8e590-5b6f-4468-a81a-6b282eec519a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538130035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1538130035
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1627968799
Short name T686
Test name
Test status
Simulation time 160830346807 ps
CPU time 380.86 seconds
Started May 21 02:44:06 PM PDT 24
Finished May 21 02:50:29 PM PDT 24
Peak memory 201852 kb
Host smart-bdd87c82-b3a0-462e-b2c5-bd611178e60f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627968799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1627968799
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3668538005
Short name T385
Test name
Test status
Simulation time 400971162303 ps
CPU time 872.77 seconds
Started May 21 02:44:05 PM PDT 24
Finished May 21 02:58:41 PM PDT 24
Peak memory 201916 kb
Host smart-a5cd0d7e-8687-4b06-aa15-de6686159e53
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668538005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3668538005
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3048037737
Short name T537
Test name
Test status
Simulation time 45027069509 ps
CPU time 26.54 seconds
Started May 21 02:44:10 PM PDT 24
Finished May 21 02:44:38 PM PDT 24
Peak memory 201676 kb
Host smart-d50f4299-0078-48ac-a4a2-069e180bd521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048037737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3048037737
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.88133729
Short name T474
Test name
Test status
Simulation time 5130251132 ps
CPU time 13.44 seconds
Started May 21 02:44:05 PM PDT 24
Finished May 21 02:44:21 PM PDT 24
Peak memory 201604 kb
Host smart-19abf22a-7a06-47d5-a1ef-149d2550a12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88133729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.88133729
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2038873664
Short name T492
Test name
Test status
Simulation time 5728646647 ps
CPU time 4.06 seconds
Started May 21 02:44:06 PM PDT 24
Finished May 21 02:44:12 PM PDT 24
Peak memory 201688 kb
Host smart-fed45368-d37b-4a82-aef7-d6ed6a957d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038873664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2038873664
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.2798280414
Short name T171
Test name
Test status
Simulation time 166864267940 ps
CPU time 104.19 seconds
Started May 21 02:44:13 PM PDT 24
Finished May 21 02:45:58 PM PDT 24
Peak memory 201840 kb
Host smart-f0e7d145-59cc-4d38-8db0-a1da209b7bd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798280414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.2798280414
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.248416220
Short name T268
Test name
Test status
Simulation time 143693563632 ps
CPU time 97.49 seconds
Started May 21 02:44:10 PM PDT 24
Finished May 21 02:45:49 PM PDT 24
Peak memory 210200 kb
Host smart-9cb30509-e7c1-4949-a1ff-90cb575da155
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248416220 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.248416220
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1068546975
Short name T552
Test name
Test status
Simulation time 379443316 ps
CPU time 1.51 seconds
Started May 21 02:44:18 PM PDT 24
Finished May 21 02:44:21 PM PDT 24
Peak memory 201532 kb
Host smart-c7d695ae-3180-406f-9e1c-28e3c8b4cbd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068546975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1068546975
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2646549089
Short name T323
Test name
Test status
Simulation time 163510239601 ps
CPU time 85.74 seconds
Started May 21 02:44:17 PM PDT 24
Finished May 21 02:45:44 PM PDT 24
Peak memory 201888 kb
Host smart-fb8d2cd3-d736-46a1-97a8-7eb4f78c266d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646549089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2646549089
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2635675609
Short name T302
Test name
Test status
Simulation time 160186537229 ps
CPU time 392.63 seconds
Started May 21 02:44:15 PM PDT 24
Finished May 21 02:50:49 PM PDT 24
Peak memory 201876 kb
Host smart-31a8a2ba-277c-4bb1-9a15-c4be98b78770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635675609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2635675609
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2353589141
Short name T625
Test name
Test status
Simulation time 331350600304 ps
CPU time 809.72 seconds
Started May 21 02:44:12 PM PDT 24
Finished May 21 02:57:43 PM PDT 24
Peak memory 201904 kb
Host smart-a6bcf673-383e-4203-9f43-b28e1ed90e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353589141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2353589141
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2878187741
Short name T405
Test name
Test status
Simulation time 169711077754 ps
CPU time 103.79 seconds
Started May 21 02:44:13 PM PDT 24
Finished May 21 02:45:58 PM PDT 24
Peak memory 201796 kb
Host smart-8a1eb880-50c7-4cf5-b4ff-98953d7f364c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878187741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2878187741
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2731307849
Short name T732
Test name
Test status
Simulation time 163421674879 ps
CPU time 199.92 seconds
Started May 21 02:44:13 PM PDT 24
Finished May 21 02:47:34 PM PDT 24
Peak memory 201824 kb
Host smart-16c4a65d-7631-4285-9b4c-ab6f9ba5aaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731307849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2731307849
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2225376185
Short name T655
Test name
Test status
Simulation time 162283965133 ps
CPU time 189.85 seconds
Started May 21 02:44:13 PM PDT 24
Finished May 21 02:47:24 PM PDT 24
Peak memory 201816 kb
Host smart-08a65804-ec1c-4bd8-a5b5-48f49cfad86f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225376185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2225376185
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3281828321
Short name T611
Test name
Test status
Simulation time 395707501251 ps
CPU time 235.76 seconds
Started May 21 02:44:11 PM PDT 24
Finished May 21 02:48:08 PM PDT 24
Peak memory 201948 kb
Host smart-f71ee593-9ea6-4461-b3f5-127b34d343a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281828321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3281828321
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2726142411
Short name T728
Test name
Test status
Simulation time 578986098059 ps
CPU time 659.68 seconds
Started May 21 02:44:13 PM PDT 24
Finished May 21 02:55:14 PM PDT 24
Peak memory 201796 kb
Host smart-439b78ff-22c3-47a1-9ee7-683f9507fb70
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726142411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2726142411
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3466443239
Short name T68
Test name
Test status
Simulation time 76732789600 ps
CPU time 349.04 seconds
Started May 21 02:44:17 PM PDT 24
Finished May 21 02:50:08 PM PDT 24
Peak memory 202136 kb
Host smart-c7e52e35-6196-45fe-b29d-98f7c8f1fafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466443239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3466443239
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.501509129
Short name T384
Test name
Test status
Simulation time 22436256218 ps
CPU time 51.2 seconds
Started May 21 02:44:17 PM PDT 24
Finished May 21 02:45:10 PM PDT 24
Peak memory 201700 kb
Host smart-25289f2a-19a0-4e49-a13a-79d74a45e4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501509129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.501509129
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2564151662
Short name T646
Test name
Test status
Simulation time 3617814599 ps
CPU time 9.16 seconds
Started May 21 02:44:17 PM PDT 24
Finished May 21 02:44:28 PM PDT 24
Peak memory 201628 kb
Host smart-035c7600-a7ff-4e09-ab8f-4d958299dbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564151662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2564151662
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.581558290
Short name T506
Test name
Test status
Simulation time 5880998733 ps
CPU time 3.54 seconds
Started May 21 02:44:10 PM PDT 24
Finished May 21 02:44:15 PM PDT 24
Peak memory 201708 kb
Host smart-2a4ca70c-22ca-4aca-9fa6-dee29bea19b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581558290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.581558290
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1221086967
Short name T211
Test name
Test status
Simulation time 429212803688 ps
CPU time 1265.32 seconds
Started May 21 02:44:16 PM PDT 24
Finished May 21 03:05:23 PM PDT 24
Peak memory 202160 kb
Host smart-8f336fa8-6982-43eb-849c-3e099540b515
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221086967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1221086967
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2014724741
Short name T58
Test name
Test status
Simulation time 107543387921 ps
CPU time 137.91 seconds
Started May 21 02:44:17 PM PDT 24
Finished May 21 02:46:37 PM PDT 24
Peak memory 210460 kb
Host smart-985215ce-050e-45d7-a308-1d7edccb867b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014724741 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2014724741
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.636669972
Short name T615
Test name
Test status
Simulation time 621814023 ps
CPU time 0.7 seconds
Started May 21 02:40:16 PM PDT 24
Finished May 21 02:40:22 PM PDT 24
Peak memory 201540 kb
Host smart-d8db2e1c-1847-4f85-b713-f20d1005a93d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636669972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.636669972
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.644902685
Short name T555
Test name
Test status
Simulation time 161995107353 ps
CPU time 99.39 seconds
Started May 21 02:41:07 PM PDT 24
Finished May 21 02:43:01 PM PDT 24
Peak memory 201792 kb
Host smart-3bd73841-726f-4430-9d5e-8c377c4d828b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644902685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.644902685
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2399829530
Short name T167
Test name
Test status
Simulation time 159771526217 ps
CPU time 374.07 seconds
Started May 21 02:40:16 PM PDT 24
Finished May 21 02:46:35 PM PDT 24
Peak memory 201908 kb
Host smart-faa04275-f10b-4158-b840-c98b662f5ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399829530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2399829530
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1315850421
Short name T236
Test name
Test status
Simulation time 488563280116 ps
CPU time 296.19 seconds
Started May 21 02:41:07 PM PDT 24
Finished May 21 02:46:18 PM PDT 24
Peak memory 201792 kb
Host smart-aa0fb139-b7e6-419f-8f1e-b61e6d48cae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315850421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1315850421
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1350233748
Short name T358
Test name
Test status
Simulation time 331360385050 ps
CPU time 749.34 seconds
Started May 21 02:40:16 PM PDT 24
Finished May 21 02:52:51 PM PDT 24
Peak memory 201808 kb
Host smart-675b3d1a-8787-4cc0-b3a8-184af8b66040
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350233748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1350233748
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2036232979
Short name T525
Test name
Test status
Simulation time 325973365344 ps
CPU time 368.87 seconds
Started May 21 02:40:09 PM PDT 24
Finished May 21 02:46:27 PM PDT 24
Peak memory 201944 kb
Host smart-714b3604-bad7-4265-bf16-4c9fd65ff3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036232979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2036232979
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.995121694
Short name T440
Test name
Test status
Simulation time 162967582157 ps
CPU time 92.29 seconds
Started May 21 02:40:09 PM PDT 24
Finished May 21 02:41:51 PM PDT 24
Peak memory 201848 kb
Host smart-97f99b45-9fb6-4dd2-a240-5ba9bc728ad5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=995121694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.995121694
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1813930062
Short name T194
Test name
Test status
Simulation time 608770164776 ps
CPU time 293.43 seconds
Started May 21 02:40:18 PM PDT 24
Finished May 21 02:45:15 PM PDT 24
Peak memory 201916 kb
Host smart-b1892194-dd74-409e-b4c8-8830a780447e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813930062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1813930062
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1951177233
Short name T534
Test name
Test status
Simulation time 407247595922 ps
CPU time 247.23 seconds
Started May 21 02:40:17 PM PDT 24
Finished May 21 02:44:29 PM PDT 24
Peak memory 201832 kb
Host smart-af9482c4-83f0-42d1-9435-b4fc3dbf1e6e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951177233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1951177233
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1565515472
Short name T515
Test name
Test status
Simulation time 29443184178 ps
CPU time 18.69 seconds
Started May 21 02:40:17 PM PDT 24
Finished May 21 02:40:40 PM PDT 24
Peak memory 201668 kb
Host smart-0e74437c-5619-4d48-b0a5-71db63dcb743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565515472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1565515472
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.293447284
Short name T719
Test name
Test status
Simulation time 3492271956 ps
CPU time 8.84 seconds
Started May 21 02:40:14 PM PDT 24
Finished May 21 02:40:29 PM PDT 24
Peak memory 201568 kb
Host smart-61a6dee7-f5db-4b82-a000-ec2435292c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293447284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.293447284
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3026550001
Short name T79
Test name
Test status
Simulation time 8041775572 ps
CPU time 4.06 seconds
Started May 21 02:40:17 PM PDT 24
Finished May 21 02:40:26 PM PDT 24
Peak memory 218476 kb
Host smart-8a362bf2-04e2-4493-aeeb-19317f80dcca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026550001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3026550001
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3041126313
Short name T113
Test name
Test status
Simulation time 6201007248 ps
CPU time 14.07 seconds
Started May 21 02:40:08 PM PDT 24
Finished May 21 02:40:32 PM PDT 24
Peak memory 201700 kb
Host smart-790122dc-be82-46db-a0d2-806dcdce5800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041126313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3041126313
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3026153378
Short name T580
Test name
Test status
Simulation time 7613800802 ps
CPU time 10.42 seconds
Started May 21 02:40:17 PM PDT 24
Finished May 21 02:40:32 PM PDT 24
Peak memory 201644 kb
Host smart-c4c81b63-2756-41f2-8ce9-0c958e607e77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026153378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3026153378
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1008498975
Short name T775
Test name
Test status
Simulation time 152120854168 ps
CPU time 65.85 seconds
Started May 21 02:40:16 PM PDT 24
Finished May 21 02:41:27 PM PDT 24
Peak memory 210416 kb
Host smart-13114e54-a023-425d-8a7b-682a7bcd42bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008498975 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1008498975
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1817960503
Short name T402
Test name
Test status
Simulation time 383582712 ps
CPU time 0.79 seconds
Started May 21 02:44:28 PM PDT 24
Finished May 21 02:44:31 PM PDT 24
Peak memory 201564 kb
Host smart-3f5f0a00-975c-44ac-a4c4-f1a3b7f38edf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817960503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1817960503
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1560291867
Short name T652
Test name
Test status
Simulation time 328934734726 ps
CPU time 712.6 seconds
Started May 21 02:44:19 PM PDT 24
Finished May 21 02:56:13 PM PDT 24
Peak memory 201912 kb
Host smart-6b21a55d-0a92-4399-bbf7-c4024472d58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560291867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1560291867
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3250546364
Short name T111
Test name
Test status
Simulation time 325621465388 ps
CPU time 798.27 seconds
Started May 21 02:44:26 PM PDT 24
Finished May 21 02:57:45 PM PDT 24
Peak memory 201780 kb
Host smart-a83e1e05-b238-44cd-bc79-13bd873ea6fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250546364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3250546364
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.640453720
Short name T584
Test name
Test status
Simulation time 334686041207 ps
CPU time 761.22 seconds
Started May 21 02:44:17 PM PDT 24
Finished May 21 02:57:00 PM PDT 24
Peak memory 201784 kb
Host smart-13f9c841-5a2d-43fa-acc7-cb246104ff75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640453720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.640453720
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.240460752
Short name T547
Test name
Test status
Simulation time 480749107257 ps
CPU time 1188.43 seconds
Started May 21 02:44:17 PM PDT 24
Finished May 21 03:04:08 PM PDT 24
Peak memory 201924 kb
Host smart-20d16b32-410a-4076-afc1-9f6ab8233f60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=240460752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.240460752
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1019690018
Short name T694
Test name
Test status
Simulation time 557933566631 ps
CPU time 1310.19 seconds
Started May 21 02:44:22 PM PDT 24
Finished May 21 03:06:13 PM PDT 24
Peak memory 201864 kb
Host smart-626f5f57-c504-408a-97a2-8f786a321f06
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019690018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1019690018
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2464170567
Short name T471
Test name
Test status
Simulation time 408839620349 ps
CPU time 241.2 seconds
Started May 21 02:44:25 PM PDT 24
Finished May 21 02:48:27 PM PDT 24
Peak memory 201836 kb
Host smart-96209f69-3e70-493a-afa5-554c474ea43a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464170567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2464170567
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.306663965
Short name T223
Test name
Test status
Simulation time 93258886566 ps
CPU time 384.67 seconds
Started May 21 02:44:29 PM PDT 24
Finished May 21 02:50:57 PM PDT 24
Peak memory 202140 kb
Host smart-3292c2a9-96cf-462e-987d-2405622061e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306663965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.306663965
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1670144713
Short name T431
Test name
Test status
Simulation time 35802106669 ps
CPU time 19.13 seconds
Started May 21 02:44:25 PM PDT 24
Finished May 21 02:44:45 PM PDT 24
Peak memory 201652 kb
Host smart-4b766491-96b2-4f9d-82be-0fc619b11a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670144713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1670144713
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.691662120
Short name T766
Test name
Test status
Simulation time 4911967977 ps
CPU time 13 seconds
Started May 21 02:44:23 PM PDT 24
Finished May 21 02:44:37 PM PDT 24
Peak memory 201676 kb
Host smart-09e55942-2672-4d8e-9195-496f3af7dbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691662120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.691662120
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.598482921
Short name T650
Test name
Test status
Simulation time 5662406785 ps
CPU time 4.08 seconds
Started May 21 02:44:16 PM PDT 24
Finished May 21 02:44:22 PM PDT 24
Peak memory 201704 kb
Host smart-9d678e8b-2493-44c1-80ff-185ae65146be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598482921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.598482921
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3164213453
Short name T613
Test name
Test status
Simulation time 217179784850 ps
CPU time 257.55 seconds
Started May 21 02:44:29 PM PDT 24
Finished May 21 02:48:48 PM PDT 24
Peak memory 201864 kb
Host smart-e9411150-3450-4ba6-abcf-fa194db7d3da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164213453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3164213453
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2478635413
Short name T754
Test name
Test status
Simulation time 305432925105 ps
CPU time 574.09 seconds
Started May 21 02:44:29 PM PDT 24
Finished May 21 02:54:06 PM PDT 24
Peak memory 218236 kb
Host smart-218e2b26-513e-4e36-8393-a0aa0ea1a0de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478635413 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2478635413
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2989111121
Short name T366
Test name
Test status
Simulation time 476329401 ps
CPU time 1.73 seconds
Started May 21 02:44:35 PM PDT 24
Finished May 21 02:44:37 PM PDT 24
Peak memory 201556 kb
Host smart-dd6b88ff-de10-4ea2-bafb-b61c4d12f333
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989111121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2989111121
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.288434401
Short name T275
Test name
Test status
Simulation time 550808308655 ps
CPU time 345.13 seconds
Started May 21 02:44:28 PM PDT 24
Finished May 21 02:50:15 PM PDT 24
Peak memory 201956 kb
Host smart-b11abfe1-9297-49de-b3be-b3afc91d31cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288434401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati
ng.288434401
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1997698039
Short name T161
Test name
Test status
Simulation time 165007667279 ps
CPU time 54.3 seconds
Started May 21 02:44:30 PM PDT 24
Finished May 21 02:45:27 PM PDT 24
Peak memory 201864 kb
Host smart-024adbc0-2f5a-405b-8712-ae0bc1919997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997698039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1997698039
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2678220542
Short name T381
Test name
Test status
Simulation time 331552476166 ps
CPU time 415.81 seconds
Started May 21 02:44:31 PM PDT 24
Finished May 21 02:51:29 PM PDT 24
Peak memory 201876 kb
Host smart-ef30fc70-88c0-484b-b9e5-9e18cb2ad18a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678220542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2678220542
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1549759314
Short name T190
Test name
Test status
Simulation time 493816460727 ps
CPU time 565.1 seconds
Started May 21 02:44:30 PM PDT 24
Finished May 21 02:53:58 PM PDT 24
Peak memory 201960 kb
Host smart-60c3d9e6-8d00-4ca1-aac3-1bf2545106f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549759314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1549759314
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1837675934
Short name T701
Test name
Test status
Simulation time 161188950585 ps
CPU time 386.52 seconds
Started May 21 02:44:28 PM PDT 24
Finished May 21 02:50:56 PM PDT 24
Peak memory 201844 kb
Host smart-a75fc9b3-7e6c-4eb7-8a72-1e92fabac4e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837675934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1837675934
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2895751034
Short name T785
Test name
Test status
Simulation time 395517046886 ps
CPU time 987.39 seconds
Started May 21 02:44:30 PM PDT 24
Finished May 21 03:01:00 PM PDT 24
Peak memory 201824 kb
Host smart-b7d382a4-8158-43ee-956f-4a1efc4e4322
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895751034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2895751034
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.383474946
Short name T634
Test name
Test status
Simulation time 126625147132 ps
CPU time 429.11 seconds
Started May 21 02:44:37 PM PDT 24
Finished May 21 02:51:47 PM PDT 24
Peak memory 202224 kb
Host smart-fd4c806d-c5c0-430d-b349-620fc4088fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383474946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.383474946
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1561582056
Short name T790
Test name
Test status
Simulation time 31239625451 ps
CPU time 75.3 seconds
Started May 21 02:44:35 PM PDT 24
Finished May 21 02:45:51 PM PDT 24
Peak memory 201676 kb
Host smart-d5f0a57e-318a-4b87-94fb-adb2ab7604f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561582056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1561582056
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2021921136
Short name T502
Test name
Test status
Simulation time 3183621168 ps
CPU time 8.44 seconds
Started May 21 02:44:28 PM PDT 24
Finished May 21 02:44:39 PM PDT 24
Peak memory 201568 kb
Host smart-8cb034b7-a73a-4168-a30e-4fd5570d8cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021921136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2021921136
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3480487573
Short name T493
Test name
Test status
Simulation time 5884154326 ps
CPU time 14 seconds
Started May 21 02:44:31 PM PDT 24
Finished May 21 02:44:47 PM PDT 24
Peak memory 201676 kb
Host smart-8ab9efca-de87-4f4a-90bb-862797d77390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480487573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3480487573
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1981230433
Short name T336
Test name
Test status
Simulation time 530631320091 ps
CPU time 315.42 seconds
Started May 21 02:44:38 PM PDT 24
Finished May 21 02:49:55 PM PDT 24
Peak memory 201920 kb
Host smart-252ade4c-afdb-40d3-a9c3-fe587c42dc7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981230433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1981230433
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1142910074
Short name T267
Test name
Test status
Simulation time 191472966793 ps
CPU time 35.66 seconds
Started May 21 02:44:38 PM PDT 24
Finished May 21 02:45:15 PM PDT 24
Peak memory 210156 kb
Host smart-6275c432-494a-42a4-acf6-e5da0cb06be7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142910074 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1142910074
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3416095039
Short name T678
Test name
Test status
Simulation time 365943658 ps
CPU time 0.83 seconds
Started May 21 02:44:47 PM PDT 24
Finished May 21 02:44:49 PM PDT 24
Peak memory 201556 kb
Host smart-18cda27b-0bd1-4d10-86b1-3566b735c1c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416095039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3416095039
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2164209095
Short name T744
Test name
Test status
Simulation time 507935526779 ps
CPU time 234.9 seconds
Started May 21 02:44:41 PM PDT 24
Finished May 21 02:48:37 PM PDT 24
Peak memory 201884 kb
Host smart-666cb59f-d8dd-4f8b-be02-1e8c23da3682
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164209095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2164209095
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.537910106
Short name T237
Test name
Test status
Simulation time 352444780474 ps
CPU time 845.3 seconds
Started May 21 02:44:42 PM PDT 24
Finished May 21 02:58:48 PM PDT 24
Peak memory 201804 kb
Host smart-be46125d-5e66-444c-831a-663bc83b5c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537910106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.537910106
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3088840616
Short name T422
Test name
Test status
Simulation time 483750546948 ps
CPU time 870.66 seconds
Started May 21 02:44:42 PM PDT 24
Finished May 21 02:59:14 PM PDT 24
Peak memory 201840 kb
Host smart-5a394beb-5ba5-4350-b2e4-9aa2387a79e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088840616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3088840616
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.202425030
Short name T489
Test name
Test status
Simulation time 162166835832 ps
CPU time 384.1 seconds
Started May 21 02:44:38 PM PDT 24
Finished May 21 02:51:03 PM PDT 24
Peak memory 201924 kb
Host smart-31fb3183-6cf1-4353-8e64-5319dd33bc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202425030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.202425030
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.279360468
Short name T472
Test name
Test status
Simulation time 487861868263 ps
CPU time 1141.48 seconds
Started May 21 02:44:41 PM PDT 24
Finished May 21 03:03:44 PM PDT 24
Peak memory 201852 kb
Host smart-7555c1f2-85f4-45fa-8586-7da0b6295e14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=279360468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.279360468
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.233254650
Short name T519
Test name
Test status
Simulation time 576806550667 ps
CPU time 1347.22 seconds
Started May 21 02:44:41 PM PDT 24
Finished May 21 03:07:10 PM PDT 24
Peak memory 201840 kb
Host smart-fe62a19c-1357-48d1-9488-3e319e263194
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233254650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.233254650
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1915814773
Short name T11
Test name
Test status
Simulation time 586324160463 ps
CPU time 1245.06 seconds
Started May 21 02:44:42 PM PDT 24
Finished May 21 03:05:28 PM PDT 24
Peak memory 201876 kb
Host smart-317660f5-64ed-42e6-bed4-be5787eef4bb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915814773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1915814773
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1644868411
Short name T64
Test name
Test status
Simulation time 92183864450 ps
CPU time 336.05 seconds
Started May 21 02:44:47 PM PDT 24
Finished May 21 02:50:24 PM PDT 24
Peak memory 202232 kb
Host smart-c24739d0-70a5-4e55-8f23-df9f617b40ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644868411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1644868411
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2763400414
Short name T486
Test name
Test status
Simulation time 37119195201 ps
CPU time 64.25 seconds
Started May 21 02:44:42 PM PDT 24
Finished May 21 02:45:47 PM PDT 24
Peak memory 201684 kb
Host smart-7889c358-577a-4ef8-bb17-3c9d6fafecd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763400414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2763400414
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3687707272
Short name T394
Test name
Test status
Simulation time 4908545459 ps
CPU time 6.46 seconds
Started May 21 02:44:43 PM PDT 24
Finished May 21 02:44:50 PM PDT 24
Peak memory 201684 kb
Host smart-e7fd98a1-21a7-4965-b372-5b5846055e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687707272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3687707272
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3126174524
Short name T435
Test name
Test status
Simulation time 5751915755 ps
CPU time 4.03 seconds
Started May 21 02:44:35 PM PDT 24
Finished May 21 02:44:40 PM PDT 24
Peak memory 201652 kb
Host smart-87ea571c-7049-4285-92fc-c9d27912d760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126174524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3126174524
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1076355522
Short name T22
Test name
Test status
Simulation time 53018838693 ps
CPU time 112.92 seconds
Started May 21 02:44:48 PM PDT 24
Finished May 21 02:46:43 PM PDT 24
Peak memory 218700 kb
Host smart-8955d868-f8ba-4721-b158-19a7f5525b6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076355522 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1076355522
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1020900148
Short name T383
Test name
Test status
Simulation time 515659845 ps
CPU time 1.8 seconds
Started May 21 02:44:59 PM PDT 24
Finished May 21 02:45:03 PM PDT 24
Peak memory 201552 kb
Host smart-cf7ae7ec-fea3-426f-ab66-780c67147c66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020900148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1020900148
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.91716894
Short name T306
Test name
Test status
Simulation time 160609151738 ps
CPU time 335.25 seconds
Started May 21 02:44:52 PM PDT 24
Finished May 21 02:50:28 PM PDT 24
Peak memory 201824 kb
Host smart-405d9127-2ffc-41dc-a4be-20982beea32e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91716894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gatin
g.91716894
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1515944616
Short name T760
Test name
Test status
Simulation time 332391581270 ps
CPU time 401.74 seconds
Started May 21 02:44:51 PM PDT 24
Finished May 21 02:51:33 PM PDT 24
Peak memory 201928 kb
Host smart-ce078625-27ae-4263-bc11-79f8d5c4d1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515944616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1515944616
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2484537905
Short name T288
Test name
Test status
Simulation time 329940857435 ps
CPU time 403.96 seconds
Started May 21 02:44:47 PM PDT 24
Finished May 21 02:51:33 PM PDT 24
Peak memory 201848 kb
Host smart-a7fbcbf2-b50a-4db6-bebd-711ecf80c2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484537905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2484537905
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2055718157
Short name T498
Test name
Test status
Simulation time 490444110684 ps
CPU time 232.1 seconds
Started May 21 02:44:53 PM PDT 24
Finished May 21 02:48:48 PM PDT 24
Peak memory 201844 kb
Host smart-5fbe4f4e-84b4-45a2-a8c4-ee26124c034a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055718157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2055718157
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.342907407
Short name T227
Test name
Test status
Simulation time 498055773928 ps
CPU time 1015.7 seconds
Started May 21 02:44:46 PM PDT 24
Finished May 21 03:01:42 PM PDT 24
Peak memory 201884 kb
Host smart-12e346fb-1cfd-4c36-a31b-fb0e6b336b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342907407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.342907407
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2690899862
Short name T466
Test name
Test status
Simulation time 326224090622 ps
CPU time 191.12 seconds
Started May 21 02:44:48 PM PDT 24
Finished May 21 02:48:01 PM PDT 24
Peak memory 201828 kb
Host smart-d6e0328d-a6f7-4cf7-9be7-0230af3ffa2d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690899862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2690899862
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1215347014
Short name T104
Test name
Test status
Simulation time 214043764716 ps
CPU time 410.97 seconds
Started May 21 02:44:54 PM PDT 24
Finished May 21 02:51:48 PM PDT 24
Peak memory 201856 kb
Host smart-879467e0-b5d7-4caf-9a2c-c9fcd381a82d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215347014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1215347014
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3506616634
Short name T603
Test name
Test status
Simulation time 194197245598 ps
CPU time 463.3 seconds
Started May 21 02:44:52 PM PDT 24
Finished May 21 02:52:37 PM PDT 24
Peak memory 201916 kb
Host smart-80d94d55-9afe-4ff1-b82e-fcd0dc9298c4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506616634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3506616634
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3114292445
Short name T656
Test name
Test status
Simulation time 96789181935 ps
CPU time 301.73 seconds
Started May 21 02:44:59 PM PDT 24
Finished May 21 02:50:02 PM PDT 24
Peak memory 202264 kb
Host smart-d57fd479-4ba3-4a58-9c60-cac70ae3a977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114292445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3114292445
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1658678251
Short name T585
Test name
Test status
Simulation time 38118183052 ps
CPU time 40.57 seconds
Started May 21 02:44:58 PM PDT 24
Finished May 21 02:45:41 PM PDT 24
Peak memory 201656 kb
Host smart-af307b08-0fbb-4659-97e1-3788dce25159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658678251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1658678251
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2009210170
Short name T416
Test name
Test status
Simulation time 4424986676 ps
CPU time 3.28 seconds
Started May 21 02:44:59 PM PDT 24
Finished May 21 02:45:04 PM PDT 24
Peak memory 201668 kb
Host smart-93ce66fd-85ef-49d7-b031-2ce69d786e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009210170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2009210170
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2989288507
Short name T629
Test name
Test status
Simulation time 6073891887 ps
CPU time 8.05 seconds
Started May 21 02:44:47 PM PDT 24
Finished May 21 02:44:58 PM PDT 24
Peak memory 201704 kb
Host smart-286fa9aa-960a-4716-9b6e-be393b3079a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989288507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2989288507
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3014617421
Short name T24
Test name
Test status
Simulation time 55715198336 ps
CPU time 56.94 seconds
Started May 21 02:44:58 PM PDT 24
Finished May 21 02:45:57 PM PDT 24
Peak memory 210468 kb
Host smart-24c1ceb7-3169-4b82-9b29-5ce86b6804da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014617421 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3014617421
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1842180507
Short name T582
Test name
Test status
Simulation time 409014919 ps
CPU time 1.58 seconds
Started May 21 02:45:11 PM PDT 24
Finished May 21 02:45:14 PM PDT 24
Peak memory 201552 kb
Host smart-17285d27-b159-4be1-8e51-566c6d558bc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842180507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1842180507
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2051127877
Short name T311
Test name
Test status
Simulation time 513790958825 ps
CPU time 1113.78 seconds
Started May 21 02:45:11 PM PDT 24
Finished May 21 03:03:46 PM PDT 24
Peak memory 201776 kb
Host smart-0a3df603-e3c1-46d9-890e-df4e79d892f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051127877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2051127877
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.14826621
Short name T661
Test name
Test status
Simulation time 164243640242 ps
CPU time 97.41 seconds
Started May 21 02:45:05 PM PDT 24
Finished May 21 02:46:43 PM PDT 24
Peak memory 201948 kb
Host smart-c9de069a-3438-4605-8d43-e1ddf9f987aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14826621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.14826621
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2465695568
Short name T591
Test name
Test status
Simulation time 491176572857 ps
CPU time 564.99 seconds
Started May 21 02:45:04 PM PDT 24
Finished May 21 02:54:30 PM PDT 24
Peak memory 201840 kb
Host smart-bcb2ee02-3abf-4624-9be0-9d73c4cf527f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465695568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2465695568
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3294686132
Short name T703
Test name
Test status
Simulation time 495592249367 ps
CPU time 919.21 seconds
Started May 21 02:45:04 PM PDT 24
Finished May 21 03:00:25 PM PDT 24
Peak memory 201832 kb
Host smart-bc69323b-c5b6-4cac-a459-c0cdf32015c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294686132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3294686132
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2764159875
Short name T753
Test name
Test status
Simulation time 320136766411 ps
CPU time 305.56 seconds
Started May 21 02:45:04 PM PDT 24
Finished May 21 02:50:11 PM PDT 24
Peak memory 201792 kb
Host smart-b71bef07-00a2-43fd-932f-e8764162af33
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764159875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2764159875
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1584837648
Short name T228
Test name
Test status
Simulation time 353454157033 ps
CPU time 436.21 seconds
Started May 21 02:45:06 PM PDT 24
Finished May 21 02:52:23 PM PDT 24
Peak memory 201844 kb
Host smart-6af0eb6b-e2ee-4a53-a23d-a48e68983ccf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584837648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1584837648
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1071887386
Short name T101
Test name
Test status
Simulation time 597904041350 ps
CPU time 870.74 seconds
Started May 21 02:45:09 PM PDT 24
Finished May 21 02:59:41 PM PDT 24
Peak memory 201860 kb
Host smart-0d3a7177-b7a9-4e24-8c9a-b1f361cd3f27
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071887386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1071887386
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.4070059765
Short name T218
Test name
Test status
Simulation time 127006824679 ps
CPU time 375.5 seconds
Started May 21 02:45:13 PM PDT 24
Finished May 21 02:51:30 PM PDT 24
Peak memory 202196 kb
Host smart-ec880d1c-40a5-4016-adfc-ac6dd8743f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070059765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.4070059765
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1224279066
Short name T531
Test name
Test status
Simulation time 27554799408 ps
CPU time 13.78 seconds
Started May 21 02:45:11 PM PDT 24
Finished May 21 02:45:26 PM PDT 24
Peak memory 201660 kb
Host smart-30d77fec-0250-4778-af9f-1fa0a2aeb48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224279066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1224279066
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.202142092
Short name T608
Test name
Test status
Simulation time 4372752335 ps
CPU time 3.31 seconds
Started May 21 02:45:12 PM PDT 24
Finished May 21 02:45:17 PM PDT 24
Peak memory 201680 kb
Host smart-046ce980-629f-4de3-904b-bd83db966c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202142092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.202142092
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3284741200
Short name T426
Test name
Test status
Simulation time 5613183338 ps
CPU time 8.03 seconds
Started May 21 02:44:59 PM PDT 24
Finished May 21 02:45:09 PM PDT 24
Peak memory 201664 kb
Host smart-e73a4d0b-b21c-4f8c-8a1a-eae716ef5456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284741200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3284741200
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.244891999
Short name T640
Test name
Test status
Simulation time 272494970744 ps
CPU time 267.89 seconds
Started May 21 02:45:12 PM PDT 24
Finished May 21 02:49:41 PM PDT 24
Peak memory 202248 kb
Host smart-f511acba-315e-4687-b69f-243820951796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244891999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
244891999
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1477975356
Short name T688
Test name
Test status
Simulation time 74428308289 ps
CPU time 170.4 seconds
Started May 21 02:45:10 PM PDT 24
Finished May 21 02:48:02 PM PDT 24
Peak memory 210484 kb
Host smart-c6604ed7-de2b-43af-ae80-5e24a106eda2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477975356 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1477975356
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2754672820
Short name T755
Test name
Test status
Simulation time 540772458 ps
CPU time 1.04 seconds
Started May 21 02:45:17 PM PDT 24
Finished May 21 02:45:19 PM PDT 24
Peak memory 201576 kb
Host smart-a34a9f92-bdde-4aa2-a364-bcfb0f803dba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754672820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2754672820
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.1065300767
Short name T265
Test name
Test status
Simulation time 271651641254 ps
CPU time 24.69 seconds
Started May 21 02:45:19 PM PDT 24
Finished May 21 02:45:45 PM PDT 24
Peak memory 201792 kb
Host smart-36983d48-b11e-465d-9979-4b4793041218
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065300767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.1065300767
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2557408100
Short name T736
Test name
Test status
Simulation time 321824300395 ps
CPU time 753.57 seconds
Started May 21 02:45:11 PM PDT 24
Finished May 21 02:57:46 PM PDT 24
Peak memory 201936 kb
Host smart-1cd110e1-149b-4c7a-b7f6-7e22188b2780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557408100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2557408100
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3983624664
Short name T490
Test name
Test status
Simulation time 164779331509 ps
CPU time 115.02 seconds
Started May 21 02:45:12 PM PDT 24
Finished May 21 02:47:08 PM PDT 24
Peak memory 201892 kb
Host smart-16195129-f4d4-4932-8700-80a0307a68af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983624664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3983624664
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.191497609
Short name T99
Test name
Test status
Simulation time 491870897681 ps
CPU time 1146.76 seconds
Started May 21 02:45:14 PM PDT 24
Finished May 21 03:04:22 PM PDT 24
Peak memory 201884 kb
Host smart-1efda94f-f31d-4ff0-af06-1a5a192e3b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191497609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.191497609
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1505305982
Short name T706
Test name
Test status
Simulation time 164098000250 ps
CPU time 395.47 seconds
Started May 21 02:45:11 PM PDT 24
Finished May 21 02:51:47 PM PDT 24
Peak memory 201804 kb
Host smart-7cfff7af-491e-4013-a053-86bd1aa83f4f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505305982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1505305982
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1206413668
Short name T624
Test name
Test status
Simulation time 377549282292 ps
CPU time 460.35 seconds
Started May 21 02:45:19 PM PDT 24
Finished May 21 02:53:01 PM PDT 24
Peak memory 201840 kb
Host smart-5d2c3973-795d-4b90-b04a-2bea6c0dfbbc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206413668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1206413668
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1847516975
Short name T773
Test name
Test status
Simulation time 402437867352 ps
CPU time 252.07 seconds
Started May 21 02:45:20 PM PDT 24
Finished May 21 02:49:34 PM PDT 24
Peak memory 201840 kb
Host smart-a1fec48c-2270-4275-9daf-0bd4dbfb248a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847516975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1847516975
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2623111635
Short name T718
Test name
Test status
Simulation time 123445505069 ps
CPU time 489.45 seconds
Started May 21 02:45:18 PM PDT 24
Finished May 21 02:53:28 PM PDT 24
Peak memory 202160 kb
Host smart-7a8827b5-1f58-4f89-8d6c-31183d161069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623111635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2623111635
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2561481076
Short name T165
Test name
Test status
Simulation time 32292174287 ps
CPU time 19.01 seconds
Started May 21 02:45:19 PM PDT 24
Finished May 21 02:45:39 PM PDT 24
Peak memory 201608 kb
Host smart-87dd20d4-1df0-4a7c-a445-e8cb7bb20815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561481076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2561481076
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.1328496116
Short name T530
Test name
Test status
Simulation time 3552517512 ps
CPU time 2.61 seconds
Started May 21 02:45:19 PM PDT 24
Finished May 21 02:45:24 PM PDT 24
Peak memory 201576 kb
Host smart-16ac586d-83ae-4d0f-81b0-590c8ed177b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328496116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1328496116
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.414078354
Short name T483
Test name
Test status
Simulation time 5832717817 ps
CPU time 9.08 seconds
Started May 21 02:45:12 PM PDT 24
Finished May 21 02:45:23 PM PDT 24
Peak memory 201656 kb
Host smart-fb20c61e-7fa6-4da9-9b22-7fe8d0a0efe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414078354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.414078354
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2577829772
Short name T301
Test name
Test status
Simulation time 517462858711 ps
CPU time 613.16 seconds
Started May 21 02:45:20 PM PDT 24
Finished May 21 02:55:35 PM PDT 24
Peak memory 202124 kb
Host smart-ee7dec11-3d1d-4ece-8df7-47e7d64211e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577829772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2577829772
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1683778118
Short name T53
Test name
Test status
Simulation time 84834095262 ps
CPU time 135.55 seconds
Started May 21 02:45:20 PM PDT 24
Finished May 21 02:47:37 PM PDT 24
Peak memory 210668 kb
Host smart-4eb6cac9-4c2d-4705-803f-e3c6f8243163
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683778118 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1683778118
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.4236088034
Short name T4
Test name
Test status
Simulation time 321323514 ps
CPU time 0.98 seconds
Started May 21 02:45:31 PM PDT 24
Finished May 21 02:45:33 PM PDT 24
Peak memory 201580 kb
Host smart-ce8eb152-1c50-4ab6-9d69-cf545b1bf584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236088034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.4236088034
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1450948186
Short name T317
Test name
Test status
Simulation time 170814602713 ps
CPU time 26.78 seconds
Started May 21 02:45:26 PM PDT 24
Finished May 21 02:45:55 PM PDT 24
Peak memory 201908 kb
Host smart-69242580-f91a-4ba9-95eb-3e5963aec19d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450948186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1450948186
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3454701340
Short name T679
Test name
Test status
Simulation time 167688334873 ps
CPU time 388.48 seconds
Started May 21 02:45:25 PM PDT 24
Finished May 21 02:51:55 PM PDT 24
Peak memory 201864 kb
Host smart-28acf780-465d-4c1e-946b-5961aec50434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454701340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3454701340
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1730251654
Short name T714
Test name
Test status
Simulation time 492809243860 ps
CPU time 624.36 seconds
Started May 21 02:45:28 PM PDT 24
Finished May 21 02:55:55 PM PDT 24
Peak memory 201856 kb
Host smart-1345a09d-ecea-4c03-a794-ebc69335973f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730251654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1730251654
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3909640819
Short name T49
Test name
Test status
Simulation time 164290206712 ps
CPU time 59.85 seconds
Started May 21 02:45:29 PM PDT 24
Finished May 21 02:46:31 PM PDT 24
Peak memory 201872 kb
Host smart-15dee5e5-10f4-4f0d-b978-f8ac929df1de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909640819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3909640819
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2166277726
Short name T193
Test name
Test status
Simulation time 323465640880 ps
CPU time 775.89 seconds
Started May 21 02:45:26 PM PDT 24
Finished May 21 02:58:24 PM PDT 24
Peak memory 201904 kb
Host smart-a81fb1a1-0c91-455f-8362-f8c00a54b883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166277726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2166277726
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3873758650
Short name T115
Test name
Test status
Simulation time 323892124340 ps
CPU time 175.4 seconds
Started May 21 02:45:25 PM PDT 24
Finished May 21 02:48:22 PM PDT 24
Peak memory 201856 kb
Host smart-5947f4b3-c062-4d30-9dc8-4ffccb278276
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873758650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3873758650
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3632954732
Short name T478
Test name
Test status
Simulation time 188964307814 ps
CPU time 204.14 seconds
Started May 21 02:45:25 PM PDT 24
Finished May 21 02:48:51 PM PDT 24
Peak memory 201892 kb
Host smart-4e2000d7-2c91-46c3-bde0-e0ba00ff7cf1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632954732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3632954732
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.905682520
Short name T700
Test name
Test status
Simulation time 406182529230 ps
CPU time 97.18 seconds
Started May 21 02:45:26 PM PDT 24
Finished May 21 02:47:06 PM PDT 24
Peak memory 201840 kb
Host smart-9b9a1da4-e9d5-4e2b-b144-e2c0d9d38679
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905682520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.905682520
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3875720670
Short name T482
Test name
Test status
Simulation time 82571975030 ps
CPU time 324.84 seconds
Started May 21 02:45:26 PM PDT 24
Finished May 21 02:50:53 PM PDT 24
Peak memory 202244 kb
Host smart-27f09878-c034-4761-8145-ebeabe6ac7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875720670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3875720670
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3979053456
Short name T639
Test name
Test status
Simulation time 35852685448 ps
CPU time 84.75 seconds
Started May 21 02:45:27 PM PDT 24
Finished May 21 02:46:55 PM PDT 24
Peak memory 201656 kb
Host smart-bfbe9a6a-3fa9-4800-80ec-e23a48091708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979053456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3979053456
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1920707130
Short name T29
Test name
Test status
Simulation time 3872679232 ps
CPU time 3.33 seconds
Started May 21 02:45:27 PM PDT 24
Finished May 21 02:45:33 PM PDT 24
Peak memory 201584 kb
Host smart-cef3ad21-2246-4e4a-bb3c-7ccae3431eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920707130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1920707130
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1150571542
Short name T415
Test name
Test status
Simulation time 5997531854 ps
CPU time 14.42 seconds
Started May 21 02:45:19 PM PDT 24
Finished May 21 02:45:35 PM PDT 24
Peak memory 201652 kb
Host smart-7c3624c8-97d0-42e2-80d1-d6d2e9390adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150571542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1150571542
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.858087019
Short name T683
Test name
Test status
Simulation time 332633993029 ps
CPU time 805.09 seconds
Started May 21 02:45:32 PM PDT 24
Finished May 21 02:59:00 PM PDT 24
Peak memory 201852 kb
Host smart-45ff6079-c551-4ebb-a9cd-17dcfc0a8990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858087019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
858087019
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1254067260
Short name T17
Test name
Test status
Simulation time 199073242513 ps
CPU time 354.96 seconds
Started May 21 02:45:31 PM PDT 24
Finished May 21 02:51:28 PM PDT 24
Peak memory 211488 kb
Host smart-6dbf5888-ab0f-4c59-9b16-4f3032bfe77d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254067260 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1254067260
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.4103026321
Short name T429
Test name
Test status
Simulation time 367368985 ps
CPU time 1.48 seconds
Started May 21 02:45:39 PM PDT 24
Finished May 21 02:45:42 PM PDT 24
Peak memory 201572 kb
Host smart-81bb4e38-536a-4748-b486-fc85d5d7d23d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103026321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.4103026321
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3441123298
Short name T528
Test name
Test status
Simulation time 179342014433 ps
CPU time 217.22 seconds
Started May 21 02:45:38 PM PDT 24
Finished May 21 02:49:16 PM PDT 24
Peak memory 201960 kb
Host smart-cd1ade50-81e9-4391-928a-77c15c17485f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441123298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3441123298
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.276188379
Short name T522
Test name
Test status
Simulation time 159538718006 ps
CPU time 193.68 seconds
Started May 21 02:45:31 PM PDT 24
Finished May 21 02:48:46 PM PDT 24
Peak memory 201924 kb
Host smart-5cba1025-f2c4-41e9-b798-7980aabac660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276188379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.276188379
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1585698731
Short name T631
Test name
Test status
Simulation time 325271101013 ps
CPU time 197.8 seconds
Started May 21 02:45:38 PM PDT 24
Finished May 21 02:48:58 PM PDT 24
Peak memory 201860 kb
Host smart-7d0e3b89-a0e3-4cd1-9a0e-2a0aa42f1410
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585698731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1585698731
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.136376375
Short name T499
Test name
Test status
Simulation time 162242685683 ps
CPU time 96.89 seconds
Started May 21 02:45:32 PM PDT 24
Finished May 21 02:47:11 PM PDT 24
Peak memory 201920 kb
Host smart-0a0b0319-e796-491d-8b8e-e83a69e61060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136376375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.136376375
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2717581650
Short name T453
Test name
Test status
Simulation time 495899352289 ps
CPU time 617.49 seconds
Started May 21 02:45:32 PM PDT 24
Finished May 21 02:55:51 PM PDT 24
Peak memory 201804 kb
Host smart-c71ae18d-2be2-4248-ad13-183d3deb627c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717581650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2717581650
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1644740139
Short name T319
Test name
Test status
Simulation time 546223928868 ps
CPU time 1212.1 seconds
Started May 21 02:45:41 PM PDT 24
Finished May 21 03:05:55 PM PDT 24
Peak memory 201860 kb
Host smart-cb539a7e-90af-4203-ae48-8d672ef56e08
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644740139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1644740139
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1262699140
Short name T554
Test name
Test status
Simulation time 208443736735 ps
CPU time 122.01 seconds
Started May 21 02:45:41 PM PDT 24
Finished May 21 02:47:45 PM PDT 24
Peak memory 201848 kb
Host smart-b1e29109-7486-409f-824c-d167f3f73145
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262699140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1262699140
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2349516621
Short name T617
Test name
Test status
Simulation time 117243231399 ps
CPU time 622.49 seconds
Started May 21 02:45:38 PM PDT 24
Finished May 21 02:56:03 PM PDT 24
Peak memory 202132 kb
Host smart-7e20fdec-4916-4467-9f80-462d43c688af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349516621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2349516621
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.499610304
Short name T164
Test name
Test status
Simulation time 34691011214 ps
CPU time 74.95 seconds
Started May 21 02:45:39 PM PDT 24
Finished May 21 02:46:55 PM PDT 24
Peak memory 201676 kb
Host smart-da5a1bf3-16bd-4d62-824b-c494bf27619e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499610304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.499610304
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3565214513
Short name T566
Test name
Test status
Simulation time 5395792057 ps
CPU time 3.84 seconds
Started May 21 02:45:40 PM PDT 24
Finished May 21 02:45:44 PM PDT 24
Peak memory 201640 kb
Host smart-3912ab38-94be-4bd0-8b8d-9092321e944d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565214513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3565214513
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.570467862
Short name T48
Test name
Test status
Simulation time 5833726004 ps
CPU time 3.1 seconds
Started May 21 02:45:32 PM PDT 24
Finished May 21 02:45:37 PM PDT 24
Peak memory 201620 kb
Host smart-b9df3078-5de3-4800-95b0-f893f793a42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570467862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.570467862
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1916555154
Short name T36
Test name
Test status
Simulation time 375259729790 ps
CPU time 790.62 seconds
Started May 21 02:45:39 PM PDT 24
Finished May 21 02:58:51 PM PDT 24
Peak memory 201852 kb
Host smart-75f9116e-ad27-4758-b07f-47baf69977ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916555154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1916555154
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1863196971
Short name T362
Test name
Test status
Simulation time 347792883 ps
CPU time 1.37 seconds
Started May 21 02:45:51 PM PDT 24
Finished May 21 02:45:54 PM PDT 24
Peak memory 201564 kb
Host smart-eeefd697-ebed-4867-9872-49a2c1bf1c15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863196971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1863196971
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1289741028
Short name T783
Test name
Test status
Simulation time 160096122225 ps
CPU time 83.1 seconds
Started May 21 02:45:50 PM PDT 24
Finished May 21 02:47:14 PM PDT 24
Peak memory 201832 kb
Host smart-e6ac017f-787d-43a8-8153-f4c5d3f9e685
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289741028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1289741028
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3050288511
Short name T244
Test name
Test status
Simulation time 161902320055 ps
CPU time 160.08 seconds
Started May 21 02:45:45 PM PDT 24
Finished May 21 02:48:27 PM PDT 24
Peak memory 201840 kb
Host smart-6ce15a3d-9df8-449d-b5a8-9470122aebd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050288511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3050288511
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2950678413
Short name T704
Test name
Test status
Simulation time 503677652392 ps
CPU time 1137.69 seconds
Started May 21 02:45:42 PM PDT 24
Finished May 21 03:04:42 PM PDT 24
Peak memory 201868 kb
Host smart-2fc76c72-5d7d-429f-97e9-f19b1e4e6c9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950678413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.2950678413
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1116045493
Short name T199
Test name
Test status
Simulation time 492053393418 ps
CPU time 291.87 seconds
Started May 21 02:45:43 PM PDT 24
Finished May 21 02:50:37 PM PDT 24
Peak memory 202076 kb
Host smart-a3872165-2b20-4457-8e85-5f6dea9be132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116045493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1116045493
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.4214608526
Short name T770
Test name
Test status
Simulation time 335883299072 ps
CPU time 136.95 seconds
Started May 21 02:45:43 PM PDT 24
Finished May 21 02:48:02 PM PDT 24
Peak memory 201820 kb
Host smart-fe76f54c-d81c-46bb-86f7-d37cba888908
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214608526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.4214608526
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1733292770
Short name T556
Test name
Test status
Simulation time 365998138278 ps
CPU time 224.69 seconds
Started May 21 02:45:44 PM PDT 24
Finished May 21 02:49:31 PM PDT 24
Peak memory 201852 kb
Host smart-bdb1391f-8210-4783-88b9-683510987a34
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733292770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1733292770
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2992674001
Short name T569
Test name
Test status
Simulation time 598238511422 ps
CPU time 1279.82 seconds
Started May 21 02:45:49 PM PDT 24
Finished May 21 03:07:10 PM PDT 24
Peak memory 201848 kb
Host smart-29757dc8-3aaa-44e7-bf42-2361c7184475
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992674001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2992674001
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2722734341
Short name T758
Test name
Test status
Simulation time 80133891797 ps
CPU time 334.79 seconds
Started May 21 02:45:49 PM PDT 24
Finished May 21 02:51:26 PM PDT 24
Peak memory 202228 kb
Host smart-bce2855f-3aec-43e4-8750-c1a2af62b742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722734341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2722734341
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1480225371
Short name T593
Test name
Test status
Simulation time 32402519138 ps
CPU time 71.88 seconds
Started May 21 02:45:49 PM PDT 24
Finished May 21 02:47:02 PM PDT 24
Peak memory 201672 kb
Host smart-4b8dc2a1-042f-4ad3-852f-437ebcc2d725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480225371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1480225371
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3254063114
Short name T752
Test name
Test status
Simulation time 2963537533 ps
CPU time 7.65 seconds
Started May 21 02:45:49 PM PDT 24
Finished May 21 02:45:58 PM PDT 24
Peak memory 201652 kb
Host smart-d10efad7-39fd-435b-bf3b-153b754faa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254063114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3254063114
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1470111108
Short name T387
Test name
Test status
Simulation time 5922895594 ps
CPU time 4.38 seconds
Started May 21 02:45:44 PM PDT 24
Finished May 21 02:45:51 PM PDT 24
Peak memory 201688 kb
Host smart-635c47ee-de64-4ba7-a65a-19af07e240da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470111108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1470111108
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1623930971
Short name T247
Test name
Test status
Simulation time 550473697360 ps
CPU time 1234.07 seconds
Started May 21 02:45:49 PM PDT 24
Finished May 21 03:06:25 PM PDT 24
Peak memory 201940 kb
Host smart-eaf6a2c3-982d-4cae-99e7-f6b3461e8eaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623930971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1623930971
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2823812178
Short name T56
Test name
Test status
Simulation time 75753407607 ps
CPU time 87.53 seconds
Started May 21 02:45:49 PM PDT 24
Finished May 21 02:47:18 PM PDT 24
Peak memory 210428 kb
Host smart-491d3101-fd8d-4c75-bb75-8f97d029db8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823812178 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2823812178
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1764062720
Short name T444
Test name
Test status
Simulation time 373734548 ps
CPU time 0.77 seconds
Started May 21 02:46:08 PM PDT 24
Finished May 21 02:46:11 PM PDT 24
Peak memory 201556 kb
Host smart-106979bc-d0d0-47fc-b50e-f7c32fce12cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764062720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1764062720
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2451930509
Short name T448
Test name
Test status
Simulation time 334192751525 ps
CPU time 345.29 seconds
Started May 21 02:45:55 PM PDT 24
Finished May 21 02:51:43 PM PDT 24
Peak memory 201852 kb
Host smart-32f417ea-d8fb-4569-8404-75ce91ac266c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451930509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2451930509
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.871281121
Short name T412
Test name
Test status
Simulation time 167251244956 ps
CPU time 185.01 seconds
Started May 21 02:45:57 PM PDT 24
Finished May 21 02:49:04 PM PDT 24
Peak memory 201848 kb
Host smart-a77bb5df-9c47-44c7-820b-7195221ee04e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=871281121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrup
t_fixed.871281121
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2708623910
Short name T557
Test name
Test status
Simulation time 497064854810 ps
CPU time 1257.24 seconds
Started May 21 02:45:56 PM PDT 24
Finished May 21 03:06:57 PM PDT 24
Peak memory 201848 kb
Host smart-f7a2f4ef-de04-432d-8779-20ae6da9bfb4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708623910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2708623910
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.654504493
Short name T365
Test name
Test status
Simulation time 216805479062 ps
CPU time 276.54 seconds
Started May 21 02:45:55 PM PDT 24
Finished May 21 02:50:34 PM PDT 24
Peak memory 201836 kb
Host smart-071c0008-0894-4c70-bfad-0964615d275c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654504493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.654504493
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2141154690
Short name T446
Test name
Test status
Simulation time 44305096180 ps
CPU time 23.9 seconds
Started May 21 02:46:08 PM PDT 24
Finished May 21 02:46:34 PM PDT 24
Peak memory 201640 kb
Host smart-c85b08c3-3314-4888-9052-ac4372c169c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141154690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2141154690
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1572288574
Short name T494
Test name
Test status
Simulation time 3664478517 ps
CPU time 9.96 seconds
Started May 21 02:46:03 PM PDT 24
Finished May 21 02:46:14 PM PDT 24
Peak memory 201520 kb
Host smart-4f16458c-ad10-48aa-aa62-709abce44d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572288574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1572288574
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3255833228
Short name T400
Test name
Test status
Simulation time 6099812192 ps
CPU time 14.54 seconds
Started May 21 02:45:56 PM PDT 24
Finished May 21 02:46:13 PM PDT 24
Peak memory 201664 kb
Host smart-dc2657a7-3bbe-4dea-b6dc-7730174175a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255833228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3255833228
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.724375046
Short name T26
Test name
Test status
Simulation time 197290126106 ps
CPU time 429.11 seconds
Started May 21 02:46:12 PM PDT 24
Finished May 21 02:53:24 PM PDT 24
Peak memory 201876 kb
Host smart-e35292ba-d624-4927-80ba-bdd02612f39a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724375046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
724375046
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2503978592
Short name T684
Test name
Test status
Simulation time 386460621 ps
CPU time 0.83 seconds
Started May 21 02:40:28 PM PDT 24
Finished May 21 02:40:32 PM PDT 24
Peak memory 201468 kb
Host smart-1a625734-b778-490e-96eb-f8ad289642c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503978592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2503978592
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.697095603
Short name T291
Test name
Test status
Simulation time 513079083220 ps
CPU time 340.55 seconds
Started May 21 02:40:26 PM PDT 24
Finished May 21 02:46:09 PM PDT 24
Peak memory 201956 kb
Host smart-e4b10435-a00d-471f-a821-60516496c804
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697095603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.697095603
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.747736225
Short name T786
Test name
Test status
Simulation time 170115684043 ps
CPU time 190.9 seconds
Started May 21 02:40:24 PM PDT 24
Finished May 21 02:43:35 PM PDT 24
Peak memory 201880 kb
Host smart-e3a2d8b3-94fd-4195-aa28-01fcc028f495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747736225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.747736225
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.617979985
Short name T251
Test name
Test status
Simulation time 331132251211 ps
CPU time 803.23 seconds
Started May 21 02:41:07 PM PDT 24
Finished May 21 02:54:45 PM PDT 24
Peak memory 201888 kb
Host smart-b65e738e-ccd1-4482-a343-a077806b6f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617979985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.617979985
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1674125632
Short name T465
Test name
Test status
Simulation time 164050054467 ps
CPU time 26.26 seconds
Started May 21 02:40:26 PM PDT 24
Finished May 21 02:40:55 PM PDT 24
Peak memory 201836 kb
Host smart-b4a4402f-9f8c-40e1-9503-a6a37ed54cce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674125632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1674125632
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.268951493
Short name T560
Test name
Test status
Simulation time 168017620704 ps
CPU time 351.56 seconds
Started May 21 02:40:26 PM PDT 24
Finished May 21 02:46:20 PM PDT 24
Peak memory 201840 kb
Host smart-ec26039c-4ac4-43f4-95bc-421d186b78af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268951493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.268951493
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1885431191
Short name T588
Test name
Test status
Simulation time 329037677320 ps
CPU time 219.53 seconds
Started May 21 02:40:24 PM PDT 24
Finished May 21 02:44:05 PM PDT 24
Peak memory 201796 kb
Host smart-0e189afd-06d5-478b-ba65-a3279bb1218b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885431191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1885431191
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2700695810
Short name T741
Test name
Test status
Simulation time 558306676972 ps
CPU time 967.85 seconds
Started May 21 02:40:25 PM PDT 24
Finished May 21 02:56:35 PM PDT 24
Peak memory 201896 kb
Host smart-983c7598-07e6-48b3-aea2-e659a94a9d22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700695810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2700695810
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.393725196
Short name T451
Test name
Test status
Simulation time 605985706594 ps
CPU time 269.97 seconds
Started May 21 02:40:25 PM PDT 24
Finished May 21 02:44:58 PM PDT 24
Peak memory 201848 kb
Host smart-6f316138-7fc9-41e0-9705-1d13d2181952
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393725196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.393725196
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1749318742
Short name T220
Test name
Test status
Simulation time 71592945775 ps
CPU time 312.83 seconds
Started May 21 02:40:26 PM PDT 24
Finished May 21 02:45:41 PM PDT 24
Peak memory 202144 kb
Host smart-742e4df1-dd07-4913-8dd4-05b8f4a23124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749318742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1749318742
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2724317380
Short name T100
Test name
Test status
Simulation time 48341851243 ps
CPU time 29.59 seconds
Started May 21 02:41:09 PM PDT 24
Finished May 21 02:41:52 PM PDT 24
Peak memory 201660 kb
Host smart-bf1c4bc8-d029-4af7-b2ac-fc01b255ea0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724317380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2724317380
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3363786514
Short name T583
Test name
Test status
Simulation time 5101777816 ps
CPU time 3.81 seconds
Started May 21 02:40:25 PM PDT 24
Finished May 21 02:40:31 PM PDT 24
Peak memory 201664 kb
Host smart-f27e4502-733f-4655-adec-35ab40824886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363786514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3363786514
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1771775522
Short name T411
Test name
Test status
Simulation time 5908504198 ps
CPU time 4.14 seconds
Started May 21 02:40:24 PM PDT 24
Finished May 21 02:40:31 PM PDT 24
Peak memory 201712 kb
Host smart-dfe028be-ce73-4102-a472-e9e5ee9a15da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771775522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1771775522
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1975721764
Short name T789
Test name
Test status
Simulation time 165106288041 ps
CPU time 779.78 seconds
Started May 21 02:40:28 PM PDT 24
Finished May 21 02:53:30 PM PDT 24
Peak memory 202152 kb
Host smart-60d931d0-cadd-4992-8606-db28a9484fca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975721764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1975721764
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2708099877
Short name T776
Test name
Test status
Simulation time 93260757949 ps
CPU time 56.51 seconds
Started May 21 02:40:25 PM PDT 24
Finished May 21 02:41:23 PM PDT 24
Peak memory 210184 kb
Host smart-a3c99b5c-b7b1-44ea-a7dd-d93fccbb0f44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708099877 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2708099877
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.621275402
Short name T418
Test name
Test status
Simulation time 439790945 ps
CPU time 0.9 seconds
Started May 21 02:41:08 PM PDT 24
Finished May 21 02:41:23 PM PDT 24
Peak memory 201560 kb
Host smart-0316a987-256c-479c-80fe-e08a41df5065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621275402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.621275402
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1707796114
Short name T284
Test name
Test status
Simulation time 164092875365 ps
CPU time 91.53 seconds
Started May 21 02:40:33 PM PDT 24
Finished May 21 02:42:08 PM PDT 24
Peak memory 201828 kb
Host smart-56d636c3-ad53-4627-8973-6e64fc9a2b28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707796114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1707796114
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2181768128
Short name T276
Test name
Test status
Simulation time 527869178781 ps
CPU time 621.54 seconds
Started May 21 02:40:33 PM PDT 24
Finished May 21 02:50:58 PM PDT 24
Peak memory 201784 kb
Host smart-ef4e5306-2256-4a16-91ce-6b5bfb89a9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181768128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2181768128
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.498588485
Short name T437
Test name
Test status
Simulation time 331628471592 ps
CPU time 790.68 seconds
Started May 21 02:40:32 PM PDT 24
Finished May 21 02:53:46 PM PDT 24
Peak memory 201920 kb
Host smart-73063108-7dfe-42ac-bda3-8752f645d92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498588485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.498588485
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2145506246
Short name T480
Test name
Test status
Simulation time 163517200832 ps
CPU time 277.1 seconds
Started May 21 02:40:33 PM PDT 24
Finished May 21 02:45:14 PM PDT 24
Peak memory 201860 kb
Host smart-3f00e6d4-9b0d-4915-bc7d-9c93d1ba4e06
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145506246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2145506246
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3414260579
Short name T424
Test name
Test status
Simulation time 495477970036 ps
CPU time 548.16 seconds
Started May 21 02:40:25 PM PDT 24
Finished May 21 02:49:35 PM PDT 24
Peak memory 201856 kb
Host smart-bf5a8b50-53c3-4167-894c-c47d94fbb10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414260579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3414260579
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2590831265
Short name T380
Test name
Test status
Simulation time 157541765195 ps
CPU time 182.38 seconds
Started May 21 02:41:02 PM PDT 24
Finished May 21 02:44:20 PM PDT 24
Peak memory 201768 kb
Host smart-5a657327-4495-4f74-85be-e086fe74d021
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590831265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2590831265
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2357613676
Short name T62
Test name
Test status
Simulation time 419940968555 ps
CPU time 106.1 seconds
Started May 21 02:40:41 PM PDT 24
Finished May 21 02:42:34 PM PDT 24
Peak memory 201948 kb
Host smart-a62ce831-3ce2-4e32-9b7b-ebcfa67f975a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357613676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2357613676
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.4271336516
Short name T653
Test name
Test status
Simulation time 401601482902 ps
CPU time 746.22 seconds
Started May 21 02:40:33 PM PDT 24
Finished May 21 02:53:02 PM PDT 24
Peak memory 201920 kb
Host smart-a75a35d8-eb9f-4a0f-9da4-56e4f7bf5906
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271336516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.4271336516
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3958377985
Short name T225
Test name
Test status
Simulation time 128491256486 ps
CPU time 661.39 seconds
Started May 21 02:40:33 PM PDT 24
Finished May 21 02:51:37 PM PDT 24
Peak memory 202116 kb
Host smart-156947be-e56b-4928-bd45-bb01a6c3821c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958377985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3958377985
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1277179384
Short name T367
Test name
Test status
Simulation time 42582264056 ps
CPU time 11.52 seconds
Started May 21 02:40:41 PM PDT 24
Finished May 21 02:40:59 PM PDT 24
Peak memory 201664 kb
Host smart-3ccc915d-f5c1-4f8e-bd8b-15134465cf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277179384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1277179384
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.4108263195
Short name T599
Test name
Test status
Simulation time 3422201349 ps
CPU time 8.45 seconds
Started May 21 02:40:34 PM PDT 24
Finished May 21 02:40:46 PM PDT 24
Peak memory 201620 kb
Host smart-a9c077b8-bf6b-4354-bc9a-364f5d2876ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108263195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.4108263195
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.603362371
Short name T601
Test name
Test status
Simulation time 5825300554 ps
CPU time 7.5 seconds
Started May 21 02:40:27 PM PDT 24
Finished May 21 02:40:38 PM PDT 24
Peak memory 201612 kb
Host smart-e1e778c0-285b-485f-a1e6-3be533033043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603362371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.603362371
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3449004930
Short name T239
Test name
Test status
Simulation time 332311995437 ps
CPU time 78.42 seconds
Started May 21 02:40:31 PM PDT 24
Finished May 21 02:41:52 PM PDT 24
Peak memory 201800 kb
Host smart-02a6ce2d-2867-4909-bbda-b813e24ef6b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449004930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3449004930
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.295036516
Short name T201
Test name
Test status
Simulation time 347104950 ps
CPU time 0.78 seconds
Started May 21 02:40:35 PM PDT 24
Finished May 21 02:40:39 PM PDT 24
Peak memory 201544 kb
Host smart-c3381160-b0a9-48d6-98bf-36bbd5678d94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295036516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.295036516
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.158249675
Short name T243
Test name
Test status
Simulation time 347079564978 ps
CPU time 163.79 seconds
Started May 21 02:40:42 PM PDT 24
Finished May 21 02:43:33 PM PDT 24
Peak memory 201860 kb
Host smart-6dd35300-fcdb-4b0f-8223-41a74f862c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158249675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.158249675
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3696140734
Short name T720
Test name
Test status
Simulation time 325284164945 ps
CPU time 363.65 seconds
Started May 21 02:40:39 PM PDT 24
Finished May 21 02:46:48 PM PDT 24
Peak memory 201848 kb
Host smart-d2c2e151-f24b-4b50-83f6-c53a4339bd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696140734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3696140734
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1733264597
Short name T621
Test name
Test status
Simulation time 494332367075 ps
CPU time 1207.51 seconds
Started May 21 02:40:34 PM PDT 24
Finished May 21 03:00:44 PM PDT 24
Peak memory 201776 kb
Host smart-f109a91d-dea1-4f6a-b192-806f1fca2198
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733264597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1733264597
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.612572360
Short name T536
Test name
Test status
Simulation time 483894486342 ps
CPU time 1208.29 seconds
Started May 21 02:40:40 PM PDT 24
Finished May 21 03:00:55 PM PDT 24
Peak memory 201848 kb
Host smart-34faf9f5-1fdf-49fe-9138-eafd1fdef76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612572360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.612572360
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3584311698
Short name T379
Test name
Test status
Simulation time 334006784668 ps
CPU time 739.19 seconds
Started May 21 02:40:34 PM PDT 24
Finished May 21 02:52:56 PM PDT 24
Peak memory 201832 kb
Host smart-594bbed2-dff2-4f46-9794-f1a62156a80f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584311698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3584311698
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3573880483
Short name T280
Test name
Test status
Simulation time 359100100938 ps
CPU time 188.95 seconds
Started May 21 02:40:35 PM PDT 24
Finished May 21 02:43:47 PM PDT 24
Peak memory 201848 kb
Host smart-e4681fd2-e449-4246-bba1-4b1ef97d0038
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573880483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3573880483
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.299800078
Short name T622
Test name
Test status
Simulation time 200175318052 ps
CPU time 424.38 seconds
Started May 21 02:40:34 PM PDT 24
Finished May 21 02:47:42 PM PDT 24
Peak memory 201832 kb
Host smart-fb8ab17d-c773-4e52-9d63-d0c3f1ca8037
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299800078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.299800078
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.4253440178
Short name T373
Test name
Test status
Simulation time 89569970462 ps
CPU time 345.56 seconds
Started May 21 02:40:35 PM PDT 24
Finished May 21 02:46:24 PM PDT 24
Peak memory 202076 kb
Host smart-4c25e478-22f9-41b7-a596-424c684a058f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253440178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.4253440178
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2226983498
Short name T395
Test name
Test status
Simulation time 27252613338 ps
CPU time 63.26 seconds
Started May 21 02:40:42 PM PDT 24
Finished May 21 02:41:52 PM PDT 24
Peak memory 201676 kb
Host smart-23ca3a2c-7c0d-485d-8bf9-6bc2c8424272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226983498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2226983498
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1591749667
Short name T355
Test name
Test status
Simulation time 2968737770 ps
CPU time 7.66 seconds
Started May 21 02:40:32 PM PDT 24
Finished May 21 02:40:43 PM PDT 24
Peak memory 201532 kb
Host smart-4e87eb69-cb5e-4f21-b96a-89a819843220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591749667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1591749667
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3330558042
Short name T579
Test name
Test status
Simulation time 5861122078 ps
CPU time 4.97 seconds
Started May 21 02:40:35 PM PDT 24
Finished May 21 02:40:43 PM PDT 24
Peak memory 201688 kb
Host smart-9246f9e0-e7de-4f36-acc0-91f90bf1b5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330558042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3330558042
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.770760995
Short name T460
Test name
Test status
Simulation time 331129089126 ps
CPU time 487.16 seconds
Started May 21 02:40:33 PM PDT 24
Finished May 21 02:48:44 PM PDT 24
Peak memory 210444 kb
Host smart-66d8193f-1e73-4694-8a75-2975d58d2745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770760995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.770760995
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1544579768
Short name T689
Test name
Test status
Simulation time 284712056 ps
CPU time 1.23 seconds
Started May 21 02:40:38 PM PDT 24
Finished May 21 02:40:45 PM PDT 24
Peak memory 201512 kb
Host smart-c271f140-d0fe-440c-bffc-c4a57db878e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544579768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1544579768
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.102169368
Short name T154
Test name
Test status
Simulation time 326537269683 ps
CPU time 781.64 seconds
Started May 21 02:40:34 PM PDT 24
Finished May 21 02:53:39 PM PDT 24
Peak memory 201816 kb
Host smart-54686e6d-80d3-409e-9e90-f38cb9886671
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102169368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.102169368
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1449056660
Short name T232
Test name
Test status
Simulation time 162796289939 ps
CPU time 245.15 seconds
Started May 21 02:40:35 PM PDT 24
Finished May 21 02:44:43 PM PDT 24
Peak memory 201844 kb
Host smart-ae121a3a-0b5f-4e86-b078-ac1a3d2e1a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449056660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1449056660
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1028308171
Short name T376
Test name
Test status
Simulation time 162057387264 ps
CPU time 361.24 seconds
Started May 21 02:40:39 PM PDT 24
Finished May 21 02:46:46 PM PDT 24
Peak memory 201864 kb
Host smart-96ce4260-dde6-4069-81f9-870bcbdf4367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028308171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1028308171
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3936572652
Short name T390
Test name
Test status
Simulation time 486593588731 ps
CPU time 341.41 seconds
Started May 21 02:41:09 PM PDT 24
Finished May 21 02:47:04 PM PDT 24
Peak memory 201844 kb
Host smart-241e51f9-49dc-423c-b097-d9c9b906ed1c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936572652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3936572652
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2350865402
Short name T614
Test name
Test status
Simulation time 490604478388 ps
CPU time 280.07 seconds
Started May 21 02:40:33 PM PDT 24
Finished May 21 02:45:16 PM PDT 24
Peak memory 201776 kb
Host smart-90a3b761-a996-4aad-bc02-31eb8fb8e76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350865402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2350865402
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1601342299
Short name T417
Test name
Test status
Simulation time 502422329962 ps
CPU time 130.79 seconds
Started May 21 02:40:35 PM PDT 24
Finished May 21 02:42:48 PM PDT 24
Peak memory 201852 kb
Host smart-539556fe-4642-4845-9441-4ec8e16f7f29
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601342299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1601342299
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.351556980
Short name T561
Test name
Test status
Simulation time 591721444420 ps
CPU time 1425.76 seconds
Started May 21 02:40:39 PM PDT 24
Finished May 21 03:04:31 PM PDT 24
Peak memory 201820 kb
Host smart-7f2271d5-48ef-42f3-8a4e-bf1021f7acdf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351556980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.351556980
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2191743244
Short name T578
Test name
Test status
Simulation time 128796948815 ps
CPU time 588.69 seconds
Started May 21 02:40:43 PM PDT 24
Finished May 21 02:50:39 PM PDT 24
Peak memory 202204 kb
Host smart-f874e603-0572-47a9-a79a-1410a536d076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191743244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2191743244
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2523578697
Short name T633
Test name
Test status
Simulation time 37021839181 ps
CPU time 84.06 seconds
Started May 21 02:40:40 PM PDT 24
Finished May 21 02:42:10 PM PDT 24
Peak memory 201676 kb
Host smart-e5fb6f28-92d1-4d9d-9f7e-1b5bc433c2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523578697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2523578697
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2582562229
Short name T657
Test name
Test status
Simulation time 4122417811 ps
CPU time 6.81 seconds
Started May 21 02:40:34 PM PDT 24
Finished May 21 02:40:44 PM PDT 24
Peak memory 201532 kb
Host smart-c431b0a5-bf7b-4df3-aaab-c96d1e57d209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582562229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2582562229
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2773934339
Short name T475
Test name
Test status
Simulation time 5595664440 ps
CPU time 6.43 seconds
Started May 21 02:40:37 PM PDT 24
Finished May 21 02:40:47 PM PDT 24
Peak memory 201692 kb
Host smart-30a71f44-15bf-4a51-8b74-4a2aea8afe9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773934339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2773934339
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1419147536
Short name T571
Test name
Test status
Simulation time 211471353607 ps
CPU time 230.93 seconds
Started May 21 02:41:02 PM PDT 24
Finished May 21 02:45:08 PM PDT 24
Peak memory 218628 kb
Host smart-74aa5d89-79a0-42ba-8bd3-6c9ab85b9e25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419147536 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1419147536
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.263041796
Short name T359
Test name
Test status
Simulation time 298032027 ps
CPU time 0.96 seconds
Started May 21 02:40:40 PM PDT 24
Finished May 21 02:40:47 PM PDT 24
Peak memory 201568 kb
Host smart-ebe8637a-546c-4d0c-adaf-dd23c84a9d8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263041796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.263041796
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.48673244
Short name T461
Test name
Test status
Simulation time 167668173609 ps
CPU time 296.04 seconds
Started May 21 02:40:37 PM PDT 24
Finished May 21 02:45:37 PM PDT 24
Peak memory 201892 kb
Host smart-96700395-4f35-46d5-8029-55b433a45a48
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48673244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gating
.48673244
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3112755970
Short name T180
Test name
Test status
Simulation time 327381851483 ps
CPU time 209.78 seconds
Started May 21 02:40:39 PM PDT 24
Finished May 21 02:44:14 PM PDT 24
Peak memory 201892 kb
Host smart-7bd6dccc-b2dc-4f28-b0f3-6d4757b4dcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112755970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3112755970
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2866865458
Short name T463
Test name
Test status
Simulation time 169881378856 ps
CPU time 275.32 seconds
Started May 21 02:40:38 PM PDT 24
Finished May 21 02:45:19 PM PDT 24
Peak memory 201828 kb
Host smart-52638826-1ee2-417e-9756-48567f36a0d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866865458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2866865458
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.4032370466
Short name T772
Test name
Test status
Simulation time 483887968124 ps
CPU time 559.69 seconds
Started May 21 02:40:41 PM PDT 24
Finished May 21 02:50:07 PM PDT 24
Peak memory 201832 kb
Host smart-288dfa23-1deb-4af9-89a0-c3d65d4924bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032370466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.4032370466
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.124913437
Short name T596
Test name
Test status
Simulation time 160981360641 ps
CPU time 102.84 seconds
Started May 21 02:40:38 PM PDT 24
Finished May 21 02:42:25 PM PDT 24
Peak memory 201880 kb
Host smart-edf9eb42-519f-44db-b870-bbad4c2607d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=124913437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.124913437
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.4069409696
Short name T27
Test name
Test status
Simulation time 340490455905 ps
CPU time 732.95 seconds
Started May 21 02:40:36 PM PDT 24
Finished May 21 02:52:52 PM PDT 24
Peak memory 201856 kb
Host smart-e9c42c5d-0385-4d70-baee-9ed295ef7b0d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069409696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.4069409696
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.19713696
Short name T762
Test name
Test status
Simulation time 412843659742 ps
CPU time 193.33 seconds
Started May 21 02:40:37 PM PDT 24
Finished May 21 02:43:54 PM PDT 24
Peak memory 201812 kb
Host smart-fc5c5402-8bb3-4741-aeae-85bc1b4072e2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19713696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.ad
c_ctrl_filters_wakeup_fixed.19713696
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2744592245
Short name T216
Test name
Test status
Simulation time 128431227602 ps
CPU time 450.64 seconds
Started May 21 02:41:06 PM PDT 24
Finished May 21 02:48:52 PM PDT 24
Peak memory 202080 kb
Host smart-72595452-d9fc-4e20-a777-46c67fdde275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744592245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2744592245
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3592718271
Short name T352
Test name
Test status
Simulation time 40083125984 ps
CPU time 8.02 seconds
Started May 21 02:40:38 PM PDT 24
Finished May 21 02:40:50 PM PDT 24
Peak memory 201704 kb
Host smart-642ae45a-1719-487a-8d57-74b2befce47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592718271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3592718271
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.2337904590
Short name T521
Test name
Test status
Simulation time 3989733266 ps
CPU time 9.77 seconds
Started May 21 02:40:40 PM PDT 24
Finished May 21 02:40:56 PM PDT 24
Peak memory 201628 kb
Host smart-2470d82c-5c62-49a9-8f7c-ce7e1139cdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337904590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.2337904590
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.2680103975
Short name T407
Test name
Test status
Simulation time 5626089144 ps
CPU time 13.04 seconds
Started May 21 02:40:38 PM PDT 24
Finished May 21 02:40:56 PM PDT 24
Peak memory 201692 kb
Host smart-b6887d30-9a2a-48ee-9123-2ff21aaaa306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680103975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2680103975
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2427453930
Short name T597
Test name
Test status
Simulation time 346423691377 ps
CPU time 401.56 seconds
Started May 21 02:40:41 PM PDT 24
Finished May 21 02:47:29 PM PDT 24
Peak memory 201872 kb
Host smart-2f9d6baf-8e1a-46a6-9807-9f548114024a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427453930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2427453930
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.753535200
Short name T794
Test name
Test status
Simulation time 100127825256 ps
CPU time 111.15 seconds
Started May 21 02:40:38 PM PDT 24
Finished May 21 02:42:33 PM PDT 24
Peak memory 210448 kb
Host smart-b61aed7a-547c-45eb-a934-effb220d5cb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753535200 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.753535200
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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