Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7479	1			T3	10		T6	20		T7	7
testmodes[AdcCtrlTestmodeNormal]	5739	1			T2	3		T3	8		T4	1
testmodes[AdcCtrlTestmodeLowpower]	6023	1			T1	3		T8	62		T10	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	4121	1			T3	3		T6	19		T7	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1792	1			T3	6		T7	4		T8	28
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1448	1			T8	20		T41	19		T27	14
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1844	1			T3	6		T7	4		T8	27
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2200	1			T2	2		T3	2		T5	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1369	1			T8	20		T41	15		T14	3
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1395	1			T8	22		T41	16		T14	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1414	1			T8	19		T41	19		T14	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2958	1			T1	2		T8	21		T10	18