Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27484

1

T1

40

T2

3

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23557

1

T1

38

T2

3

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3927

1

T1

2

T9

18

T12

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21334

1

T1

31

T3

18

T5

11

auto[1]

6150

1

T1

9

T2

3

T4

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23422

1

T1

23

T2

3

T3

18

auto[1]

4062

1

T1

17

T4

9

T5

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	97	1			T26	8		T218	4		T236	12
values[1]	770	1			T24	12		T25	1		T31	19
values[2]	707	1			T5	6		T9	15		T14	8
values[3]	689	1			T1	2		T25	1		T174	9
values[4]	2651	1			T2	3		T4	10		T11	11
values[5]	753	1			T24	16		T53	1		T50	20
values[6]	621	1			T1	38		T9	3		T147	5
values[7]	818	1			T5	5		T14	15		T147	1
values[8]	749	1			T28	5		T32	21		T174	11
values[9]	1342	1			T5	12		T12	10		T24	19
minimum	18287	1			T3	18		T6	20		T7	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1059	1			T5	6		T14	8		T24	12
values[1]	629	1			T1	2		T9	15		T25	1
values[2]	715	1			T25	1		T146	32		T148	1
values[3]	2707	1			T2	3		T4	10		T11	11
values[4]	691	1			T9	3		T24	16		T159	1
values[5]	592	1			T1	38		T14	3		T147	5
values[6]	929	1			T5	5		T32	21		T147	1
values[7]	620	1			T12	10		T14	12		T28	5
values[8]	932	1			T5	12		T147	10		T52	1
values[9]	323	1			T24	19		T42	2		T156	15
minimum	18287	1			T3	18		T6	20		T7	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

4181

1

T1

20

T9

9

T14

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T5	1		T14	4		T24	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T39	11		T237	3		T149	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T25	1		T174	1		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	1		T9	8		T237	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T25	1		T148	1		T43	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T146	16		T155	8		T15	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1484	1			T2	3		T4	1		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T43	6		T177	2		T217	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T24	16		T53	2		T50	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T9	3		T159	1		T158	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	22		T14	3		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T52	12		T44	1		T162	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T5	1		T32	10		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T49	11		T174	1		T155	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T44	2		T177	1		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	1		T14	6		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	1		T52	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T147	1		T148	1		T156	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T24	19		T179	20		T195	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T42	2		T156	9		T201	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18157	1			T3	18		T6	20		T7	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T5	5		T14	4		T26	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T39	10		T149	9		T239	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T174	8		T154	12		T193	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	1		T9	7		T42	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T43	1		T192	13		T151	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T146	16		T15	2		T151	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	918	1			T4	9		T11	10		T26	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T43	4		T177	1		T217	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T146	9		T47	9		T240	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T158	13		T240	4		T241	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	16		T147	4		T49	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T52	4		T242	13		T243	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	4		T32	11		T49	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T49	11		T174	10		T244	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T44	1		T177	10		T245	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	9		T14	6		T28	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	11		T154	10		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T147	9		T156	8		T186	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T179	30		T246	12		T247	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T156	6		T248	15		T38	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	2		T27	1		T39	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T26	1		T218	4		T196	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T236	4		T249	1		T250	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T24	12		T25	1		T31	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T39	11		T149	10		T239	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	1		T14	4		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	8		T237	3		T178	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T25	1		T174	1		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	1		T237	16		T42	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1473	1			T2	3		T4	1		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T146	16		T155	8		T15	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T24	16		T53	1		T50	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T240	4		T251	1		T183	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	22		T147	1		T49	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T9	3		T159	1		T52	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	1		T14	3		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T14	6		T49	11		T155	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T32	10		T157	1		T44	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T28	1		T174	1		T160	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T5	1		T24	19		T52	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	464	1			T12	1		T147	1		T148	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18157	1			T3	18		T6	20		T7	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T26	7		T252	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T236	8		T249	2		T253	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T161	5		T160	10		T44	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T39	10		T149	9		T239	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	5		T14	4		T149	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	7		T178	12		T217	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T174	8		T154	12		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T1	1		T42	1		T151	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	888	1			T4	9		T11	10		T26	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T146	16		T15	2		T43	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T46	5		T47	9		T240	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T240	4		T251	7		T183	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T1	16		T147	4		T49	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T52	4		T158	13		T242	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	4		T49	4		T40	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	6		T49	11		T244	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T32	11		T44	1		T177	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T28	4		T174	10		T160	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	11		T154	10		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	399	1			T12	9		T147	9		T211	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	2		T27	1		T39	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T5	6		T14	7		T24	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T39	14		T237	1		T149	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T25	1		T174	9		T154	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	2		T9	8		T237	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T25	1		T148	1		T43	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T146	17		T155	1		T15	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T2	3		T4	10		T11	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T43	5		T177	3		T217	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T24	1		T53	2		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	1		T159	1		T158	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	18		T14	2		T147	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T52	5		T44	1		T162	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T5	5		T32	12		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T49	12		T174	11		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T44	2		T177	11		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	10		T14	9		T28	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	12		T52	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T147	10		T148	1		T156	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T24	1		T179	32		T195	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T42	1		T156	7		T201	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18287	1			T3	18		T6	20		T7	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T14	1		T24	11		T31	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T39	7		T237	2		T149	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T193	9		T151	13		T254	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T9	7		T237	15		T42	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T43	1		T192	10		T151	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T146	15		T155	7		T15	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1162	1			T51	17		T210	17		T214	32
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T43	5		T217	9		T255	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T24	15		T50	19		T146	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	2		T158	10		T240	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	20		T14	1		T49	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T52	11		T162	3		T243	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T32	9		T49	3		T40	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T49	10		T155	2		T244	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T44	1		T181	13		T256	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	3		T160	13		T257	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T155	3		T42	2		T179	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T156	8		T258	10		T186	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T24	18		T179	18		T223	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T42	1		T156	8		T201	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T26	8		T218	1		T196	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T236	9		T249	3		T250	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T24	1		T25	1		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T39	14		T149	10		T239	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	6		T14	7		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T9	8		T237	1		T178	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T25	1		T174	9		T154	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T1	2		T237	1		T42	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1206	1			T2	3		T4	10		T11	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T146	17		T155	1		T15	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T24	1		T53	1		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T240	5		T251	8		T183	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	18		T147	5		T49	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	1		T159	1		T52	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T5	5		T14	2		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T14	9		T49	12		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T32	12		T157	1		T44	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T28	5		T174	11		T160	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T5	12		T24	1		T52	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	477	1			T12	10		T147	10		T148	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18287	1			T3	18		T6	20		T7	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T218	3		T259	8		T260	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T236	3		T253	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T24	11		T31	18		T160	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T39	7		T149	9		T186	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T14	1		T149	9		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T9	7		T237	2		T217	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T43	1		T151	13		T261	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T237	15		T42	1		T151	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1155	1			T51	17		T146	7		T210	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T146	15		T155	7		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T24	15		T50	19		T162	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T240	3		T183	7		T235	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T1	20		T49	10		T186	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T9	2		T52	11		T158	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	1		T49	3		T40	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	3		T49	10		T155	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T32	9		T44	1		T191	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T160	13		T257	2		T47	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T24	18		T155	3		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	386	1			T42	1		T156	16		T258	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

auto[0]

4181

1

T1

20

T9

9

T14

5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27484

1

T1

40

T2

3

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24078

1

T1

9

T2

3

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3406

1

T1

31

T5

12

T9

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21458

1

T1

11

T3

18

T5

23

auto[1]

6026

1

T1

29

T2

3

T4

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23422

1

T1

23

T2

3

T3

18

auto[1]

4062

1

T1

17

T4

9

T5

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	6	1			T53	1		T262	5		-	-
values[0]	15	1			T263	8		T264	1		T265	2
values[1]	830	1			T9	15		T32	21		T53	1
values[2]	785	1			T5	5		T12	10		T28	5
values[3]	716	1			T1	9		T174	9		T42	3
values[4]	601	1			T5	6		T24	19		T147	1
values[5]	2683	1			T2	3		T4	10		T11	11
values[6]	927	1			T1	29		T5	12		T14	12
values[7]	775	1			T1	2		T9	3		T14	3
values[8]	715	1			T31	19		T49	22		T50	20
values[9]	1144	1			T24	12		T25	2		T26	8
minimum	18287	1			T3	18		T6	20		T7	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1087	1			T9	15		T32	21		T53	1
values[1]	742	1			T1	9		T5	5		T12	10
values[2]	690	1			T5	6		T24	19		T147	1
values[3]	2648	1			T2	3		T4	10		T11	11
values[4]	730	1			T5	12		T14	20		T147	5
values[5]	886	1			T1	29		T9	3		T14	3
values[6]	678	1			T1	2		T24	16		T49	21
values[7]	768	1			T26	8		T31	19		T49	22
values[8]	833	1			T24	12		T25	1		T147	10
values[9]	127	1			T25	1		T149	2		T186	9
minimum	18295	1			T3	18		T6	20		T7	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

4181

1

T1

20

T9

9

T14

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T32	10		T148	1		T162	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T9	8		T53	1		T15	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	9		T5	1		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T28	1		T257	3		T239	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T5	1		T24	19		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T146	8		T174	1		T42	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1458	1			T2	3		T4	1		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T159	1		T42	3		T158	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T14	6		T147	1		T39	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	1		T14	4		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T26	1		T40	27		T155	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	13		T9	3		T14	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T24	16		T191	4		T46	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	1		T49	11		T50	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T26	1		T52	1		T146	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T31	19		T49	11		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T25	1		T53	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T24	12		T147	1		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T25	1		T86	1		T266	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T149	1		T186	7		T162	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18160	1			T3	18		T6	20		T7	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T32	11		T151	13		T248	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	7		T15	2		T154	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	4		T12	9		T49	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T28	4		T257	4		T239	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T5	5		T201	4		T151	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T146	9		T174	8		T42	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	903	1			T4	9		T11	10		T215	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T42	2		T158	13		T44	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T14	6		T147	4		T39	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	11		T14	4		T174	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T26	10		T40	24		T149	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	16		T150	6		T267	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T46	5		T179	17		T242	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T1	1		T49	10		T52	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T26	7		T146	16		T186	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T49	11		T152	4		T268	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T154	12		T156	14		T43	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T147	9		T161	5		T160	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T86	1		T266	7		T184	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T149	1		T186	2		T222	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T14	2		T27	1		T39	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T53	1		T262	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T263	3		T265	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T264	1		T269	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T32	10		T162	4		T47	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T9	8		T53	1		T15	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	1		T12	1		T49	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T28	1		T257	3		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	9		T194	1		T44	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T174	1		T42	2		T149	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	1		T24	19		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T159	1		T146	8		T42	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1485	1			T2	3		T4	1		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	4		T157	1		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T14	6		T147	1		T40	27
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T1	13		T5	1		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T24	16		T26	1		T43	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T1	1		T9	3		T14	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T146	16		T173	1		T186	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T31	19		T49	11		T50	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	383	1			T25	2		T26	1		T52	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T24	12		T147	1		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18157	1			T3	18		T6	20		T7	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T263	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T269	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T32	11		T47	9		T270	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	7		T15	2		T154	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	4		T12	9		T49	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T28	4		T257	4		T151	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T44	1		T151	13		T271	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T174	8		T42	1		T149	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T5	5		T272	4		T179	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T146	9		T42	2		T158	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	915	1			T4	9		T11	10		T215	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T14	4		T35	14		T255	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	6		T147	4		T40	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T1	16		T5	11		T52	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T26	10		T43	13		T177	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	1		T49	10		T211	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T146	16		T186	7		T242	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T49	11		T267	7		T268	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T26	7		T154	12		T156	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T147	9		T161	5		T160	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	2		T27	1		T39	4