Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27484

1

T1

40

T2

3

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21749

1

T1

2

T3

18

T6

20

auto[ADC_CTRL_FILTER_COND_OUT]

5735

1

T1

38

T2

3

T4

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21204

1

T1

11

T3

18

T5

11

auto[1]

6280

1

T1

29

T2

3

T4

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23422

1

T1

23

T2

3

T3

18

auto[1]

4062

1

T1

17

T4

9

T5

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	51	1			T52	16		T35	15		T207	15
values[0]	89	1			T168	13		T21	8		T326	15
values[1]	616	1			T9	15		T14	12		T32	21
values[2]	567	1			T24	12		T147	1		T49	21
values[3]	806	1			T1	2		T5	17		T14	3
values[4]	778	1			T5	6		T147	5		T53	1
values[5]	769	1			T1	29		T25	1		T26	11
values[6]	746	1			T9	3		T25	1		T49	22
values[7]	791	1			T1	9		T24	19		T237	3
values[8]	694	1			T26	8		T148	1		T42	2
values[9]	3290	1			T2	3		T4	10		T11	11
minimum	18287	1			T3	18		T6	20		T7	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	887	1			T9	15		T14	12		T24	12
values[1]	2772	1			T2	3		T4	10		T5	12
values[2]	746	1			T1	2		T5	11		T14	3
values[3]	786	1			T31	19		T50	20		T39	21
values[4]	729	1			T1	29		T25	1		T26	11
values[5]	772	1			T9	3		T24	19		T25	1
values[6]	769	1			T26	8		T148	1		T42	2
values[7]	663	1			T1	9		T159	1		T149	14
values[8]	899	1			T12	10		T14	8		T24	16
values[9]	165	1			T25	1		T43	12		T277	1
minimum	18296	1			T3	18		T6	20		T7	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

4181

1

T1

20

T9

9

T14

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T9	8		T24	12		T32	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	6		T49	11		T175	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T239	1		T44	2		T162	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1516	1			T2	3		T4	1		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T1	1		T147	1		T155	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	2		T14	3		T53	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T40	27		T154	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T31	19		T50	20		T39	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T25	1		T49	15		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T1	13		T26	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T154	1		T151	15		T255	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T9	3		T24	19		T25	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T26	1		T148	1		T42	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T156	9		T160	14		T177	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T149	10		T152	1		T272	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T1	9		T159	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	1		T155	8		T194	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T14	4		T24	16		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T25	1		T43	1		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T277	1		T219	1		T275	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18157	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T327	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	7		T32	11		T146	25
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	6		T49	10		T44	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T239	10		T44	1		T152	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	942	1			T4	9		T5	11		T11	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	1		T147	4		T156	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	9		T15	2		T201	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T40	24		T154	10		T192	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T39	10		T174	10		T211	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T49	15		T161	5		T211	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	16		T26	10		T150	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T154	12		T151	16		T255	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T160	10		T43	13		T186	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T26	7		T257	4		T151	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T156	6		T160	8		T178	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T149	2		T152	4		T272	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T149	1		T267	7		T217	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T12	9		T177	11		T35	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T14	4		T28	4		T147	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T43	11		T182	2		T314	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T275	15		T301	1		T318	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	2		T27	1		T39	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T327	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T35	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T52	12		T207	15		T318	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T168	9		T21	3		T326	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T328	1		T329	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T9	8		T32	10		T146	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T14	6		T44	4		T47	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T24	12		T147	1		T146	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T49	11		T53	1		T174	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	1		T155	4		T157	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	2		T14	3		T39	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T147	1		T40	27		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	1		T53	1		T52	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T25	1		T49	4		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T1	13		T26	1		T31	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T49	11		T211	1		T192	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T9	3		T25	1		T237	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T154	1		T43	1		T162	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	9		T24	19		T237	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T26	1		T148	1		T42	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T160	14		T149	1		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T12	1		T25	1		T155	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1647	1			T2	3		T4	1		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18157	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T35	14		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T52	4		T318	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T168	4		T21	5		T326	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T328	10		T329	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T9	7		T32	11		T146	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T14	6		T44	1		T47	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T146	9		T239	10		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T49	10		T174	8		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	1		T216	13		T179	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	15		T39	10		T42	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T147	4		T40	24		T154	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	5		T174	10		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T49	4		T161	5		T149	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	16		T26	10		T150	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T49	11		T211	2		T192	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T160	10		T186	2		T152	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T154	12		T151	13		T323	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T156	6		T43	13		T178	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T26	7		T257	4		T152	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T160	8		T149	1		T217	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T12	9		T149	2		T43	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1060	1			T4	9		T11	10		T14	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	2		T27	1		T39	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T9	8		T24	1		T32	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T14	9		T49	11		T175	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T239	11		T44	2		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1274	1			T2	3		T4	10		T5	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T1	2		T147	5		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	11		T14	2		T53	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T40	28		T154	11		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T31	1		T50	1		T39	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T25	1		T49	17		T161	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T1	17		T26	11		T150	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T154	13		T151	17		T255	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	1		T24	1		T25	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T26	8		T148	1		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T156	7		T160	9		T177	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T149	3		T152	5		T272	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	1		T159	1		T149	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T12	10		T155	1		T194	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T14	7		T24	1		T28	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T25	1		T43	12		T182	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T277	1		T219	1		T275	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18287	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T327	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T9	7		T24	11		T32	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	3		T49	10		T175	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T44	1		T162	12		T255	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1184	1			T51	17		T210	17		T42	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T155	3		T156	8		T43	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	1		T15	2		T191	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T40	23		T175	4		T192	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T31	18		T50	19		T39	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T49	13		T149	9		T186	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T1	12		T217	7		T248	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T151	14		T255	14		T228	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	2		T24	18		T237	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T42	1		T257	2		T162	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T156	8		T160	13		T240	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T149	9		T183	7		T263	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T1	8		T217	18		T286	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T155	7		T163	9		T248	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	1		T24	15		T52	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T314	3		T330	2		T331	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T301	1		T332	11		T333	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T35	15		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T52	5		T207	1		T318	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T168	5		T21	6		T326	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T328	11		T329	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	8		T32	12		T146	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	9		T44	4		T47	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T24	1		T147	1		T146	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T49	11		T53	1		T174	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	2		T155	1		T157	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T5	17		T14	2		T39	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T147	5		T40	28		T154	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T5	6		T53	1		T52	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T25	1		T49	5		T161	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	17		T26	11		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T49	12		T211	3		T192	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T9	1		T25	1		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T154	13		T43	1		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	1		T24	1		T237	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T26	8		T148	1		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T160	9		T149	2		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T12	10		T25	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1419	1			T2	3		T4	10		T11	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18287	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T52	11		T207	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T168	8		T21	2		T326	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	7		T32	9		T146	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T14	3		T44	1		T47	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T24	11		T146	7		T43	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T49	10		T175	13		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T155	3		T201	6		T179	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	1		T39	7		T42	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T40	23		T156	8		T175	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T15	2		T42	1		T191	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T49	3		T149	9		T192	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	12		T31	18		T50	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T49	10		T192	3		T151	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	2		T237	15		T160	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T162	3		T151	13		T181	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	8		T24	18		T237	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T42	1		T257	2		T325	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T160	13		T217	18		T286	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T155	7		T149	9		T163	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1288	1			T14	1		T24	15		T51	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

auto[0]

4181

1

T1

20

T9

9

T14

5