Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27484

1

T1

40

T2

3

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24030

1

T1

9

T2

3

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3454

1

T1

31

T5

18

T9

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21575

1

T1

11

T3

18

T5

17

auto[1]

5909

1

T1

29

T2

3

T4

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23422

1

T1

23

T2

3

T3

18

auto[1]

4062

1

T1

17

T4

9

T5

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	194	1			T53	1		T160	22		T149	2
values[0]	6	1			T264	1		T208	1		T269	4
values[1]	861	1			T9	15		T32	21		T53	1
values[2]	784	1			T5	5		T12	10		T28	5
values[3]	696	1			T1	9		T5	6		T174	9
values[4]	606	1			T24	19		T147	1		T159	1
values[5]	2699	1			T2	3		T4	10		T11	11
values[6]	890	1			T1	29		T5	12		T14	12
values[7]	762	1			T1	2		T9	3		T14	3
values[8]	746	1			T31	19		T49	22		T50	20
values[9]	953	1			T24	12		T25	2		T26	8
minimum	18287	1			T3	18		T6	20		T7	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	924	1			T9	15		T32	21		T53	1
values[1]	682	1			T5	5		T12	10		T28	5
values[2]	721	1			T1	9		T5	6		T24	19
values[3]	2744	1			T2	3		T4	10		T11	11
values[4]	697	1			T14	20		T147	5		T39	21
values[5]	813	1			T1	29		T5	12		T9	3
values[6]	669	1			T1	2		T24	16		T49	21
values[7]	813	1			T26	8		T31	19		T49	22
values[8]	867	1			T24	12		T25	1		T147	10
values[9]	94	1			T25	1		T149	2		T162	13
minimum	18460	1			T3	18		T6	20		T7	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

4181

1

T1

20

T9

9

T14

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T32	10		T148	1		T162	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T9	8		T53	1		T15	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	1		T12	1		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T257	3		T239	1		T175	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	9		T147	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T5	1		T24	19		T146	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1489	1			T2	3		T4	1		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T159	1		T42	3		T158	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T14	10		T147	1		T39	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T267	1		T216	1		T302	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T40	27		T237	3		T43	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T1	13		T5	1		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T52	12		T191	4		T46	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	1		T24	16		T49	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T26	1		T52	1		T146	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T31	19		T49	11		T173	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T25	1		T53	1		T237	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T24	12		T147	1		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T25	1		T334	1		T273	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T149	1		T162	13		T290	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18216	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T251	10		T16	3		T263	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T32	11		T151	13		T47	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	7		T15	2		T154	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	4		T12	9		T28	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T257	4		T239	10		T45	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T151	13		T271	11		T179	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	5		T146	9		T174	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	924	1			T4	9		T11	10		T215	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T42	2		T158	13		T44	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	10		T147	4		T39	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T267	5		T216	2		T302	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T40	24		T43	24		T177	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	16		T5	11		T26	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T52	4		T46	5		T179	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T1	1		T49	10		T211	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T26	7		T146	16		T268	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T49	11		T186	7		T152	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T154	12		T156	14		T166	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T147	9		T161	5		T160	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T334	12		T273	15		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T149	1		T305	3		T335	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	2		T27	1		T39	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T251	2		T16	1		T263	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T53	1		T219	1		T336	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T160	14		T149	1		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T208	1		T269	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T264	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T32	10		T160	11		T162	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T9	8		T53	1		T15	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	1		T12	1		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T257	3		T175	5		T201	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	9		T194	1		T151	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	1		T174	1		T42	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T147	1		T148	1		T42	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T24	19		T159	1		T146	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1495	1			T2	3		T4	1		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T35	1		T201	15		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T14	6		T39	11		T40	27
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	13		T5	1		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T52	12		T43	5		T177	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	1		T9	3		T14	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T52	1		T146	16		T268	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T31	19		T49	11		T50	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T25	2		T26	1		T237	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T24	12		T147	1		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18157	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T266	7		T301	1		T184	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T160	8		T149	1		T325	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T269	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T32	11		T160	10		T47	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T9	7		T15	2		T154	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	4		T12	9		T28	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T257	4		T151	16		T271	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T151	13		T271	11		T168	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	5		T174	8		T42	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T272	4		T179	13		T276	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T146	9		T42	2		T158	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	890	1			T4	9		T11	10		T14	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T35	14		T201	22		T216	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T14	6		T39	10		T40	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	16		T5	11		T150	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T52	4		T43	13		T177	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	1		T26	10		T49	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T146	16		T268	2		T242	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T49	11		T186	7		T267	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T26	7		T154	12		T156	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T147	9		T161	5		T43	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	2		T27	1		T39	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T32	12		T148	1		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	8		T53	1		T15	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	5		T12	10		T28	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T257	5		T239	11		T175	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	1		T147	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T5	6		T24	1		T146	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T2	3		T4	10		T11	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T159	1		T42	3		T158	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	16		T147	5		T39	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T267	6		T216	3		T302	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T40	28		T237	1		T43	26
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	17		T5	12		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T52	5		T191	1		T46	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	2		T24	1		T49	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T26	8		T52	1		T146	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T31	1		T49	12		T173	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T25	1		T53	1		T237	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T24	1		T147	10		T161	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T25	1		T334	13		T273	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T149	2		T162	1		T290	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18323	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T251	3		T16	3		T263	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T32	9		T162	3		T151	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	7		T15	2		T151	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T49	3		T155	7		T43	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T257	2		T175	4		T201	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	8		T42	1		T151	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T24	18		T146	7		T42	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1160	1			T51	17		T155	2		T210	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T42	2		T158	10		T44	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	4		T39	7		T149	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T255	14		T168	8		T256	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T40	23		T237	2		T43	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T1	12		T9	2		T14	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T52	11		T191	3		T46	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T24	15		T49	10		T50	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T146	15		T256	6		T254	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T31	18		T49	10		T186	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T237	15		T156	16		T175	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T24	11		T160	13		T43	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T273	14		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T162	12		T335	16		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T160	10		T270	13		T337	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T251	9		T16	1		T263	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T53	1		T219	1		T336	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T160	9		T149	2		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T208	1		T269	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T264	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T32	12		T160	11		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	8		T53	1		T15	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T5	5		T12	10		T28	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T257	5		T175	1		T201	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	1		T194	1		T151	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	6		T174	9		T42	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T147	1		T148	1		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T24	1		T159	1		T146	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T2	3		T4	10		T11	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T35	15		T201	23		T216	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T14	9		T39	14		T40	28
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	17		T5	12		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T52	5		T43	14		T177	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	2		T9	1		T14	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T52	1		T146	17		T268	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T31	1		T49	12		T50	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T25	2		T26	8		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T24	1		T147	10		T161	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18287	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T266	3		T301	1		T23	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T160	13		T325	2		T338	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T32	9		T160	10		T162	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T9	7		T15	2		T217	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T49	3		T155	7		T43	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T257	2		T175	4		T201	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	8		T151	13		T168	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T42	1		T149	9		T217	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T42	1		T179	6		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T24	18		T146	7		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1171	1			T14	1		T51	17		T155	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T201	14		T255	14		T241	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T14	3		T39	7		T40	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	12		T155	3		T261	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T52	11		T43	4		T191	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T9	2		T14	1		T24	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T146	15		T256	6		T254	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T31	18		T49	10		T50	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T237	15		T156	16		T175	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T24	11		T43	5		T186	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

auto[0]

4181

1

T1

20

T9

9

T14

5