Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27484

1

T1

40

T2

3

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23560

1

T1

38

T2

3

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3924

1

T1

2

T9

18

T12

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21335

1

T1

31

T3

18

T5

11

auto[1]

6149

1

T1

9

T2

3

T4

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23422

1

T1

23

T2

3

T3

18

auto[1]

4062

1

T1

17

T4

9

T5

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	237	1			T148	1		T155	4		T156	15
values[0]	78	1			T218	4		T303	17		T236	12
values[1]	781	1			T24	12		T25	1		T26	8
values[2]	736	1			T5	6		T14	8		T25	1
values[3]	656	1			T1	2		T9	15		T25	1
values[4]	2704	1			T2	3		T4	10		T11	11
values[5]	655	1			T24	16		T53	1		T50	20
values[6]	667	1			T1	38		T9	3		T147	5
values[7]	915	1			T5	5		T14	3		T32	21
values[8]	628	1			T14	12		T28	5		T174	11
values[9]	1140	1			T5	12		T12	10		T24	19
minimum	18287	1			T3	18		T6	20		T7	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	820	1			T5	6		T14	8		T24	12
values[1]	602	1			T1	2		T9	15		T25	1
values[2]	711	1			T25	1		T146	32		T148	1
values[3]	2671	1			T2	3		T4	10		T11	11
values[4]	673	1			T9	3		T24	16		T159	1
values[5]	672	1			T1	38		T14	3		T147	5
values[6]	871	1			T5	5		T14	12		T32	21
values[7]	636	1			T12	10		T28	5		T174	11
values[8]	1020	1			T5	12		T147	10		T52	1
values[9]	243	1			T24	19		T42	2		T156	15
minimum	18565	1			T3	18		T6	20		T7	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

4181

1

T1

20

T9

9

T14

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	1		T14	4		T24	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T39	11		T237	3		T149	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T25	1		T174	1		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	1		T9	8		T237	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T25	1		T148	1		T43	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T146	16		T155	8		T15	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1485	1			T2	3		T4	1		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T43	6		T177	2		T217	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T24	16		T53	2		T50	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T9	3		T159	1		T158	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	22		T14	3		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T52	12		T44	1		T162	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T5	1		T32	10		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T14	6		T49	11		T155	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T44	2		T177	1		T191	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	1		T28	1		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	1		T52	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T147	1		T148	1		T156	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T24	19		T179	20		T223	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T42	2		T156	9		T248	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18282	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T236	14		T118	11		T250	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	5		T14	4		T26	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T39	10		T149	9		T239	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T174	8		T154	12		T42	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T1	1		T9	7		T217	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T43	1		T192	13		T151	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T146	16		T15	2		T151	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T4	9		T11	10		T26	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T43	4		T177	1		T217	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T146	9		T47	9		T240	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T158	13		T240	4		T183	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	16		T147	4		T49	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T52	4		T242	13		T243	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	4		T32	11		T49	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	6		T49	11		T244	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T44	1		T177	10		T245	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	9		T28	4		T174	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	11		T154	10		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T147	9		T156	8		T186	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T179	30		T246	12		T247	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T156	6		T248	15		T38	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T14	2		T27	1		T161	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T236	10		T23	1		T253	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T155	4		T152	1		T197	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T148	1		T156	9		T201	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T218	4		T196	1		T259	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T303	10		T236	4		T249	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T24	12		T25	1		T26	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T39	11		T149	10		T43	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	1		T14	4		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T237	3		T239	1		T178	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T25	1		T174	1		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T1	1		T9	8		T237	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1483	1			T2	3		T4	1		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T146	16		T155	8		T15	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T24	16		T53	1		T50	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T177	1		T240	4		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	22		T147	1		T49	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T9	3		T159	1		T52	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	1		T14	3		T32	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T49	11		T155	3		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T157	1		T44	2		T191	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	6		T28	1		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	1		T24	19		T52	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	394	1			T12	1		T147	1		T211	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18157	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T152	4		T246	12		T247	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T156	6		T302	13		T228	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T303	7		T236	8		T249	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T26	7		T161	5		T160	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T39	10		T149	9		T43	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	5		T14	4		T42	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T239	10		T178	12		T217	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T174	8		T154	12		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	1		T9	7		T151	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	902	1			T4	9		T11	10		T26	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T146	16		T15	2		T43	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T146	9		T47	9		T240	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T240	4		T251	7		T183	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T1	16		T147	4		T49	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T52	4		T158	13		T242	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	4		T32	11		T49	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T49	11		T244	17		T228	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T44	1		T201	4		T245	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T14	6		T28	4		T174	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	11		T154	10		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T12	9		T147	9		T211	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	2		T27	1		T39	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	6		T14	7		T24	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T39	14		T237	1		T149	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T25	1		T174	9		T154	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	2		T9	8		T237	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T25	1		T148	1		T43	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T146	17		T155	1		T15	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T2	3		T4	10		T11	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T43	5		T177	3		T217	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T24	1		T53	2		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T9	1		T159	1		T158	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	18		T14	2		T147	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T52	5		T44	1		T162	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T5	5		T32	12		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	9		T49	12		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T44	2		T177	11		T191	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	10		T28	5		T174	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	12		T52	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	378	1			T147	10		T148	1		T156	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T24	1		T179	32		T223	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T42	1		T156	7		T248	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18396	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T236	12		T118	1		T250	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	1		T24	11		T31	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T39	7		T237	2		T149	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T42	1		T193	9		T151	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T9	7		T237	15		T217	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T43	1		T192	10		T151	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T146	15		T155	7		T15	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1162	1			T51	17		T210	17		T214	32
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T43	5		T217	9		T255	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T24	15		T50	19		T146	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	2		T158	10		T240	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T1	20		T14	1		T49	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T52	11		T162	3		T243	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T32	9		T49	3		T40	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T14	3		T49	10		T155	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T44	1		T191	3		T256	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T160	13		T257	2		T163	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T155	3		T42	2		T179	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T156	8		T258	10		T186	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T24	18		T179	18		T223	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T42	1		T156	8		T248	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T44	1		T270	13		T286	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T236	12		T118	10		T23	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T155	1		T152	5		T197	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T148	1		T156	7		T201	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T218	1		T196	1		T259	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T303	8		T236	9		T249	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T24	1		T25	1		T26	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T39	14		T149	10		T43	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	6		T14	7		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T237	1		T239	11		T178	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T25	1		T174	9		T154	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T1	2		T9	8		T237	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T2	3		T4	10		T11	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T146	17		T155	1		T15	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T24	1		T53	1		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T177	1		T240	5		T251	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	18		T147	5		T49	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T9	1		T159	1		T52	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T5	5		T14	2		T32	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T49	12		T155	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T157	1		T44	2		T191	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	9		T28	5		T174	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T5	12		T24	1		T52	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	395	1			T12	10		T147	10		T211	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18287	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T155	3		T332	11		T246	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T156	8		T201	6		T228	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T218	3		T259	8		T339	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T303	9		T236	3		T253	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T24	11		T31	18		T160	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T39	7		T149	9		T186	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T14	1		T42	1		T149	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T237	2		T217	7		T338	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T43	1		T151	13		T261	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T9	7		T237	15		T151	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1160	1			T51	17		T210	17		T214	32
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T146	15		T155	7		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T24	15		T50	19		T146	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T240	3		T183	7		T235	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	20		T49	10		T186	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T9	2		T52	11		T158	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	1		T32	9		T49	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T49	10		T155	2		T175	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T44	1		T191	3		T164	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T14	3		T160	13		T257	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T24	18		T42	2		T179	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T42	1		T156	8		T258	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

auto[0]

4181

1

T1

20

T9

9

T14

5