Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27484

1

T1

40

T2

3

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21777

1

T1

2

T3

18

T6

20

auto[ADC_CTRL_FILTER_COND_OUT]

5707

1

T1

38

T2

3

T4

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21150

1

T1

11

T3

18

T5

11

auto[1]

6334

1

T1

29

T2

3

T4

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23422

1

T1

23

T2

3

T3

18

auto[1]

4062

1

T1

17

T4

9

T5

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	263	1			T14	8		T155	8		T43	12
values[0]	64	1			T326	15		T340	7		T329	5
values[1]	665	1			T9	15		T14	12		T32	21
values[2]	563	1			T24	12		T49	21		T146	17
values[3]	861	1			T1	2		T5	17		T14	3
values[4]	724	1			T5	6		T147	5		T52	1
values[5]	719	1			T25	1		T26	11		T31	19
values[6]	762	1			T1	29		T9	3		T25	1
values[7]	832	1			T1	9		T24	19		T26	8
values[8]	660	1			T148	1		T42	2		T160	22
values[9]	3084	1			T2	3		T4	10		T11	11
minimum	18287	1			T3	18		T6	20		T7	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	665	1			T32	21		T147	1		T49	21
values[1]	2792	1			T1	2		T2	3		T4	10
values[2]	779	1			T5	11		T14	3		T147	5
values[3]	761	1			T31	19		T50	20		T40	51
values[4]	695	1			T25	1		T26	11		T49	30
values[5]	826	1			T1	29		T9	3		T24	19
values[6]	723	1			T1	9		T26	8		T148	1
values[7]	646	1			T42	2		T160	22		T149	14
values[8]	960	1			T12	10		T14	8		T24	16
values[9]	135	1			T25	1		T43	12		T219	1
minimum	18502	1			T3	18		T6	20		T7	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

4181

1

T1

20

T9

9

T14

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T32	10		T147	1		T146	24
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T49	11		T175	14		T178	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	1		T24	12		T155	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1505	1			T2	3		T4	1		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T147	1		T156	9		T157	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	2		T14	3		T53	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T40	27		T154	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T31	19		T50	20		T174	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T25	1		T49	15		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T26	1		T150	1		T216	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T151	15		T255	15		T228	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T1	13		T9	3		T24	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T26	1		T148	1		T257	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	9		T156	9		T177	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T42	2		T149	10		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T160	14		T149	1		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T12	1		T155	8		T194	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T14	4		T24	16		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T25	1		T43	1		T314	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T219	1		T275	1		T301	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18211	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T14	6		T44	4		T270	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T32	11		T146	25		T158	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T49	10		T47	9		T242	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	1		T239	10		T44	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	937	1			T4	9		T5	11		T11	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T147	4		T156	8		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	9		T39	10		T15	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T40	24		T154	10		T217	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T174	10		T211	13		T42	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T49	15		T161	5		T211	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T26	10		T150	6		T216	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T151	16		T255	12		T228	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	16		T154	12		T160	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T26	7		T257	4		T151	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T156	6		T178	12		T228	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T149	2		T152	4		T302	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T160	8		T149	1		T267	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T12	9		T177	11		T35	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	4		T28	4		T147	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T43	11		T314	4		T341	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T275	15		T301	1		T333	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	7		T14	2		T27	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T14	6		T44	1		T270	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T155	8		T43	1		T177	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T14	4		T286	18		T219	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T326	11		T340	3		T253	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T329	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T9	8		T32	10		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T14	6		T44	4		T47	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T24	12		T146	8		T239	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T49	11		T174	1		T175	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T1	1		T155	4		T157	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	2		T14	3		T53	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T147	1		T40	27		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	1		T52	1		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T25	1		T49	4		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T26	1		T31	19		T50	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T49	11		T211	1		T192	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	13		T9	3		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T26	1		T43	1		T162	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	9		T24	19		T237	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T148	1		T42	2		T257	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T160	14		T149	1		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T12	1		T25	1		T194	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1593	1			T2	3		T4	1		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18157	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T43	11		T177	1		T35	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T14	4		T286	17		T301	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T326	4		T340	4		T253	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T329	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T9	7		T32	11		T146	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	6		T44	1		T47	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T146	9		T239	10		T44	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T49	10		T174	8		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	1		T43	4		T216	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	15		T39	10		T42	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T147	4		T40	24		T154	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	5		T174	10		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T49	4		T161	5		T149	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T26	10		T248	15		T244	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T49	11		T211	2		T192	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	16		T160	10		T150	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T26	7		T151	13		T86	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T154	12		T156	6		T43	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T257	4		T302	13		T272	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T160	8		T149	1		T217	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	9		T149	2		T177	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1006	1			T4	9		T11	10		T28	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	2		T27	1		T39	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T32	12		T147	1		T146	27
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T49	11		T175	1		T178	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	2		T24	1		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1269	1			T2	3		T4	10		T5	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T147	5		T156	9		T157	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	11		T14	2		T53	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T40	28		T154	11		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T31	1		T50	1		T174	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T25	1		T49	17		T161	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T26	11		T150	7		T216	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T151	17		T255	13		T228	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T1	17		T9	1		T24	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T26	8		T148	1		T257	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	1		T156	7		T177	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T42	1		T149	3		T152	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T160	9		T149	2		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T12	10		T155	1		T194	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T14	7		T24	1		T28	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T25	1		T43	12		T314	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T219	1		T275	16		T301	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18324	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T14	9		T44	4		T270	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T32	9		T146	22		T158	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T49	10		T175	13		T47	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T24	11		T155	3		T44	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1173	1			T51	17		T210	17		T42	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T156	8		T43	5		T201	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	1		T39	7		T15	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T40	23		T175	4		T217	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T31	18		T50	19		T42	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T49	13		T149	9		T186	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T217	7		T248	13		T244	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T151	14		T255	14		T323	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	12		T9	2		T24	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T257	2		T162	3		T151	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T1	8		T156	8		T228	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T42	1		T149	9		T183	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T160	13		T217	18		T286	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T155	7		T163	9		T248	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T14	1		T24	15		T52	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T314	3		T342	2		T331	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T301	1		T332	11		T333	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T9	7		T299	7		T265	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T14	3		T44	1		T181	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T155	1		T43	12		T177	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T14	7		T286	18		T219	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T326	9		T340	5		T253	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T329	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	8		T32	12		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T14	9		T44	4		T47	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T24	1		T146	10		T239	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T49	11		T174	9		T175	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T1	2		T155	1		T157	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	17		T14	2		T53	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T147	5		T40	28		T154	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T5	6		T52	1		T174	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T25	1		T49	5		T161	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T26	11		T31	1		T50	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T49	12		T211	3		T192	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T1	17		T9	1		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T26	8		T43	1		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T1	1		T24	1		T237	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T148	1		T42	1		T257	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T160	9		T149	2		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T12	10		T25	1		T194	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1352	1			T2	3		T4	10		T11	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18287	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T155	7		T218	8		T303	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T14	1		T286	17		T301	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T326	6		T340	2		T253	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	7		T32	9		T146	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T14	3		T44	1		T47	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T24	11		T146	7		T44	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T49	10		T175	13		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T155	3		T43	5		T201	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	1		T39	7		T42	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T40	23		T156	8		T175	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	2		T42	1		T192	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T49	3		T149	9		T186	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T31	18		T50	19		T248	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T49	10		T192	3		T151	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	12		T9	2		T237	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T162	3		T151	13		T181	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T1	8		T24	18		T237	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T42	1		T257	2		T325	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T160	13		T217	18		T286	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T149	9		T163	9		T248	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1247	1			T24	15		T51	17		T52	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

auto[0]

4181

1

T1

20

T9

9

T14

5