Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27484

1

T1

40

T2

3

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23972

1

T1

29

T2

3

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3512

1

T1

11

T5

17

T14

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21605

1

T1

38

T3

18

T5

12

auto[1]

5879

1

T1

2

T2

3

T4

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23422

1

T1

23

T2

3

T3

18

auto[1]

4062

1

T1

17

T4

9

T5

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	259	1			T49	22		T148	1		T267	8
values[0]	32	1			T217	10		T343	2		T340	7
values[1]	579	1			T5	5		T24	16		T159	1
values[2]	606	1			T1	29		T12	10		T25	1
values[3]	764	1			T26	8		T50	20		T52	1
values[4]	1108	1			T1	2		T5	6		T9	18
values[5]	696	1			T31	19		T32	21		T49	8
values[6]	588	1			T1	9		T28	5		T147	5
values[7]	677	1			T24	31		T53	1		T146	17
values[8]	2925	1			T2	3		T4	10		T11	11
values[9]	963	1			T5	12		T14	3		T25	1
minimum	18287	1			T3	18		T6	20		T7	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	573	1			T5	5		T159	1		T52	16
values[1]	668	1			T1	29		T12	10		T25	1
values[2]	902	1			T5	6		T26	8		T50	20
values[3]	914	1			T1	2		T9	18		T147	1
values[4]	717	1			T31	19		T32	21		T49	8
values[5]	526	1			T1	9		T28	5		T147	5
values[6]	2895	1			T2	3		T4	10		T11	11
values[7]	679	1			T14	11		T147	10		T156	15
values[8]	980	1			T25	2		T26	11		T49	22
values[9]	122	1			T5	12		T157	1		T267	8
minimum	18508	1			T3	18		T6	20		T7	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

4181

1

T1

20

T9

9

T14

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T159	1		T155	4		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	1		T52	12		T174	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T1	13		T12	1		T25	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T49	11		T257	3		T177	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T5	1		T50	20		T211	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T26	1		T40	27		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T9	11		T147	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	1		T154	1		T239	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T31	19		T53	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T32	10		T49	4		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T28	1		T146	16		T177	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T1	9		T147	1		T194	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1572	1			T2	3		T4	1		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T237	16		T177	1		T192	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	3		T156	9		T163	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	4		T147	1		T186	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T25	1		T26	1		T49	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T25	1		T211	1		T43	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T157	1		T165	1		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T5	1		T267	1		T243	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18217	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T24	16		T237	3		T160	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T149	1		T193	12		T151	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	4		T52	4		T174	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	16		T12	9		T156	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T49	10		T257	4		T177	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	5		T211	2		T149	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T26	7		T40	24		T201	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T9	7		T161	5		T39	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	1		T154	10		T239	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T150	6		T201	22		T151	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T32	11		T49	4		T216	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T28	4		T146	16		T47	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T147	4		T158	13		T43	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T4	9		T11	10		T14	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T177	10		T192	11		T152	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T156	6		T163	18		T275	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	4		T147	9		T186	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T26	10		T49	11		T42	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T211	13		T43	13		T44	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T166	2		T281	9		T344	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T5	11		T267	7		T243	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	2		T27	1		T39	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T160	8		T245	1		T222	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T49	11		T148	1		T228	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T267	1		T271	1		T306	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T217	8		T343	1		T97	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T340	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T159	1		T160	11		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	1		T24	16		T52	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T1	13		T12	1		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T49	11		T174	1		T257	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T50	20		T52	1		T211	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T26	1		T44	1		T177	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	367	1			T5	1		T9	11		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	1		T40	27		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T31	19		T53	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T32	10		T49	4		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T28	1		T146	16		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T1	9		T147	1		T194	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T24	31		T53	1		T146	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T158	11		T175	14		T43	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1559	1			T2	3		T4	1		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	4		T25	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T14	3		T25	1		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T5	1		T211	1		T43	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18157	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T49	11		T228	13		T291	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T267	7		T271	11		T275	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T217	2		T343	1		T97	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T340	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T160	10		T149	1		T45	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T5	4		T52	4		T15	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	16		T12	9		T156	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T49	10		T174	10		T257	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T211	2		T149	2		T186	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T26	7		T177	1		T248	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T5	5		T9	7		T161	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	1		T40	24		T154	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T150	6		T291	3		T263	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T32	11		T49	4		T216	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T28	4		T146	16		T201	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T147	4		T192	5		T152	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T146	9		T278	5		T242	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T158	13		T43	1		T192	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T4	9		T11	10		T14	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	4		T147	9		T177	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T26	10		T42	1		T178	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	11		T211	13		T43	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	2		T27	1		T39	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T159	1		T155	1		T149	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	5		T52	5		T174	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	17		T12	10		T25	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T49	11		T257	5		T177	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	6		T50	1		T211	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T26	8		T40	28		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T9	9		T147	1		T161	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T1	2		T154	11		T239	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T31	1		T53	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T32	12		T49	5		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T28	5		T146	17		T177	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	1		T147	5		T194	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T2	3		T4	10		T11	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T237	1		T177	11		T192	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T14	2		T156	7		T163	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T14	7		T147	10		T186	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T25	1		T26	11		T49	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T25	1		T211	14		T43	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T157	1		T165	1		T166	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T5	12		T267	8		T243	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18362	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T24	1		T237	1		T160	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T155	3		T193	9		T151	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T52	11		T15	2		T149	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	12		T156	8		T175	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T49	10		T257	2		T270	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T50	19		T149	9		T186	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T40	23		T248	13		T47	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T9	9		T39	7		T155	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T242	9		T256	6		T266	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T31	18		T201	14		T151	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T32	9		T49	3		T258	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T146	15		T47	1		T228	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	8		T158	10		T175	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T14	3		T24	29		T51	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T237	15		T192	12		T248	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	1		T156	8		T163	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T14	1		T186	2		T266	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T49	10		T155	2		T42	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T43	4		T44	1		T162	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T281	11		T345	17		T332	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T243	4		T312	2		T346	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T160	10		T217	7		T347	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T24	15		T237	2		T160	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T49	12		T148	1		T228	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T267	8		T271	12		T306	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T217	3		T343	2		T97	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T340	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T159	1		T160	11		T149	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	5		T24	1		T52	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	17		T12	10		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T49	11		T174	11		T257	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T50	1		T52	1		T211	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T26	8		T44	1		T177	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	409	1			T5	6		T9	9		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T1	2		T40	28		T154	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T31	1		T53	1		T150	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T32	12		T49	5		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T28	5		T146	17		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	1		T147	5		T194	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T24	2		T53	1		T146	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T158	14		T175	1		T43	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T2	3		T4	10		T11	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	7		T25	1		T147	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T14	2		T25	1		T26	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T5	12		T211	14		T43	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18287	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T49	10		T291	11		T281	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T207	19		T183	13		T223	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T217	7		T97	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T340	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T160	10		T301	1		T347	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T24	15		T52	11		T237	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	12		T155	3		T156	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T49	10		T257	2		T186	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T50	19		T149	9		T186	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T248	13		T251	9		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T9	9		T39	7		T155	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T40	23		T47	1		T256	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T31	18		T261	5		T218	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T32	9		T49	3		T258	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T146	15		T201	14		T151	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	8		T192	3		T162	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T24	29		T146	7		T42	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T158	10		T175	13		T43	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T14	3		T51	17		T210	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	1		T237	15		T186	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T14	1		T155	2		T42	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T43	4		T44	1		T162	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

auto[0]

4181

1

T1

20

T9

9

T14

5