Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27484

1

T1

40

T2

3

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24140

1

T1

29

T2

3

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3344

1

T1

11

T5

11

T9

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21373

1

T1

2

T3

18

T5

12

auto[1]

6111

1

T1

38

T2

3

T4

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23422

1

T1

23

T2

3

T3

18

auto[1]

4062

1

T1

17

T4

9

T5

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	423	1			T12	10		T14	3		T24	12
values[0]	85	1			T283	15		T284	19		T198	15
values[1]	796	1			T1	29		T14	8		T25	1
values[2]	649	1			T5	11		T52	16		T174	9
values[3]	591	1			T1	2		T25	1		T26	11
values[4]	568	1			T5	12		T24	19		T26	8
values[5]	2804	1			T2	3		T4	10		T11	11
values[6]	690	1			T9	3		T14	12		T49	30
values[7]	807	1			T1	9		T25	1		T31	19
values[8]	866	1			T9	15		T24	16		T49	21
values[9]	918	1			T28	5		T147	5		T155	3
minimum	18287	1			T3	18		T6	20		T7	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	862	1			T1	29		T5	5		T25	1
values[1]	603	1			T5	6		T26	11		T52	16
values[2]	653	1			T1	2		T5	12		T25	1
values[3]	2642	1			T2	3		T4	10		T11	11
values[4]	607	1			T159	1		T50	20		T148	1
values[5]	655	1			T9	3		T14	12		T25	1
values[6]	926	1			T1	9		T31	19		T49	21
values[7]	824	1			T9	15		T24	16		T155	12
values[8]	985	1			T12	10		T24	12		T28	5
values[9]	192	1			T14	3		T211	14		T149	12
minimum	18535	1			T3	18		T6	20		T7	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

4181

1

T1

20

T9

9

T14

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T1	13		T43	1		T267	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	1		T25	1		T52	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T26	1		T52	12		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T5	1		T174	1		T43	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	1		T25	1		T32	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	1		T53	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1473	1			T2	3		T4	1		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T24	19		T173	1		T174	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T159	1		T192	4		T277	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T50	20		T148	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	6		T39	11		T160	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	3		T25	1		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T49	11		T40	27		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T1	9		T31	19		T42	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T24	16		T155	4		T15	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	8		T155	8		T237	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T12	1		T24	12		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T147	1		T53	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T14	3		T337	11		T236	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T211	1		T149	10		T151	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18244	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T157	1		T286	1		T240	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	16		T267	7		T302	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	4		T146	16		T161	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T26	10		T52	4		T154	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T5	5		T174	8		T43	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	11		T32	11		T47	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T1	1		T156	6		T239	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	902	1			T4	9		T11	10		T26	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T174	10		T257	4		T286	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T192	5		T277	9		T255	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T158	13		T45	1		T151	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T14	6		T39	10		T160	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T147	9		T49	15		T179	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T49	10		T40	24		T43	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T42	1		T152	8		T286	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T15	2		T42	2		T151	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T9	7		T156	8		T186	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	9		T28	4		T150	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T147	4		T154	12		T44	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T236	8		T285	10		T287	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T211	13		T149	2		T151	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	6		T27	1		T39	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T240	15		T323	11		T253	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	1		T14	3		T24	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T53	1		T151	14		T216	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T283	15		T284	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T198	15		T348	10		T288	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T1	13		T14	4		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T25	1		T52	1		T146	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T52	12		T44	1		T177	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	2		T174	1		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T25	1		T26	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	1		T42	2		T156	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	1		T26	1		T32	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T24	19		T53	1		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1515	1			T2	3		T4	1		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T148	1		T174	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	6		T39	11		T160	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	3		T49	15		T50	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T40	27		T258	11		T217	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	9		T25	1		T31	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T24	16		T49	11		T155	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	8		T155	8		T237	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T28	1		T155	3		T15	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T147	1		T237	3		T154	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18157	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T12	9		T150	6		T248	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T151	13		T216	4		T294	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T284	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T348	9		T288	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T1	16		T14	4		T278	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T146	16		T161	5		T211	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T52	4		T177	1		T267	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T5	9		T174	8		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T26	10		T154	10		T43	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T1	1		T156	6		T239	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	11		T26	7		T32	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T257	4		T43	4		T44	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	927	1			T4	9		T11	10		T215	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T174	10		T158	13		T45	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T14	6		T39	10		T160	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T49	15		T179	17		T166	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T40	24		T217	10		T179	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T147	9		T152	8		T286	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T49	10		T42	2		T43	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T9	7		T42	1		T156	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T28	4		T15	2		T186	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T147	4		T154	12		T211	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	2		T27	1		T39	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T1	17		T43	1		T267	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	5		T25	1		T52	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T26	11		T52	5		T154	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T5	6		T174	9		T43	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T5	12		T25	1		T32	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	2		T53	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T2	3		T4	10		T11	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T24	1		T173	1		T174	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T159	1		T192	6		T277	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T50	1		T148	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T14	9		T39	14		T160	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	1		T25	1		T147	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T49	11		T40	28		T43	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	1		T31	1		T42	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T24	1		T155	1		T15	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T9	8		T155	1		T237	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T12	10		T24	1		T28	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T147	5		T53	1		T154	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T14	2		T337	1		T236	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T211	14		T149	3		T151	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18365	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T157	1		T286	1		T240	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	12		T181	13		T38	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T146	15		T149	9		T201	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T52	11		T43	4		T191	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T43	1		T255	14		T338	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T32	9		T175	4		T47	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T42	1		T156	8		T175	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1143	1			T51	17		T146	7		T210	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T24	18		T257	2		T286	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T192	3		T277	13		T255	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T50	19		T158	10		T151	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T14	3		T39	7		T160	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	2		T49	13		T179	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T49	10		T40	23		T258	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T1	8		T31	18		T42	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T24	15		T155	3		T15	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T9	7		T155	7		T237	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T24	11		T155	2		T186	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T44	1		T186	6		T192	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T14	1		T337	10		T236	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T149	9		T151	13		T115	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T14	1		T236	3		T119	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T240	2		T323	16		T253	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T12	10		T14	2		T24	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T53	1		T151	14		T216	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T283	1		T284	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T198	1		T348	10		T288	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T1	17		T14	7		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T25	1		T52	1		T146	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T52	5		T44	1		T177	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T5	11		T174	9		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T25	1		T26	11		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T1	2		T42	1		T156	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	12		T26	8		T32	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T24	1		T53	1		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T2	3		T4	10		T11	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T148	1		T174	11		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T14	9		T39	14		T160	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	1		T49	17		T50	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T40	28		T258	1		T217	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	1		T25	1		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T24	1		T49	11		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	8		T155	1		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T28	5		T155	1		T15	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T147	5		T237	1		T154	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18287	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T14	1		T24	11		T248	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T151	13		T294	10		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T283	14		T284	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T198	14		T348	9		T288	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	12		T14	1		T181	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T146	15		T149	9		T163	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T52	11		T191	3		T217	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T43	1		T201	14		T255	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T43	4		T243	4		T291	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T42	1		T156	8		T175	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T32	9		T146	7		T175	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T24	18		T257	2		T43	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1186	1			T51	17		T210	17		T214	32
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T158	10		T151	14		T244	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T14	3		T39	7		T160	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T9	2		T49	13		T50	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T40	23		T258	10		T217	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	8		T31	18		T162	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T24	15		T49	10		T155	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	7		T155	7		T237	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T155	2		T15	2		T186	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T237	2		T149	9		T44	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

auto[0]

4181

1

T1

20

T9

9

T14

5