Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27484

1

T1

40

T2

3

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23809

1

T2

3

T3

18

T4

10

auto[ADC_CTRL_FILTER_COND_OUT]

3675

1

T1

40

T12

10

T14

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21348

1

T1

9

T3

18

T5

23

auto[1]

6136

1

T1

31

T2

3

T4

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23422

1

T1

23

T2

3

T3

18

auto[1]

4062

1

T1

17

T4

9

T5

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	290	1			T159	1		T148	1		T156	32
values[0]	70	1			T52	16		T192	24		T305	4
values[1]	877	1			T14	8		T39	21		T174	11
values[2]	2818	1			T2	3		T4	10		T9	3
values[3]	660	1			T148	1		T40	51		T155	3
values[4]	692	1			T9	15		T14	12		T25	1
values[5]	769	1			T25	1		T26	11		T53	1
values[6]	713	1			T1	9		T5	6		T26	8
values[7]	679	1			T5	12		T24	19		T25	1
values[8]	654	1			T1	29		T5	5		T12	10
values[9]	975	1			T1	2		T14	3		T24	16
minimum	18287	1			T3	18		T6	20		T7	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	771	1			T14	8		T147	5		T52	16
values[1]	2844	1			T2	3		T4	10		T9	3
values[2]	638	1			T14	12		T148	1		T40	51
values[3]	744	1			T9	15		T25	1		T26	11
values[4]	857	1			T25	1		T53	1		T52	1
values[5]	670	1			T1	9		T5	18		T25	1
values[6]	531	1			T5	5		T24	19		T49	29
values[7]	690	1			T1	29		T12	10		T24	12
values[8]	893	1			T1	2		T14	3		T31	19
values[9]	252	1			T24	16		T157	1		T277	23
minimum	18594	1			T3	18		T6	20		T7	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

4181

1

T1

20

T9

9

T14

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T147	1		T52	12		T155	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T14	4		T39	11		T155	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1548	1			T2	3		T4	1		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T50	20		T211	1		T149	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T14	6		T155	3		T237	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T148	1		T40	27		T258	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T9	8		T25	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T26	1		T161	1		T42	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T52	1		T239	1		T186	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T25	1		T53	1		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	2		T25	1		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	9		T194	1		T248	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	1		T49	15		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T24	19		T177	1		T192	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T28	1		T147	1		T49	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	13		T12	1		T24	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T14	3		T31	19		T32	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	1		T159	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T24	16		T157	1		T277	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T299	8		T349	14		T300	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18225	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T175	14		T192	13		T243	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T147	4		T52	4		T15	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	4		T39	10		T154	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	905	1			T4	9		T11	10		T215	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T211	13		T149	2		T44	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T14	6		T154	10		T150	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T40	24		T193	12		T151	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	7		T147	9		T146	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T26	10		T161	5		T268	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T239	10		T186	2		T217	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T174	8		T43	11		T44	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	16		T26	7		T301	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T248	30		T302	13		T228	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	4		T49	14		T42	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T177	10		T192	18		T267	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T28	4		T49	11		T146	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T1	16		T12	9		T42	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T32	11		T211	2		T151	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	1		T156	14		T160	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T277	9		T303	16		T304	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T299	7		T349	13		T273	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	2		T27	1		T39	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T192	11		T243	5		T236	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T157	1		T43	1		T165	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T159	1		T148	1		T156	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T52	12		T97	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T192	13		T305	1		T350	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T174	1		T155	8		T162	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T14	4		T39	11		T155	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1541	1			T2	3		T4	1		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T50	20		T154	1		T211	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T155	3		T237	3		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T148	1		T40	27		T44	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T9	8		T14	6		T25	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T161	1		T42	2		T258	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T52	1		T239	1		T217	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T25	1		T26	1		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	1		T26	1		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	9		T248	24		T47	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	1		T25	1		T49	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T24	19		T194	1		T177	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	1		T49	11		T146	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	13		T12	1		T24	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T14	3		T24	16		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T1	1		T237	16		T160	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18157	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T275	9		T303	16		T351	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T156	14		T242	13		T273	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T52	4		T97	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T192	11		T305	3		T350	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T174	10		T152	12		T168	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	4		T39	10		T160	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	890	1			T4	9		T11	10		T147	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T154	12		T211	13		T149	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T154	10		T150	6		T186	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T40	24		T44	1		T193	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	7		T14	6		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T161	5		T268	2		T275	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T239	10		T217	2		T303	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T26	10		T174	8		T43	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	5		T26	7		T186	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T248	30		T47	9		T270	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	11		T49	14		T42	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T177	10		T192	18		T267	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	4		T49	11		T146	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T1	16		T12	9		T42	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T28	4		T32	11		T211	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	1		T160	10		T149	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	2		T27	1		T39	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T147	5		T52	5		T155	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T14	7		T39	14		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T2	3		T4	10		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T50	1		T211	14		T149	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T14	9		T155	1		T237	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T148	1		T40	28		T258	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T9	8		T25	1		T147	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T26	11		T161	6		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T52	1		T239	11		T186	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T25	1		T53	1		T174	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	18		T25	1		T26	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	1		T194	1		T248	32
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	5		T49	16		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T24	1		T177	11		T192	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T28	5		T147	1		T49	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	17		T12	10		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T14	2		T31	1		T32	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	2		T159	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T24	1		T157	1		T277	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T299	8		T349	14		T300	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18354	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T175	1		T192	12		T243	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T52	11		T155	7		T15	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T14	1		T39	7		T155	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T9	2		T51	17		T210	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T50	19		T149	9		T44	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T14	3		T155	2		T237	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T40	23		T258	10		T193	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T9	7		T146	7		T257	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T42	1		T163	9		T218	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T186	6		T191	3		T217	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T44	1		T217	18		T47	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T164	13		T218	3		T301	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	8		T248	22		T279	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T49	13		T42	2		T43	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T24	18		T192	13		T244	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T49	10		T146	15		T270	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	12		T24	11		T42	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T14	1		T31	18		T32	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T237	15		T156	16		T160	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T24	15		T277	13		T303	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T299	7		T349	13		T300	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T162	12		T168	2		T254	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T175	13		T192	12		T243	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T157	1		T43	1		T165	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T159	1		T148	1		T156	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T52	5		T97	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T192	12		T305	4		T350	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T174	11		T155	1		T162	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T14	7		T39	14		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1221	1			T2	3		T4	10		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T50	1		T154	13		T211	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T155	1		T237	1		T154	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T148	1		T40	28		T44	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	8		T14	9		T25	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T161	6		T42	1		T258	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T52	1		T239	11		T217	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T25	1		T26	11		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	6		T26	8		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	1		T248	32		T47	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	12		T25	1		T49	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T24	1		T194	1		T177	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	5		T49	12		T146	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T1	17		T12	10		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T14	2		T24	1		T28	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	2		T237	1		T160	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18287	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T303	11		T345	17		T351	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T156	16		T254	4		T352	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T52	11		T97	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T192	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T155	7		T162	20		T168	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T14	1		T39	7		T155	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T9	2		T51	17		T15	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T50	19		T149	9		T201	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T155	2		T237	2		T175	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T40	23		T44	1		T193	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T9	7		T14	3		T146	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T42	1		T258	10		T207	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T217	7		T256	2		T303	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T44	1		T163	9		T217	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T186	6		T191	3		T286	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	8		T248	22		T47	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T49	13		T42	2		T179	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T24	18		T192	13		T244	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T49	10		T146	15		T43	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	12		T24	11		T42	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T14	1		T24	15		T31	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T237	15		T160	10		T158	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

auto[0]

4181

1

T1

20

T9

9

T14

5