Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T32	12		T148	1		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T9	8		T53	1		T15	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	1		T5	5		T12	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T28	5		T257	5		T239	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	6		T24	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T146	10		T174	9		T42	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1223	1			T2	3		T4	10		T11	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T159	1		T42	3		T158	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T14	9		T147	5		T39	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	12		T14	7		T174	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T26	11		T40	28		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T1	17		T9	1		T14	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T24	1		T191	1		T46	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	2		T49	11		T50	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T26	8		T52	1		T146	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T31	1		T49	12		T152	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T25	1		T53	1		T154	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T24	1		T147	10		T161	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T25	1		T86	2		T266	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T149	2		T186	3		T162	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18293	1			T3	18		T6	20		T7	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T32	9		T162	3		T151	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T9	7		T15	2		T160	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	8		T49	3		T175	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T257	2		T201	6		T151	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T24	18		T155	7		T42	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T146	7		T42	1		T149	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1138	1			T51	17		T155	2		T210	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T42	2		T158	10		T44	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T14	3		T39	7		T192	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	1		T255	14		T168	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T40	23		T155	3		T237	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	12		T9	2		T14	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T24	15		T191	3		T46	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T49	10		T50	19		T52	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T146	15		T186	2		T256	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T31	18		T49	10		T207	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T156	16		T175	13		T43	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T24	11		T237	15		T160	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T266	3		T273	14		T274	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T186	6		T162	12		T222	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T263	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T53	1		T262	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T263	6		T265	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T264	1		T269	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T32	12		T162	1		T47	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	8		T53	1		T15	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T5	5		T12	10		T49	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T28	5		T257	5		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	1		T194	1		T44	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T174	9		T42	2		T149	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	6		T24	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T159	1		T146	10		T42	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T2	3		T4	10		T11	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	7		T157	1		T35	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T14	9		T147	5		T40	28
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T1	17		T5	12		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T24	1		T26	11		T43	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	2		T9	1		T14	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T146	17		T173	1		T186	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T31	1		T49	12		T50	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T25	2		T26	8		T52	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T24	1		T147	10		T161	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18287	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T262	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T263	2		T265	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T32	9		T162	3		T47	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	7		T15	2		T160	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T49	3		T155	7		T175	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T257	2		T201	6		T151	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	8		T44	1		T151	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T42	1		T149	9		T248	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T24	18		T42	1		T179	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T146	7		T42	2		T158	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1164	1			T51	17		T39	7		T155	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T14	1		T255	14		T241	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T14	3		T40	23		T155	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	12		T52	11		T261	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T24	15		T43	4		T192	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T9	2		T14	1		T49	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T146	15		T186	2		T256	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T31	18		T49	10		T50	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T156	16		T175	13		T43	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T24	11		T237	15		T160	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

auto[0]

4181

1

T1

20

T9

9

T14

5