Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27484

1

T1

40

T2

3

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23947

1

T1

29

T2

3

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3537

1

T1

11

T5

17

T14

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21604

1

T1

38

T3

18

T5

12

auto[1]

5880

1

T1

2

T2

3

T4

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23422

1

T1

23

T2

3

T3

18

auto[1]

4062

1

T1

17

T4

9

T5

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T271	12		T274	1		-	-
values[0]	23	1			T217	10		T97	13		-	-
values[1]	628	1			T5	5		T24	16		T159	1
values[2]	617	1			T1	29		T12	10		T25	1
values[3]	724	1			T9	15		T26	8		T52	1
values[4]	1036	1			T1	2		T5	6		T9	3
values[5]	784	1			T31	19		T32	21		T49	8
values[6]	537	1			T1	9		T28	5		T147	5
values[7]	702	1			T24	31		T53	1		T146	17
values[8]	2891	1			T2	3		T4	10		T11	11
values[9]	1242	1			T5	12		T14	3		T25	1
minimum	18287	1			T3	18		T6	20		T7	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	754	1			T24	16		T159	1		T52	16
values[1]	709	1			T1	29		T5	5		T12	10
values[2]	932	1			T5	6		T9	15		T26	8
values[3]	823	1			T1	2		T9	3		T147	1
values[4]	725	1			T31	19		T32	21		T147	5
values[5]	635	1			T1	9		T28	5		T146	32
values[6]	2841	1			T2	3		T4	10		T11	11
values[7]	623	1			T14	11		T147	10		T156	15
values[8]	925	1			T25	2		T26	11		T49	22
values[9]	223	1			T5	12		T157	1		T43	18
minimum	18294	1			T3	18		T6	20		T7	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

4181

1

T1

20

T9

9

T14

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T155	4		T160	25		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T24	16		T159	1		T52	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	13		T12	1		T25	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T5	1		T49	11		T257	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T5	1		T9	8		T50	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T26	1		T40	27		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T9	3		T147	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	1		T154	1		T239	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T31	19		T53	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T32	10		T147	1		T49	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T28	1		T146	16		T194	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T1	9		T158	11		T175	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T2	3		T4	1		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T237	16		T177	1		T192	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	3		T156	9		T163	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	4		T147	1		T166	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T25	1		T26	1		T49	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T25	1		T211	1		T44	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T157	1		T228	1		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T5	1		T43	5		T201	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18158	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T245	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T160	18		T149	1		T193	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T52	4		T174	10		T15	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T1	16		T12	9		T156	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	4		T49	10		T257	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	5		T9	7		T211	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T26	7		T40	24		T201	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T161	5		T39	10		T42	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T1	1		T154	10		T239	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T174	8		T150	6		T201	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T32	11		T147	4		T49	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T28	4		T146	16		T46	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T158	13		T43	1		T192	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	919	1			T4	9		T11	10		T14	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T177	10		T192	11		T152	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T156	6		T163	18		T275	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	4		T147	9		T166	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T26	10		T49	11		T42	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T211	13		T44	1		T186	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T228	13		T166	2		T276	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T5	11		T43	13		T179	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T14	2		T27	1		T39	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T245	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T274	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T271	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T217	8		T97	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T156	9		T160	25		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	1		T24	16		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	13		T12	1		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T49	11		T174	1		T257	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T9	8		T52	1		T211	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T26	1		T44	1		T248	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T5	1		T9	3		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	1		T40	27		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T31	19		T53	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T32	10		T49	4		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T28	1		T146	16		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	9		T147	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T24	31		T53	1		T146	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T158	11		T175	14		T43	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1527	1			T2	3		T4	1		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T14	4		T25	1		T237	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T14	3		T25	1		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T5	1		T147	1		T211	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18157	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T271	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T217	2		T97	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T156	8		T160	18		T193	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T5	4		T52	4		T15	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T1	16		T12	9		T149	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T49	10		T174	10		T257	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T9	7		T211	2		T149	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T26	7		T248	15		T48	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T5	5		T161	5		T39	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	1		T40	24		T154	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T150	6		T43	4		T217	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T32	11		T49	4		T216	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T28	4		T146	16		T201	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T147	4		T192	5		T277	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T146	9		T278	5		T242	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T158	13		T43	1		T192	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T4	9		T11	10		T14	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	4		T177	10		T186	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T26	10		T49	11		T42	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T5	11		T147	9		T211	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	2		T27	1		T39	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T155	1		T160	20		T149	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T24	1		T159	1		T52	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	17		T12	10		T25	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	5		T49	11		T257	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T5	6		T9	8		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T26	8		T40	28		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T9	1		T147	1		T161	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T1	2		T154	11		T239	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T31	1		T53	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T32	12		T147	5		T49	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T28	5		T146	17		T194	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T1	1		T158	14		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T2	3		T4	10		T11	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T237	1		T177	11		T192	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T14	2		T156	7		T163	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	7		T147	10		T166	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T25	1		T26	11		T49	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T25	1		T211	14		T44	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T157	1		T228	14		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T5	12		T43	14		T201	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18292	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T245	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T155	3		T160	23		T193	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T24	15		T52	11		T237	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T1	12		T156	8		T149	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T49	10		T257	2		T270	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T9	7		T50	19		T175	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T40	23		T248	13		T47	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T9	2		T39	7		T155	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T256	6		T266	10		T279	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T31	18		T201	14		T151	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T32	9		T49	3		T258	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T146	15		T46	4		T47	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	8		T158	10		T175	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1198	1			T14	3		T24	29		T51	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T237	15		T192	12		T179	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T14	1		T156	8		T163	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T14	1		T266	3		T254	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T49	10		T155	2		T42	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T44	1		T186	2		T162	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T235	9		T280	3		T281	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T43	4		T201	6		T179	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T274	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T271	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T217	3		T97	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T156	9		T160	20		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	5		T24	1		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T1	17		T12	10		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T49	11		T174	11		T257	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T9	8		T52	1		T211	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T26	8		T44	1		T248	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	384	1			T5	6		T9	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T1	2		T40	28		T154	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T31	1		T53	1		T150	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T32	12		T49	5		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T28	5		T146	17		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T1	1		T147	5		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T24	2		T53	1		T146	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T158	14		T175	1		T43	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T2	3		T4	10		T11	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T14	7		T25	1		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T14	2		T25	1		T26	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T5	12		T147	10		T211	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18287	1			T3	18		T6	20		T7	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T217	7		T97	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T156	8		T160	23		T193	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T24	15		T52	11		T237	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	12		T50	19		T155	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T49	10		T257	2		T186	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	7		T149	9		T186	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T248	13		T251	9		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T9	2		T39	7		T155	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T40	23		T47	1		T256	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T31	18		T43	5		T261	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T32	9		T49	3		T258	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T146	15		T201	14		T151	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T1	8		T192	3		T162	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T24	29		T146	7		T42	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T158	10		T175	13		T43	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1197	1			T14	3		T51	17		T210	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	1		T237	15		T186	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T14	1		T49	10		T155	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T43	4		T44	1		T162	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

auto[0]

4181

1

T1

20

T9

9

T14

5