Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27484

1

T1

40

T2

3

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23910

1

T1

11

T2

3

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3574

1

T1

29

T5

12

T9

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21629

1

T1

40

T3

18

T5

6

auto[1]

5855

1

T2

3

T4

10

T5

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23422

1

T1

23

T2

3

T3

18

auto[1]

4062

1

T1

17

T4

9

T5

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	9	1			T218	9		-	-		-	-
values[0]	88	1			T43	10		T186	9		T48	3
values[1]	549	1			T1	9		T31	19		T155	11
values[2]	856	1			T24	12		T25	1		T53	1
values[3]	529	1			T14	8		T26	8		T39	21
values[4]	792	1			T5	6		T147	1		T155	4
values[5]	803	1			T26	11		T147	10		T257	7
values[6]	702	1			T5	5		T49	29		T40	51
values[7]	731	1			T14	3		T52	1		T174	11
values[8]	779	1			T1	31		T5	12		T9	18
values[9]	3359	1			T2	3		T4	10		T11	11
minimum	18287	1			T3	18		T6	20		T7	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	865	1			T1	9		T31	19		T173	1
values[1]	799	1			T14	8		T24	12		T25	1
values[2]	604	1			T5	6		T26	8		T39	21
values[3]	803	1			T26	11		T147	11		T156	15
values[4]	740	1			T40	51		T44	3		T162	9
values[5]	743	1			T5	5		T49	29		T157	1
values[6]	2873	1			T2	3		T4	10		T5	12
values[7]	676	1			T1	31		T9	15		T14	3
values[8]	849	1			T9	3		T24	35		T25	1
values[9]	226	1			T12	10		T14	12		T25	1
minimum	18306	1			T3	18		T6	20		T7	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

4181

1

T1

20

T9

9

T14

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T1	9		T174	1		T155	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T31	19		T173	1		T15	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T24	12		T25	1		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T14	4		T53	1		T50	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T5	1		T155	4		T237	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T26	1		T39	11		T177	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T147	1		T257	3		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T26	1		T147	1		T156	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T40	27		T44	2		T162	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T151	14		T216	1		T242	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	1		T239	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T49	15		T157	1		T193	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1548	1			T2	3		T4	1		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	1		T147	1		T52	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	1		T14	3		T32	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	13		T9	8		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T9	3		T24	19		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T24	16		T28	1		T52	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T46	9		T218	9		T290	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T12	1		T14	6		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18158	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T291	3		T251	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T174	8		T211	2		T43	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T15	2		T43	4		T244	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T154	12		T201	22		T243	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	4		T146	25		T160	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	5		T149	2		T150	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T26	7		T39	10		T177	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T147	9		T257	4		T268	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T26	10		T156	6		T192	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T40	24		T44	1		T201	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T151	13		T216	13		T242	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	4		T239	10		T43	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T49	14		T193	12		T275	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T4	9		T11	10		T215	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	11		T147	4		T42	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	1		T32	11		T211	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	16		T9	7		T49	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T149	1		T192	5		T216	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T28	4		T52	4		T154	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T46	5		T184	13		T23	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T12	9		T14	6		T151	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	2		T27	1		T39	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T291	3		T251	2		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T218	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T186	7		T111	10		T292	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T43	6		T48	2		T293	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T1	9		T155	3		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T31	19		T155	8		T15	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T24	12		T25	1		T174	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T53	1		T50	20		T146	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T237	3		T175	5		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	4		T26	1		T39	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	1		T155	4		T149	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T147	1		T156	9		T175	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T147	1		T257	3		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T26	1		T192	11		T162	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T5	1		T40	27		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T49	15		T42	3		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T14	3		T174	1		T42	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T52	1		T237	16		T186	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	1		T9	3		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	13		T5	1		T9	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1708	1			T2	3		T4	1		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T12	1		T14	6		T24	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18157	1			T3	18		T6	20		T7	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T186	2		T111	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T43	4		T48	1		T293	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T43	11		T152	8		T271	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T15	2		T244	17		T291	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T174	8		T154	12		T211	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T146	25		T160	8		T267	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T152	4		T243	5		T38	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T14	4		T26	7		T39	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	5		T149	2		T150	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T156	6		T177	1		T45	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T147	9		T257	4		T248	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T26	10		T192	13		T151	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	4		T40	24		T239	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T49	14		T42	2		T193	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T174	10		T42	1		T43	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T186	7		T47	9		T255	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	1		T161	5		T158	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	16		T5	11		T9	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1061	1			T4	9		T11	10		T32	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T12	9		T14	6		T28	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	2		T27	1		T39	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T1	1		T174	9		T155	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T31	1		T173	1		T15	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T24	1		T25	1		T154	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T14	7		T53	1		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	6		T155	1		T237	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T26	8		T39	14		T177	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T147	10		T257	5		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T26	11		T147	1		T156	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T40	28		T44	2		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T151	14		T216	14		T242	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T5	5		T239	11		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T49	16		T157	1		T193	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T2	3		T4	10		T11	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	12		T147	5		T52	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	2		T14	2		T32	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	17		T9	8		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T9	1		T24	1		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T24	1		T28	5		T52	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T46	10		T218	1		T290	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T12	10		T14	9		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18288	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T291	4		T251	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	8		T155	2		T186	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T31	18		T15	2		T43	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T24	11		T201	14		T243	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T14	1		T50	19		T146	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T155	3		T237	2		T149	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T39	7		T261	5		T47	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T257	2		T217	7		T255	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T156	8		T175	13		T192	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T40	23		T44	1		T162	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T151	13		T242	9		T294	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T43	1		T44	1		T258	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T49	13		T193	9		T207	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1201	1			T51	17		T210	17		T42	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T237	15		T42	2		T149	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T14	1		T32	9		T158	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	12		T9	7		T49	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T9	2		T24	18		T42	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T24	15		T52	11		T160	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T46	4		T218	8		T23	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T14	3		T151	13		T279	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T291	2		T251	9		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T218	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T186	3		T111	9		T292	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T43	5		T48	3		T293	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	1		T155	1		T43	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T31	1		T155	1		T15	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T24	1		T25	1		T174	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T53	1		T50	1		T146	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T237	1		T175	1		T152	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	7		T26	8		T39	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T5	6		T155	1		T149	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T147	1		T156	7		T175	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T147	10		T257	5		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T26	11		T192	14		T162	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	5		T40	28		T239	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T49	16		T42	3		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T14	2		T174	11		T42	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T52	1		T237	1		T186	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	2		T9	1		T161	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	17		T5	12		T9	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1449	1			T2	3		T4	10		T11	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T12	10		T14	9		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18287	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T218	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T186	6		T111	9		T292	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T43	5		T295	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T1	8		T155	2		T256	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T31	18		T155	7		T15	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T24	11		T192	12		T201	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T50	19		T146	22		T160	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T237	2		T175	4		T181	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T14	1		T39	7		T47	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T155	3		T149	9		T186	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T156	8		T175	13		T201	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T257	2		T162	8		T248	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T192	10		T162	3		T151	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T40	23		T44	2		T258	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T49	13		T42	2		T193	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T14	1		T42	1		T43	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T237	15		T186	2		T47	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T9	2		T158	10		T179	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	12		T9	7		T49	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1320	1			T24	18		T32	9		T51	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T14	3		T24	15		T52	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

auto[0]

4181

1

T1

20

T9

9

T14

5