Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27484

1

T1

40

T2

3

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23788

1

T2

3

T3

18

T4

10

auto[ADC_CTRL_FILTER_COND_OUT]

3696

1

T1

40

T12

10

T14

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21290

1

T1

9

T3

18

T5

23

auto[1]

6194

1

T1

31

T2

3

T4

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23422

1

T1

23

T2

3

T3

18

auto[1]

4062

1

T1

17

T4

9

T5

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	39	1			T296	18		T297	1		T298	20
values[0]	75	1			T52	16		T192	24		T152	5
values[1]	893	1			T14	8		T147	5		T39	21
values[2]	2838	1			T2	3		T4	10		T9	3
values[3]	684	1			T9	15		T14	12		T40	51
values[4]	603	1			T25	1		T147	10		T146	17
values[5]	765	1			T25	1		T26	11		T53	1
values[6]	786	1			T1	9		T5	6		T25	1
values[7]	649	1			T5	12		T24	19		T26	8
values[8]	680	1			T1	29		T5	5		T12	10
values[9]	1185	1			T1	2		T14	3		T24	16
minimum	18287	1			T3	18		T6	20		T7	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1061	1			T14	8		T147	5		T52	16
values[1]	2849	1			T2	3		T4	10		T9	3
values[2]	622	1			T147	10		T148	1		T40	51
values[3]	749	1			T9	15		T14	12		T25	1
values[4]	885	1			T1	9		T25	1		T52	1
values[5]	602	1			T5	18		T25	1		T26	8
values[6]	603	1			T5	5		T24	19		T49	21
values[7]	728	1			T1	29		T12	10		T24	12
values[8]	842	1			T1	2		T14	3		T32	21
values[9]	254	1			T24	16		T31	19		T157	1
minimum	18289	1			T3	18		T6	20		T7	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

4181

1

T1

20

T9

9

T14

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T147	1		T52	12		T174	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T14	4		T39	11		T155	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1553	1			T2	3		T4	1		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T50	20		T211	1		T149	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T147	1		T155	3		T237	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T148	1		T40	27		T258	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T9	8		T14	6		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T26	1		T161	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T52	1		T186	7		T286	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T1	9		T25	1		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	2		T25	1		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T53	1		T194	1		T248	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	1		T49	11		T146	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T24	19		T177	1		T192	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T28	1		T49	15		T211	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	13		T12	1		T24	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T14	3		T32	10		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	1		T159	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T24	16		T31	19		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T242	1		T299	8		T300	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18158	1			T3	18		T6	20		T7	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T147	4		T52	4		T174	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T14	4		T39	10		T154	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	906	1			T4	9		T11	10		T215	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T211	13		T149	2		T44	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T147	9		T154	10		T150	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T40	24		T193	12		T151	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	7		T14	6		T146	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T26	10		T161	5		T268	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T186	2		T286	11		T240	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T174	8		T239	10		T43	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	16		T26	7		T301	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T248	15		T302	13		T228	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	4		T49	10		T146	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T177	10		T192	18		T267	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T28	4		T49	15		T211	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	16		T12	9		T42	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T32	11		T151	16		T216	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T1	1		T156	14		T160	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T277	9		T303	16		T304	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T242	13		T299	7		T273	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T14	2		T27	1		T39	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T296	18		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T297	1		T298	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T52	12		T152	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T192	13		T243	5		T22	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T147	1		T174	1		T155	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T14	4		T39	11		T155	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1530	1			T2	3		T4	1		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T50	20		T148	1		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T9	8		T14	6		T155	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T40	27		T44	4		T258	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T25	1		T147	1		T146	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T161	1		T42	2		T268	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T52	1		T35	1		T286	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T25	1		T26	1		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	1		T25	1		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	9		T194	1		T248	24
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	1		T26	1		T49	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T24	19		T177	1		T192	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	1		T49	11		T146	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	13		T12	1		T24	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	400	1			T14	3		T24	16		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T1	1		T159	1		T148	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18157	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T298	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T52	4		T152	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T192	11		T243	5		T22	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T147	4		T174	10		T151	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T14	4		T39	10		T149	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	875	1			T4	9		T11	10		T215	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T154	12		T211	13		T160	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	7		T14	6		T154	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T40	24		T44	1		T193	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T147	9		T146	9		T257	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T161	5		T268	2		T286	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T35	14		T286	11		T303	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T26	10		T174	8		T239	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	5		T186	2		T242	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T248	30		T47	9		T275	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	11		T26	7		T49	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T177	10		T192	18		T267	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	4		T49	11		T146	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T1	16		T12	9		T42	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T28	4		T32	11		T211	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	1		T156	14		T160	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	2		T27	1		T39	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T147	5		T52	5		T174	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T14	7		T39	14		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T2	3		T4	10		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T50	1		T211	14		T149	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T147	10		T155	1		T237	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T148	1		T40	28		T258	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T9	8		T14	9		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T26	11		T161	6		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T52	1		T186	3		T286	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T1	1		T25	1		T174	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	18		T25	1		T26	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T53	1		T194	1		T248	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	5		T49	11		T146	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T24	1		T177	11		T192	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T28	5		T49	17		T211	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	17		T12	10		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T14	2		T32	12		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T1	2		T159	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T24	1		T31	1		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T242	14		T299	8		T300	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18289	1			T3	18		T6	20		T7	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T52	11		T155	7		T15	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T14	1		T39	7		T155	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1222	1			T9	2		T51	17		T210	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T50	19		T149	9		T44	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T155	2		T237	2		T175	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T40	23		T258	10		T193	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	7		T14	3		T146	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T163	9		T218	8		T220	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T186	6		T286	14		T240	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	8		T42	1		T44	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T191	3		T164	13		T218	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T248	13		T279	11		T241	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T49	10		T146	15		T42	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T24	18		T192	13		T244	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T49	13		T43	4		T291	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	12		T24	11		T42	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T14	1		T32	9		T151	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T237	15		T156	16		T160	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T24	15		T31	18		T277	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T299	7		T300	8		T273	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T296	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T297	1		T298	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T52	5		T152	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T192	12		T243	6		T22	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T147	5		T174	11		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T14	7		T39	14		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T2	3		T4	10		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T50	1		T148	1		T154	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T9	8		T14	9		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T40	28		T44	4		T258	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T25	1		T147	10		T146	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T161	6		T42	1		T268	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T52	1		T35	15		T286	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T25	1		T26	11		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	6		T25	1		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	1		T194	1		T248	32
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	12		T26	8		T49	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T24	1		T177	11		T192	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	5		T49	12		T146	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	17		T12	10		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T14	2		T24	1		T28	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T1	2		T159	1		T148	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18287	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T296	17		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T298	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T52	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T192	12		T243	4		T22	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T155	7		T162	20		T151	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	1		T39	7		T155	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1201	1			T9	2		T51	17		T15	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T50	19		T160	13		T149	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T9	7		T14	3		T155	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T40	23		T44	1		T258	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T146	7		T257	2		T43	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T42	1		T286	17		T207	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T286	14		T256	2		T303	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T44	1		T163	9		T217	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T186	6		T191	3		T242	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	8		T248	22		T47	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T49	13		T42	2		T179	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T24	18		T192	13		T244	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T49	10		T146	15		T43	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	12		T24	11		T42	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T14	1		T24	15		T31	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T237	15		T156	16		T160	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

auto[0]

4181

1

T1

20

T9

9

T14

5