Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27484

1

T1

40

T2

3

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23902

1

T1

2

T2

3

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3582

1

T1

38

T5

23

T9

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21123

1

T1

29

T3

18

T5

6

auto[1]

6361

1

T1

11

T2

3

T4

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23422

1

T1

23

T2

3

T3

18

auto[1]

4062

1

T1

17

T4

9

T5

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	467	1			T8	9		T41	6		T27	2
values[0]	78	1			T302	14		T305	11		T253	20
values[1]	713	1			T12	10		T25	1		T26	8
values[2]	2833	1			T2	3		T4	10		T9	3
values[3]	536	1			T1	2		T5	6		T25	1
values[4]	759	1			T14	12		T24	16		T147	5
values[5]	609	1			T1	9		T5	12		T147	10
values[6]	691	1			T5	5		T28	5		T49	29
values[7]	910	1			T1	29		T24	19		T147	1
values[8]	814	1			T9	15		T24	12		T31	19
values[9]	1248	1			T14	11		T53	1		T50	20
minimum	17826	1			T3	18		T6	20		T7	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	881	1			T9	3		T12	10		T25	1
values[1]	2762	1			T2	3		T4	10		T11	11
values[2]	690	1			T1	2		T5	6		T25	1
values[3]	621	1			T14	12		T24	16		T39	21
values[4]	713	1			T1	9		T5	17		T147	10
values[5]	648	1			T28	5		T49	21		T237	3
values[6]	1012	1			T1	29		T24	19		T32	21
values[7]	648	1			T9	15		T24	12		T31	19
values[8]	946	1			T14	11		T53	1		T211	3
values[9]	219	1			T50	20		T268	3		T37	7
minimum	18344	1			T3	18		T6	20		T7	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

4181

1

T1

20

T9

9

T14

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T26	1		T52	12		T174	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	3		T12	1		T25	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1524	1			T2	3		T4	1		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T237	16		T186	15		T192	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	1		T25	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	1		T40	27		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T42	2		T157	1		T177	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	6		T24	16		T39	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T147	1		T53	1		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	9		T5	2		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T28	1		T43	4		T46	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T49	11		T237	3		T156	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T24	19		T49	4		T52	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T1	13		T32	10		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T146	8		T148	1		T194	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	8		T24	12		T31	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T14	7		T150	1		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T53	1		T211	1		T149	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T268	1		T306	2		T242	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T50	20		T37	3		T307	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18176	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T302	1		T181	14		T308	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T26	7		T52	4		T174	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	9		T160	10		T158	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	916	1			T4	9		T11	10		T26	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T186	13		T192	13		T267	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	1		T147	4		T49	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T5	5		T40	24		T154	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T166	2		T243	5		T168	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T14	6		T39	10		T257	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T147	9		T161	5		T192	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	15		T174	8		T156	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	4		T43	1		T46	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T49	10		T156	6		T160	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T49	4		T42	2		T43	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T1	16		T32	11		T177	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T146	9		T216	13		T270	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T9	7		T42	1		T193	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T14	4		T43	11		T186	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T211	2		T149	11		T177	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T268	2		T242	13		T309	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T37	4		T307	14		T310	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T14	2		T27	1		T39	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T302	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	467	1			T8	9		T41	6		T27	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T253	11		T209	1		T311	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T302	1		T305	1		T312	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T26	1		T174	1		T15	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	1		T25	1		T155	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1554	1			T2	3		T4	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	3		T237	16		T158	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	1		T25	1		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T5	1		T154	1		T239	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T147	1		T159	1		T49	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T14	6		T24	16		T39	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T147	1		T53	1		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	9		T5	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T28	1		T49	4		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	1		T49	11		T237	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T24	19		T52	1		T43	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	13		T147	1		T155	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T148	1		T42	3		T150	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T9	8		T24	12		T31	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T14	7		T146	8		T194	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T53	1		T50	20		T211	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17696	1			T3	18		T6	20		T7	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T253	9		T209	1		T311	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T302	13		T305	10		T312	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T26	7		T174	10		T15	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	9		T160	10		T201	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	929	1			T4	9		T11	10		T215	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T158	13		T186	13		T192	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	1		T26	10		T146	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T5	5		T154	10		T239	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T147	4		T49	11		T151	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	6		T39	10		T40	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T147	9		T161	5		T270	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	11		T174	8		T156	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T28	4		T49	4		T192	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T5	4		T49	10		T160	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T43	14		T201	22		T46	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T1	16		T156	6		T177	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T42	2		T151	16		T216	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	7		T32	11		T42	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T14	4		T146	9		T43	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T211	2		T149	11		T177	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	2		T27	1		T39	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T26	8		T52	5		T174	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T9	1		T12	10		T25	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T2	3		T4	10		T11	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T237	1		T186	14		T192	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T1	2		T25	1		T147	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	6		T40	28		T154	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T42	1		T157	1		T177	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	9		T24	1		T39	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T147	10		T53	1		T161	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	1		T5	17		T174	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T28	5		T43	4		T46	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T49	11		T237	1		T156	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T24	1		T49	5		T52	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T1	17		T32	12		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T146	10		T148	1		T194	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T9	8		T24	1		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T14	9		T150	1		T43	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T53	1		T211	3		T149	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T268	3		T306	2		T242	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T50	1		T37	5		T307	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18299	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T302	14		T181	1		T308	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T52	11		T15	2		T43	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T9	2		T155	3		T160	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1185	1			T51	17		T210	17		T214	32
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T237	15		T186	14		T192	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T49	10		T146	15		T151	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T40	23		T44	1		T201	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T42	1		T243	4		T168	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	3		T24	15		T39	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T192	3		T261	5		T270	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	8		T156	8		T151	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T43	1		T46	4		T218	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T49	10		T237	2		T156	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T24	18		T49	3		T42	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	12		T32	9		T155	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T146	7		T286	17		T218	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T9	7		T24	11		T31	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	2		T186	2		T244	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T149	18		T186	6		T162	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T313	4		T265	1		T314	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T50	19		T37	2		T307	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T315	6		T253	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T181	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	462	1			T8	9		T41	6		T27	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T253	10		T209	2		T311	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T302	14		T305	11		T312	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T26	8		T174	11		T15	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	10		T25	1		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T2	3		T4	10		T11	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	1		T237	1		T158	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	2		T25	1		T26	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T5	6		T154	11		T239	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T147	5		T159	1		T49	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	9		T24	1		T39	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T147	10		T53	1		T161	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	1		T5	12		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T28	5		T49	5		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	5		T49	11		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T24	1		T52	1		T43	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T1	17		T147	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T148	1		T42	3		T150	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T9	8		T24	1		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T14	9		T146	10		T194	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T53	1		T50	1		T211	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17826	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T181	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T253	10		T311	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T312	2		T316	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T15	2		T43	5		T44	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T155	3		T160	10		T217	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T51	17		T52	11		T210	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	2		T237	15		T158	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T146	15		T240	2		T279	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T201	6		T286	14		T179	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T49	10		T42	1		T151	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T14	3		T24	15		T39	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T270	13		T243	4		T303	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T1	8		T156	8		T151	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T49	3		T192	3		T261	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T49	10		T237	2		T160	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T24	18		T43	5		T162	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	12		T155	7		T156	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T42	2		T151	14		T286	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T9	7		T24	11		T31	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T14	2		T146	7		T186	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T50	19		T149	18		T186	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

auto[0]

4181

1

T1

20

T9

9

T14

5