Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27484

1

T1

40

T2

3

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24196

1

T1

31

T2

3

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3288

1

T1

9

T5

23

T9

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21199

1

T3

18

T5

18

T6

20

auto[1]

6285

1

T1

40

T2

3

T4

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23422

1

T1

23

T2

3

T3

18

auto[1]

4062

1

T1

17

T4

9

T5

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	741	1			T8	9		T41	6		T27	2
values[0]	20	1			T305	11		T312	8		T308	1
values[1]	813	1			T12	10		T25	1		T26	8
values[2]	2707	1			T2	3		T4	10		T9	3
values[3]	593	1			T1	2		T5	6		T25	1
values[4]	777	1			T14	12		T24	16		T147	5
values[5]	623	1			T1	9		T5	12		T147	10
values[6]	685	1			T5	5		T28	5		T49	29
values[7]	874	1			T1	29		T24	19		T147	1
values[8]	844	1			T9	15		T24	12		T31	19
values[9]	981	1			T14	11		T53	1		T155	3
minimum	17826	1			T3	18		T6	20		T7	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	656	1			T9	3		T52	16		T174	11
values[1]	2660	1			T2	3		T4	10		T11	11
values[2]	731	1			T1	2		T5	6		T25	1
values[3]	739	1			T14	12		T24	16		T49	22
values[4]	609	1			T1	9		T5	12		T147	10
values[5]	684	1			T5	5		T49	29		T156	15
values[6]	987	1			T1	29		T24	19		T28	5
values[7]	687	1			T9	15		T24	12		T146	17
values[8]	963	1			T14	11		T53	1		T211	3
values[9]	188	1			T50	20		T268	3		T306	2
minimum	18580	1			T3	18		T6	20		T7	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

4181

1

T1

20

T9

9

T14

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T52	12		T174	1		T15	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T9	3		T155	4		T160	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1512	1			T2	3		T4	1		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T237	16		T186	15		T192	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	1		T147	1		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	1		T25	1		T40	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T49	11		T42	2		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	6		T24	16		T39	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T53	1		T161	1		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	9		T5	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T49	15		T43	3		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	1		T156	9		T160	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T1	13		T24	19		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T31	19		T32	10		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T146	8		T155	3		T194	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T9	8		T24	12		T148	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T14	7		T53	1		T149	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T211	1		T149	10		T177	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T268	1		T306	2		T242	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T50	20		T221	1		T114	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18216	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T44	2		T255	15		T181	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T52	4		T174	10		T15	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T160	10		T158	13		T192	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	911	1			T4	9		T11	10		T26	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T186	13		T192	13		T267	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	1		T147	4		T146	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T5	5		T40	24		T154	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T49	11		T151	13		T277	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T14	6		T39	10		T156	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T161	5		T150	6		T192	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T5	11		T147	9		T174	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T49	14		T43	1		T35	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T5	4		T156	6		T160	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T1	16		T28	4		T43	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T32	11		T177	1		T151	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T146	9		T216	13		T270	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	7		T42	3		T193	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T14	4		T149	2		T43	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T211	2		T149	9		T177	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T268	2		T242	13		T309	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T114	13		T317	7		T97	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T12	9		T14	2		T26	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T44	1		T255	12		T275	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	534	1			T8	9		T41	6		T27	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T50	20		T162	13		T279	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T305	1		T312	3		T308	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	1		T25	1		T26	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T155	4		T160	11		T158	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1524	1			T2	3		T4	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T9	3		T237	16		T175	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	1		T26	1		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	1		T25	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T147	1		T49	11		T146	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	6		T24	16		T39	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T53	1		T161	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	9		T5	1		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T28	1		T49	15		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	1		T156	9		T160	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	13		T24	19		T52	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T147	1		T155	8		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T146	8		T178	1		T216	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T9	8		T24	12		T31	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T14	7		T53	1		T155	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T211	1		T149	10		T177	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17696	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T266	7		T313	3		T318	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T245	10		T236	8		T319	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T305	10		T312	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	9		T26	7		T174	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T160	10		T158	13		T44	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	909	1			T4	9		T11	10		T215	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T186	13		T192	13		T267	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	1		T26	10		T211	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T5	5		T154	10		T239	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T147	4		T49	11		T146	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T14	6		T39	10		T40	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T161	5		T150	6		T178	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T5	11		T147	9		T174	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T28	4		T49	14		T192	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T5	4		T156	6		T160	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T1	16		T43	14		T201	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T177	1		T267	5		T217	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T146	9		T216	13		T286	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	7		T32	11		T42	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T14	4		T149	2		T43	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T211	2		T149	9		T177	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	2		T27	1		T39	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T52	5		T174	11		T15	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T9	1		T155	1		T160	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T2	3		T4	10		T11	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T237	1		T186	14		T192	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	2		T147	5		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	6		T25	1		T40	28
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T49	12		T42	1		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T14	9		T24	1		T39	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T53	1		T161	6		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T1	1		T5	12		T147	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T49	16		T43	3		T35	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T5	5		T156	7		T160	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T1	17		T24	1		T28	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T31	1		T32	12		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T146	10		T155	1		T194	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T9	8		T24	1		T148	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T14	9		T53	1		T149	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T211	3		T149	10		T177	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T268	3		T306	2		T242	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T50	1		T221	1		T114	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18372	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T44	2		T255	13		T181	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T52	11		T15	2		T43	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T9	2		T155	3		T160	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1175	1			T51	17		T210	17		T214	32
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T237	15		T186	14		T192	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T146	15		T240	2		T279	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T40	23		T44	1		T201	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T49	10		T42	1		T151	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T14	3		T24	15		T39	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T237	2		T192	3		T261	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T1	8		T151	13		T217	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T49	13		T43	1		T218	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T156	8		T160	13		T258	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	12		T24	18		T43	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T31	18		T32	9		T155	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T146	7		T155	2		T286	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	7		T24	11		T42	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	2		T149	9		T186	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T149	9		T162	12		T163	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T313	4		T314	3		T320	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T50	19		T114	12		T97	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T86	9		T315	6		T209	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T44	1		T255	14		T181	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	536	1			T8	9		T41	6		T27	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T50	1		T162	1		T279	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T305	11		T312	6		T308	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T12	10		T25	1		T26	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T155	1		T160	11		T158	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T2	3		T4	10		T11	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T9	1		T237	1		T175	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	2		T26	11		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T5	6		T25	1		T154	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T147	5		T49	12		T146	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T14	9		T24	1		T39	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T53	1		T161	6		T150	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	1		T5	12		T147	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T28	5		T49	16		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T5	5		T156	7		T160	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T1	17		T24	1		T52	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T147	1		T155	1		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T146	10		T178	1		T216	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T9	8		T24	1		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T14	9		T53	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T211	3		T149	10		T177	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17826	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T181	5		T266	3		T313	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T50	19		T162	12		T279	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T312	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	2		T43	5		T248	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T155	3		T160	10		T158	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1187	1			T51	17		T52	11		T210	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T9	2		T237	15		T175	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T240	2		T279	15		T251	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T201	6		T248	9		T286	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T49	10		T146	15		T42	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T14	3		T24	15		T39	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T277	13		T270	13		T303	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T1	8		T156	8		T151	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T49	13		T237	2		T192	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T156	8		T160	13		T258	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	12		T24	18		T43	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T155	7		T217	7		T47	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T146	7		T286	17		T218	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	7		T24	11		T31	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	2		T155	2		T149	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T149	9		T163	9		T228	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

auto[0]

4181

1

T1

20

T9

9

T14

5