Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27484

1

T1

40

T2

3

T3

18

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23929

1

T1

9

T2

3

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3555

1

T1

31

T5

12

T12

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21749

1

T1

40

T3

18

T5

6

auto[1]

5735

1

T2

3

T4

10

T5

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23422

1

T1

23

T2

3

T3

18

auto[1]

4062

1

T1

17

T4

9

T5

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	231	1			T25	1		T28	5		T53	1
values[0]	18	1			T293	5		T295	13		-	-
values[1]	623	1			T1	9		T31	19		T155	3
values[2]	847	1			T24	12		T25	1		T53	1
values[3]	553	1			T14	8		T26	8		T50	20
values[4]	674	1			T5	6		T147	1		T155	4
values[5]	828	1			T26	11		T147	10		T257	7
values[6]	819	1			T5	5		T49	29		T40	51
values[7]	640	1			T174	11		T237	16		T150	1
values[8]	814	1			T1	31		T5	12		T9	15
values[9]	3150	1			T2	3		T4	10		T9	3
minimum	18287	1			T3	18		T6	20		T7	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	734	1			T1	9		T31	19		T173	1
values[1]	743	1			T14	8		T24	12		T25	1
values[2]	581	1			T5	6		T26	8		T39	21
values[3]	823	1			T147	11		T156	15		T257	7
values[4]	748	1			T26	11		T40	51		T44	8
values[5]	736	1			T5	5		T49	29		T42	5
values[6]	2904	1			T2	3		T4	10		T5	12
values[7]	647	1			T1	31		T9	15		T14	3
values[8]	997	1			T9	3		T12	10		T14	12
values[9]	102	1			T25	2		T52	16		T218	9
minimum	18469	1			T3	18		T6	20		T7	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

4181

1

T1

20

T9

9

T14

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T1	9		T31	19		T174	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T173	1		T15	6		T160	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T24	12		T25	1		T237	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T14	4		T53	1		T50	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	1		T155	4		T149	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T26	1		T39	11		T177	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T147	1		T257	3		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T147	1		T156	9		T175	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T40	27		T44	6		T162	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T26	1		T193	10		T216	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	1		T239	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T49	15		T42	3		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1500	1			T2	3		T4	1		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T5	1		T147	1		T52	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	8		T14	3		T32	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	14		T159	1		T49	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T9	3		T24	19		T53	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T12	1		T14	6		T24	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T25	1		T218	9		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T25	1		T52	12		T275	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18220	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T178	1		T228	1		T291	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T174	8		T211	2		T192	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T15	2		T160	8		T43	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T154	12		T201	22		T241	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	4		T146	25		T267	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	5		T149	2		T150	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T26	7		T39	10		T177	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T147	9		T257	4		T268	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T156	6		T192	13		T45	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T40	24		T44	2		T151	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T26	10		T193	12		T216	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	4		T239	10		T43	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T49	14		T42	2		T275	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	953	1			T4	9		T11	10		T215	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T5	11		T147	4		T149	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T9	7		T32	11		T211	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T1	17		T49	11		T160	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T154	10		T149	1		T192	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	9		T14	6		T28	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T184	13		T23	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T52	4		T275	9		T321	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	2		T27	1		T39	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T291	3		T266	8		T313	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T25	1		T53	1		T270	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T28	1		T52	12		T164	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T293	1		T295	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T1	9		T31	19		T155	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T15	6		T43	6		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T24	12		T25	1		T174	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T53	1		T146	24		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T237	3		T175	5		T186	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	4		T26	1		T50	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	1		T155	4		T149	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T147	1		T156	9		T175	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T147	1		T257	3		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T26	1		T192	11		T162	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T5	1		T40	27		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T49	15		T42	3		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T174	1		T150	1		T43	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T237	16		T186	3		T191	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	8		T14	3		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T1	14		T5	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1628	1			T2	3		T4	1		T9	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T12	1		T14	6		T24	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18157	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T270	12		T184	13		T280	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T28	4		T52	4		T322	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T293	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T43	11		T186	2		T152	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T15	2		T43	4		T244	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T174	8		T154	12		T211	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T146	25		T160	8		T267	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T186	13		T152	4		T38	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T14	4		T26	7		T39	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	5		T149	2		T150	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T156	6		T177	1		T45	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T147	9		T257	4		T151	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T26	10		T192	13		T275	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T5	4		T40	24		T239	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T49	14		T42	2		T193	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T174	10		T43	1		T177	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T186	7		T47	9		T255	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	7		T161	5		T211	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	17		T5	11		T147	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T4	9		T11	10		T32	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T12	9		T14	6		T160	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	2		T27	1		T39	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	1		T31	1		T174	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T173	1		T15	6		T160	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T24	1		T25	1		T237	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	7		T53	1		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	6		T155	1		T149	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T26	8		T39	14		T177	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T147	10		T257	5		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T147	1		T156	7		T175	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T40	28		T44	6		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T26	11		T193	13		T216	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T5	5		T239	11		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T49	16		T42	3		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T2	3		T4	10		T11	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T5	12		T147	5		T52	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	8		T14	2		T32	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	19		T159	1		T49	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T9	1		T24	1		T53	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	10		T14	9		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T25	1		T218	1		T184	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T25	1		T52	5		T275	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18332	1			T3	18		T6	20		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T178	1		T228	1		T291	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	8		T31	18		T192	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T15	2		T160	13		T43	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T24	11		T237	2		T201	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	1		T50	19		T146	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T155	3		T149	9		T175	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T39	7		T179	2		T86	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T257	2		T217	7		T255	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T156	8		T175	13		T192	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T40	23		T44	2		T162	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T193	9		T294	10		T323	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T43	1		T258	10		T179	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T49	13		T42	2		T220	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1159	1			T51	17		T210	17		T214	32
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T237	15		T149	9		T186	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T9	7		T14	1		T32	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T1	12		T49	10		T160	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T9	2		T24	18		T192	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T14	3		T24	15		T42	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T218	8		T23	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T52	11		T279	11		T296	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T155	2		T186	6		T251	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T291	2		T266	10		T313	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T25	1		T53	1		T270	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T28	5		T52	5		T164	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T293	5		T295	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	1		T31	1		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T15	6		T43	5		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T24	1		T25	1		T174	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T53	1		T146	27		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T237	1		T175	1		T186	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	7		T26	8		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	6		T155	1		T149	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T147	1		T156	7		T175	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T147	10		T257	5		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T26	11		T192	14		T162	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T5	5		T40	28		T239	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T49	16		T42	3		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T174	11		T150	1		T43	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T237	1		T186	8		T191	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T9	8		T14	2		T161	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T1	19		T5	12		T147	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T2	3		T4	10		T9	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T12	10		T14	9		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18287	1			T3	18		T6	20		T7	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T270	13		T218	8		T254	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T52	11		T164	13		T324	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T295	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	8		T31	18		T155	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T15	2		T43	5		T244	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T24	11		T192	12		T201	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T146	22		T155	7		T160	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T237	2		T175	4		T186	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T14	1		T50	19		T39	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T155	3		T149	9		T255	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T156	8		T175	13		T201	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T257	2		T162	8		T151	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T192	10		T162	3		T294	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T40	23		T44	2		T258	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T49	13		T42	2		T193	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T43	1		T325	2		T168	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T237	15		T186	2		T191	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	7		T14	1		T42	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	12		T49	10		T149	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T9	2		T24	18		T32	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T14	3		T24	15		T42	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23303

1

T1

20

T2

3

T3

18

auto[1]

auto[0]

4181

1

T1

20

T9

9

T14

5