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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.07 96.67 100.00 100.00 98.83 98.33 91.14


Total test records in report: 920
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T796 /workspace/coverage/default/31.adc_ctrl_lowpower_counter.207393906 May 23 03:25:13 PM PDT 24 May 23 03:25:31 PM PDT 24 27433123117 ps
T797 /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3235442614 May 23 03:25:27 PM PDT 24 May 23 03:28:50 PM PDT 24 178843126251 ps
T308 /workspace/coverage/default/37.adc_ctrl_filters_polled.208942231 May 23 03:26:12 PM PDT 24 May 23 03:32:30 PM PDT 24 163646125160 ps
T798 /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1139470793 May 23 03:24:50 PM PDT 24 May 23 03:45:31 PM PDT 24 499719056050 ps
T799 /workspace/coverage/default/32.adc_ctrl_filters_polled.824681354 May 23 03:25:25 PM PDT 24 May 23 03:27:13 PM PDT 24 169442123765 ps
T66 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2508883785 May 23 03:34:27 PM PDT 24 May 23 03:34:33 PM PDT 24 661361759 ps
T67 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1714542901 May 23 03:34:13 PM PDT 24 May 23 03:34:22 PM PDT 24 660876493 ps
T125 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3672123419 May 23 03:34:08 PM PDT 24 May 23 03:34:18 PM PDT 24 346414374 ps
T93 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2252337392 May 23 03:34:26 PM PDT 24 May 23 03:34:32 PM PDT 24 471805520 ps
T141 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1975917792 May 23 03:34:22 PM PDT 24 May 23 03:34:27 PM PDT 24 544208161 ps
T126 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3422542753 May 23 03:34:06 PM PDT 24 May 23 03:34:15 PM PDT 24 450990400 ps
T94 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2978995881 May 23 03:34:26 PM PDT 24 May 23 03:34:32 PM PDT 24 529631843 ps
T75 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1389983002 May 23 03:34:37 PM PDT 24 May 23 03:34:42 PM PDT 24 1130919480 ps
T800 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.196550241 May 23 03:34:29 PM PDT 24 May 23 03:34:33 PM PDT 24 468444094 ps
T61 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.545046471 May 23 03:34:38 PM PDT 24 May 23 03:34:43 PM PDT 24 2347761639 ps
T801 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1940394088 May 23 03:34:46 PM PDT 24 May 23 03:34:50 PM PDT 24 388565914 ps
T62 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3981756921 May 23 03:34:41 PM PDT 24 May 23 03:34:51 PM PDT 24 4413894301 ps
T802 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4174260975 May 23 03:34:25 PM PDT 24 May 23 03:34:31 PM PDT 24 457693496 ps
T63 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1576208387 May 23 03:34:08 PM PDT 24 May 23 03:34:24 PM PDT 24 4426973639 ps
T803 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3871652002 May 23 03:34:04 PM PDT 24 May 23 03:34:12 PM PDT 24 435056507 ps
T804 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3829782377 May 23 03:34:37 PM PDT 24 May 23 03:34:40 PM PDT 24 360520016 ps
T58 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2612803341 May 23 03:34:04 PM PDT 24 May 23 03:34:18 PM PDT 24 2068891170 ps
T127 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2821321309 May 23 03:34:06 PM PDT 24 May 23 03:34:16 PM PDT 24 993608542 ps
T128 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2203440354 May 23 03:34:29 PM PDT 24 May 23 03:34:33 PM PDT 24 479237151 ps
T59 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.581216699 May 23 03:34:38 PM PDT 24 May 23 03:34:46 PM PDT 24 4990041395 ps
T73 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3161100395 May 23 03:34:09 PM PDT 24 May 23 03:34:20 PM PDT 24 752702503 ps
T142 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.675973586 May 23 03:34:26 PM PDT 24 May 23 03:34:31 PM PDT 24 398118838 ps
T74 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2000098364 May 23 03:34:27 PM PDT 24 May 23 03:34:35 PM PDT 24 574171456 ps
T143 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4260634721 May 23 03:34:30 PM PDT 24 May 23 03:34:34 PM PDT 24 569286975 ps
T129 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3750448315 May 23 03:34:24 PM PDT 24 May 23 03:34:30 PM PDT 24 437476769 ps
T64 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3534672312 May 23 03:34:49 PM PDT 24 May 23 03:34:58 PM PDT 24 4136756595 ps
T805 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2337879801 May 23 03:34:14 PM PDT 24 May 23 03:34:23 PM PDT 24 507048737 ps
T60 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.108282687 May 23 03:34:10 PM PDT 24 May 23 03:34:28 PM PDT 24 12420680219 ps
T76 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1708306209 May 23 03:34:21 PM PDT 24 May 23 03:34:28 PM PDT 24 532262034 ps
T105 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1386052931 May 23 03:34:07 PM PDT 24 May 23 03:34:17 PM PDT 24 552961050 ps
T806 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2579396449 May 23 03:34:24 PM PDT 24 May 23 03:34:31 PM PDT 24 516930730 ps
T807 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.23902129 May 23 03:34:23 PM PDT 24 May 23 03:34:28 PM PDT 24 477220948 ps
T808 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1014557948 May 23 03:34:07 PM PDT 24 May 23 03:34:17 PM PDT 24 624740602 ps
T144 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.4216156395 May 23 03:34:26 PM PDT 24 May 23 03:34:40 PM PDT 24 4143415255 ps
T130 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3346892983 May 23 03:34:07 PM PDT 24 May 23 03:34:39 PM PDT 24 22896728534 ps
T809 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1746977414 May 23 03:34:23 PM PDT 24 May 23 03:34:29 PM PDT 24 2521647607 ps
T810 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.748564952 May 23 03:34:25 PM PDT 24 May 23 03:34:32 PM PDT 24 470389991 ps
T353 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1891506199 May 23 03:34:37 PM PDT 24 May 23 03:34:51 PM PDT 24 4104604801 ps
T811 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3232443197 May 23 03:34:40 PM PDT 24 May 23 03:34:46 PM PDT 24 368609659 ps
T812 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3922621098 May 23 03:34:27 PM PDT 24 May 23 03:34:33 PM PDT 24 569421779 ps
T813 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1164372301 May 23 03:34:07 PM PDT 24 May 23 03:34:18 PM PDT 24 383453078 ps
T814 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1769127665 May 23 03:34:41 PM PDT 24 May 23 03:34:47 PM PDT 24 416116136 ps
T68 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.884640222 May 23 03:34:24 PM PDT 24 May 23 03:34:32 PM PDT 24 4576922345 ps
T815 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2000168628 May 23 03:34:39 PM PDT 24 May 23 03:34:42 PM PDT 24 486048592 ps
T816 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.830664995 May 23 03:34:04 PM PDT 24 May 23 03:34:13 PM PDT 24 315036797 ps
T817 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.914222603 May 23 03:34:39 PM PDT 24 May 23 03:34:44 PM PDT 24 487677011 ps
T818 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1483506500 May 23 03:34:29 PM PDT 24 May 23 03:34:43 PM PDT 24 4421758685 ps
T819 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2290180235 May 23 03:34:13 PM PDT 24 May 23 03:34:21 PM PDT 24 478642518 ps
T820 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1155362793 May 23 03:34:35 PM PDT 24 May 23 03:34:38 PM PDT 24 490848519 ps
T821 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2062543798 May 23 03:34:39 PM PDT 24 May 23 03:34:44 PM PDT 24 450331968 ps
T822 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4145763152 May 23 03:34:27 PM PDT 24 May 23 03:34:33 PM PDT 24 379075927 ps
T823 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2662509830 May 23 03:34:41 PM PDT 24 May 23 03:34:46 PM PDT 24 470902102 ps
T824 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3404841408 May 23 03:34:30 PM PDT 24 May 23 03:34:36 PM PDT 24 383105949 ps
T825 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3272362686 May 23 03:34:14 PM PDT 24 May 23 03:34:22 PM PDT 24 405112636 ps
T826 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1123482334 May 23 03:34:40 PM PDT 24 May 23 03:34:45 PM PDT 24 460243469 ps
T827 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3373335525 May 23 03:34:49 PM PDT 24 May 23 03:34:51 PM PDT 24 535643912 ps
T828 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3261784638 May 23 03:34:41 PM PDT 24 May 23 03:34:46 PM PDT 24 825169919 ps
T829 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1968609402 May 23 03:34:23 PM PDT 24 May 23 03:34:33 PM PDT 24 2307671017 ps
T69 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3034388546 May 23 03:34:13 PM PDT 24 May 23 03:34:42 PM PDT 24 8348146392 ps
T830 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1183987836 May 23 03:34:40 PM PDT 24 May 23 03:34:45 PM PDT 24 425658688 ps
T831 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.4068084941 May 23 03:34:07 PM PDT 24 May 23 03:34:17 PM PDT 24 583822641 ps
T832 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4268069855 May 23 03:34:38 PM PDT 24 May 23 03:34:53 PM PDT 24 8715537902 ps
T833 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3889633758 May 23 03:34:23 PM PDT 24 May 23 03:34:35 PM PDT 24 8667801430 ps
T356 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2611697154 May 23 03:34:23 PM PDT 24 May 23 03:34:38 PM PDT 24 3798988582 ps
T834 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1607356989 May 23 03:34:37 PM PDT 24 May 23 03:34:41 PM PDT 24 339367297 ps
T131 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2827875947 May 23 03:34:13 PM PDT 24 May 23 03:34:33 PM PDT 24 9717360135 ps
T835 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2576351772 May 23 03:34:36 PM PDT 24 May 23 03:34:39 PM PDT 24 476559004 ps
T836 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1169440766 May 23 03:34:38 PM PDT 24 May 23 03:34:44 PM PDT 24 4334941187 ps
T132 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2481288739 May 23 03:34:09 PM PDT 24 May 23 03:34:19 PM PDT 24 1145373524 ps
T837 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1544903340 May 23 03:34:04 PM PDT 24 May 23 03:34:24 PM PDT 24 4290965048 ps
T133 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3585934857 May 23 03:34:05 PM PDT 24 May 23 03:34:14 PM PDT 24 610473913 ps
T838 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2970349337 May 23 03:34:31 PM PDT 24 May 23 03:34:57 PM PDT 24 8605783164 ps
T839 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3021486878 May 23 03:34:25 PM PDT 24 May 23 03:34:47 PM PDT 24 5312736143 ps
T840 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3450855415 May 23 03:34:24 PM PDT 24 May 23 03:34:50 PM PDT 24 8513636034 ps
T134 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2320934255 May 23 03:34:46 PM PDT 24 May 23 03:34:50 PM PDT 24 431099747 ps
T841 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2008577666 May 23 03:34:41 PM PDT 24 May 23 03:34:46 PM PDT 24 390555364 ps
T135 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2360513135 May 23 03:34:06 PM PDT 24 May 23 03:34:17 PM PDT 24 554713827 ps
T842 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2146656747 May 23 03:34:21 PM PDT 24 May 23 03:34:27 PM PDT 24 514075803 ps
T843 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3850778750 May 23 03:34:36 PM PDT 24 May 23 03:34:38 PM PDT 24 364249217 ps
T844 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1878704336 May 23 03:34:40 PM PDT 24 May 23 03:34:45 PM PDT 24 489909746 ps
T845 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3306952282 May 23 03:34:39 PM PDT 24 May 23 03:34:46 PM PDT 24 2846047266 ps
T846 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.137765467 May 23 03:34:06 PM PDT 24 May 23 03:34:23 PM PDT 24 1318517051 ps
T847 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1455228702 May 23 03:34:31 PM PDT 24 May 23 03:34:35 PM PDT 24 527254776 ps
T848 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3921406423 May 23 03:34:40 PM PDT 24 May 23 03:34:45 PM PDT 24 327493110 ps
T849 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2145355919 May 23 03:34:32 PM PDT 24 May 23 03:34:47 PM PDT 24 4680506805 ps
T850 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.199230255 May 23 03:34:47 PM PDT 24 May 23 03:34:51 PM PDT 24 2318235988 ps
T851 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3551681483 May 23 03:34:53 PM PDT 24 May 23 03:34:57 PM PDT 24 398040727 ps
T852 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1262484003 May 23 03:34:39 PM PDT 24 May 23 03:34:44 PM PDT 24 440718428 ps
T136 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.142484315 May 23 03:34:41 PM PDT 24 May 23 03:34:46 PM PDT 24 399099926 ps
T853 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3090935083 May 23 03:34:05 PM PDT 24 May 23 03:34:14 PM PDT 24 543652796 ps
T854 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3042771794 May 23 03:34:38 PM PDT 24 May 23 03:34:41 PM PDT 24 580517663 ps
T855 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.450295693 May 23 03:34:40 PM PDT 24 May 23 03:34:48 PM PDT 24 4572656343 ps
T856 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1345612653 May 23 03:34:06 PM PDT 24 May 23 03:34:28 PM PDT 24 2724640801 ps
T857 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.534404613 May 23 03:34:40 PM PDT 24 May 23 03:34:45 PM PDT 24 278276906 ps
T137 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1143091948 May 23 03:34:27 PM PDT 24 May 23 03:34:33 PM PDT 24 421424424 ps
T858 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4009228879 May 23 03:34:07 PM PDT 24 May 23 03:34:24 PM PDT 24 5066880131 ps
T859 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3153004072 May 23 03:34:08 PM PDT 24 May 23 03:34:20 PM PDT 24 4323616099 ps
T860 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4263327729 May 23 03:34:25 PM PDT 24 May 23 03:34:34 PM PDT 24 2323502283 ps
T861 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3039444927 May 23 03:34:08 PM PDT 24 May 23 03:34:18 PM PDT 24 446718877 ps
T862 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.4098533701 May 23 03:34:39 PM PDT 24 May 23 03:34:44 PM PDT 24 488678776 ps
T863 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3585051600 May 23 03:34:44 PM PDT 24 May 23 03:34:48 PM PDT 24 366968689 ps
T864 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.612369543 May 23 03:34:40 PM PDT 24 May 23 03:34:50 PM PDT 24 3998296819 ps
T865 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1921293039 May 23 03:34:41 PM PDT 24 May 23 03:34:46 PM PDT 24 417978590 ps
T866 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3784443240 May 23 03:34:27 PM PDT 24 May 23 03:34:32 PM PDT 24 522233159 ps
T867 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.4119326669 May 23 03:34:14 PM PDT 24 May 23 03:34:23 PM PDT 24 851999506 ps
T868 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2707763235 May 23 03:34:48 PM PDT 24 May 23 03:34:53 PM PDT 24 405813290 ps
T869 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.4062500900 May 23 03:34:41 PM PDT 24 May 23 03:34:45 PM PDT 24 454544382 ps
T870 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2714390443 May 23 03:34:21 PM PDT 24 May 23 03:34:27 PM PDT 24 435247313 ps
T871 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.4047118799 May 23 03:34:04 PM PDT 24 May 23 03:34:12 PM PDT 24 845837233 ps
T872 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1584869973 May 23 03:34:25 PM PDT 24 May 23 03:34:39 PM PDT 24 4177696273 ps
T873 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1488815393 May 23 03:34:40 PM PDT 24 May 23 03:34:56 PM PDT 24 5060203658 ps
T138 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.686897961 May 23 03:34:08 PM PDT 24 May 23 03:34:19 PM PDT 24 994424809 ps
T874 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1858844748 May 23 03:34:40 PM PDT 24 May 23 03:34:46 PM PDT 24 384216974 ps
T875 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2832616274 May 23 03:34:08 PM PDT 24 May 23 03:34:20 PM PDT 24 747119538 ps
T876 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3406803103 May 23 03:34:35 PM PDT 24 May 23 03:34:39 PM PDT 24 452231729 ps
T877 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.826076412 May 23 03:34:39 PM PDT 24 May 23 03:34:44 PM PDT 24 533033640 ps
T878 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1780583428 May 23 03:34:27 PM PDT 24 May 23 03:34:32 PM PDT 24 512169300 ps
T879 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.413502208 May 23 03:34:23 PM PDT 24 May 23 03:34:28 PM PDT 24 482815643 ps
T880 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.598813871 May 23 03:34:07 PM PDT 24 May 23 03:34:16 PM PDT 24 1583362224 ps
T881 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1972204513 May 23 03:34:38 PM PDT 24 May 23 03:34:42 PM PDT 24 592128027 ps
T882 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1847498694 May 23 03:34:09 PM PDT 24 May 23 03:34:19 PM PDT 24 570483864 ps
T883 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2543518915 May 23 03:34:04 PM PDT 24 May 23 03:34:12 PM PDT 24 351458387 ps
T884 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3914825879 May 23 03:34:47 PM PDT 24 May 23 03:34:50 PM PDT 24 474728693 ps
T885 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2911901833 May 23 03:34:08 PM PDT 24 May 23 03:34:19 PM PDT 24 2074527051 ps
T886 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1352316608 May 23 03:34:40 PM PDT 24 May 23 03:34:45 PM PDT 24 504849291 ps
T887 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3568829415 May 23 03:34:39 PM PDT 24 May 23 03:34:43 PM PDT 24 370490826 ps
T888 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1776454657 May 23 03:34:40 PM PDT 24 May 23 03:34:45 PM PDT 24 580840408 ps
T889 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3178736743 May 23 03:34:22 PM PDT 24 May 23 03:34:28 PM PDT 24 347934604 ps
T890 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2521946066 May 23 03:34:41 PM PDT 24 May 23 03:34:47 PM PDT 24 453754018 ps
T891 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2692893545 May 23 03:34:24 PM PDT 24 May 23 03:34:29 PM PDT 24 435807453 ps
T139 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2645380087 May 23 03:34:03 PM PDT 24 May 23 03:34:11 PM PDT 24 523959698 ps
T892 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1857177234 May 23 03:34:45 PM PDT 24 May 23 03:34:49 PM PDT 24 518982343 ps
T893 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2437078964 May 23 03:34:27 PM PDT 24 May 23 03:34:34 PM PDT 24 540415911 ps
T894 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.669349638 May 23 03:34:09 PM PDT 24 May 23 03:34:20 PM PDT 24 619873471 ps
T895 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.404617536 May 23 03:34:50 PM PDT 24 May 23 03:34:53 PM PDT 24 522690693 ps
T896 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.589997736 May 23 03:34:39 PM PDT 24 May 23 03:34:45 PM PDT 24 665472188 ps
T897 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.158614865 May 23 03:34:39 PM PDT 24 May 23 03:34:42 PM PDT 24 431991264 ps
T898 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.911970569 May 23 03:34:25 PM PDT 24 May 23 03:34:50 PM PDT 24 8314702142 ps
T899 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3736811071 May 23 03:34:31 PM PDT 24 May 23 03:34:45 PM PDT 24 4527503800 ps
T900 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3982352839 May 23 03:34:52 PM PDT 24 May 23 03:34:55 PM PDT 24 467517858 ps
T901 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1180911325 May 23 03:34:37 PM PDT 24 May 23 03:34:40 PM PDT 24 412136330 ps
T902 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.417324572 May 23 03:34:38 PM PDT 24 May 23 03:34:43 PM PDT 24 386552109 ps
T354 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2714991652 May 23 03:34:13 PM PDT 24 May 23 03:34:25 PM PDT 24 8588635464 ps
T903 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2797793117 May 23 03:34:09 PM PDT 24 May 23 03:34:19 PM PDT 24 393704239 ps
T904 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.4017184098 May 23 03:34:10 PM PDT 24 May 23 03:34:19 PM PDT 24 637175315 ps
T905 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.948343290 May 23 03:34:38 PM PDT 24 May 23 03:34:43 PM PDT 24 1193857489 ps
T80 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3028949713 May 23 03:34:08 PM PDT 24 May 23 03:34:24 PM PDT 24 4500826102 ps
T906 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.663499362 May 23 03:34:42 PM PDT 24 May 23 03:34:46 PM PDT 24 336232148 ps
T907 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2036509540 May 23 03:34:52 PM PDT 24 May 23 03:34:54 PM PDT 24 363575697 ps
T908 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3484539890 May 23 03:34:25 PM PDT 24 May 23 03:34:31 PM PDT 24 345695626 ps
T909 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.4250152581 May 23 03:34:36 PM PDT 24 May 23 03:34:40 PM PDT 24 444730773 ps
T910 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3764603774 May 23 03:34:46 PM PDT 24 May 23 03:34:51 PM PDT 24 421180298 ps
T911 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2885435405 May 23 03:34:41 PM PDT 24 May 23 03:34:47 PM PDT 24 489585658 ps
T912 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4217594306 May 23 03:34:06 PM PDT 24 May 23 03:34:16 PM PDT 24 1072904980 ps
T913 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2191995818 May 23 03:34:46 PM PDT 24 May 23 03:34:52 PM PDT 24 2031585658 ps
T355 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2124760705 May 23 03:34:06 PM PDT 24 May 23 03:34:25 PM PDT 24 8675063660 ps
T914 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1743755798 May 23 03:34:08 PM PDT 24 May 23 03:34:18 PM PDT 24 466462594 ps
T915 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3212742833 May 23 03:34:25 PM PDT 24 May 23 03:34:32 PM PDT 24 392483008 ps
T916 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3018092627 May 23 03:34:06 PM PDT 24 May 23 03:34:18 PM PDT 24 4139765640 ps
T917 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.712383798 May 23 03:34:41 PM PDT 24 May 23 03:34:46 PM PDT 24 411625629 ps
T140 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2117229257 May 23 03:34:08 PM PDT 24 May 23 03:34:33 PM PDT 24 12784090115 ps
T918 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2006153817 May 23 03:34:24 PM PDT 24 May 23 03:34:30 PM PDT 24 565414929 ps
T919 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.282279664 May 23 03:34:44 PM PDT 24 May 23 03:34:49 PM PDT 24 427949719 ps
T920 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3338341171 May 23 03:34:24 PM PDT 24 May 23 03:34:29 PM PDT 24 427474072 ps
T81 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.919292796 May 23 03:34:27 PM PDT 24 May 23 03:34:39 PM PDT 24 8269723016 ps

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.100243472
Short name T1
Test name
Test status
Simulation time 515661141580 ps
CPU time 730.15 seconds
Started May 23 03:28:45 PM PDT 24
Finished May 23 03:40:57 PM PDT 24
Peak memory 201984 kb
Host smart-9a17b0bd-94b1-4213-9785-ed9d5ab89067
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100243472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.100243472
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2449306007
Short name T53
Test name
Test status
Simulation time 423556173779 ps
CPU time 1280.91 seconds
Started May 23 03:29:06 PM PDT 24
Finished May 23 03:50:28 PM PDT 24
Peak memory 202200 kb
Host smart-8cc68dd4-ec3a-43d1-8ec4-469bce59fa39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449306007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2449306007
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1380389235
Short name T14
Test name
Test status
Simulation time 480573951091 ps
CPU time 230.62 seconds
Started May 23 03:23:46 PM PDT 24
Finished May 23 03:27:38 PM PDT 24
Peak memory 211956 kb
Host smart-f5d67731-09b6-4ffd-9454-de12d2a53d98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380389235 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1380389235
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1812786017
Short name T43
Test name
Test status
Simulation time 591021653715 ps
CPU time 507.34 seconds
Started May 23 03:26:14 PM PDT 24
Finished May 23 03:34:44 PM PDT 24
Peak memory 210564 kb
Host smart-d475f9e1-e7c9-430b-bae8-14f400592f10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812786017 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1812786017
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3969087329
Short name T5
Test name
Test status
Simulation time 485118157271 ps
CPU time 590.02 seconds
Started May 23 03:28:12 PM PDT 24
Finished May 23 03:38:06 PM PDT 24
Peak memory 201820 kb
Host smart-250fb944-9a73-44bc-ac88-74a817d638fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969087329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3969087329
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2099725343
Short name T151
Test name
Test status
Simulation time 519277663478 ps
CPU time 191.44 seconds
Started May 23 03:22:00 PM PDT 24
Finished May 23 03:25:13 PM PDT 24
Peak memory 201848 kb
Host smart-d3ba311a-9d0b-4da3-9874-26fe1f980e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099725343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2099725343
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3353909848
Short name T186
Test name
Test status
Simulation time 489143766568 ps
CPU time 222.25 seconds
Started May 23 03:23:44 PM PDT 24
Finished May 23 03:27:28 PM PDT 24
Peak memory 201856 kb
Host smart-590d896b-dbbd-46b6-b851-6a89c746c4c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353909848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3353909848
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.4143487373
Short name T217
Test name
Test status
Simulation time 496319026252 ps
CPU time 545.75 seconds
Started May 23 03:24:53 PM PDT 24
Finished May 23 03:34:01 PM PDT 24
Peak memory 201852 kb
Host smart-10c08b3a-cfa9-4c64-b70e-c9b7c36e193e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143487373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.4143487373
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1389983002
Short name T75
Test name
Test status
Simulation time 1130919480 ps
CPU time 2.72 seconds
Started May 23 03:34:37 PM PDT 24
Finished May 23 03:34:42 PM PDT 24
Peak memory 217820 kb
Host smart-0dbcb3ab-08d0-4478-b1b1-f4dd5b9d3fff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389983002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1389983002
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.143617948
Short name T42
Test name
Test status
Simulation time 172158017740 ps
CPU time 151.83 seconds
Started May 23 03:22:42 PM PDT 24
Finished May 23 03:25:16 PM PDT 24
Peak memory 218504 kb
Host smart-685b5f62-3a2c-4d23-b1ce-157c94af7853
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143617948 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.143617948
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3164065227
Short name T162
Test name
Test status
Simulation time 639965525107 ps
CPU time 200.33 seconds
Started May 23 03:24:15 PM PDT 24
Finished May 23 03:27:38 PM PDT 24
Peak memory 201904 kb
Host smart-b4a9e153-4572-4c50-ad86-2807fd11bd3b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164065227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3164065227
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.4153152349
Short name T8
Test name
Test status
Simulation time 128816369459 ps
CPU time 465.87 seconds
Started May 23 03:23:42 PM PDT 24
Finished May 23 03:31:31 PM PDT 24
Peak memory 202184 kb
Host smart-eea4022e-ccd2-4bb3-8297-023b0dd14d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153152349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.4153152349
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2402075876
Short name T4
Test name
Test status
Simulation time 164480005729 ps
CPU time 69.02 seconds
Started May 23 03:25:59 PM PDT 24
Finished May 23 03:27:10 PM PDT 24
Peak memory 201868 kb
Host smart-81c9b48c-ea33-4127-afdc-27cce55e5068
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402075876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2402075876
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.521579012
Short name T49
Test name
Test status
Simulation time 519908350427 ps
CPU time 600.87 seconds
Started May 23 03:28:29 PM PDT 24
Finished May 23 03:38:31 PM PDT 24
Peak memory 201868 kb
Host smart-33a40f78-87a1-4467-a781-7ae1e6f956d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521579012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.521579012
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3820177172
Short name T79
Test name
Test status
Simulation time 441319240 ps
CPU time 0.92 seconds
Started May 23 03:21:30 PM PDT 24
Finished May 23 03:21:35 PM PDT 24
Peak memory 201508 kb
Host smart-4c4fb5de-09dc-447c-93e9-9edde29bf776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820177172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3820177172
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.710939144
Short name T177
Test name
Test status
Simulation time 486733383548 ps
CPU time 1087.43 seconds
Started May 23 03:25:57 PM PDT 24
Finished May 23 03:44:07 PM PDT 24
Peak memory 201812 kb
Host smart-ef2cc7fb-f22e-4f2d-8591-99e78b923983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710939144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.710939144
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2992852901
Short name T303
Test name
Test status
Simulation time 598643149604 ps
CPU time 1161.57 seconds
Started May 23 03:26:32 PM PDT 24
Finished May 23 03:45:56 PM PDT 24
Peak memory 201828 kb
Host smart-d32f7ff2-79f6-433e-ad01-b32e068760a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992852901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2992852901
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3346892983
Short name T130
Test name
Test status
Simulation time 22896728534 ps
CPU time 23.63 seconds
Started May 23 03:34:07 PM PDT 24
Finished May 23 03:34:39 PM PDT 24
Peak memory 201980 kb
Host smart-389451a3-b34d-445d-b336-23847a7387d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346892983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3346892983
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1240318658
Short name T146
Test name
Test status
Simulation time 379926254894 ps
CPU time 213.78 seconds
Started May 23 03:22:39 PM PDT 24
Finished May 23 03:26:15 PM PDT 24
Peak memory 201840 kb
Host smart-720070ec-2be3-473c-8bf8-a9f77ca94bee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240318658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1240318658
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2756842181
Short name T71
Test name
Test status
Simulation time 4482169141 ps
CPU time 10.25 seconds
Started May 23 03:21:22 PM PDT 24
Finished May 23 03:21:38 PM PDT 24
Peak memory 217504 kb
Host smart-c3a97bf5-a943-43c2-a576-d4e49a6c7fb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756842181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2756842181
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2376259589
Short name T156
Test name
Test status
Simulation time 367018596822 ps
CPU time 350.56 seconds
Started May 23 03:21:26 PM PDT 24
Finished May 23 03:27:21 PM PDT 24
Peak memory 201828 kb
Host smart-7bf7ad40-c3fc-4b81-9c94-9c3228ebd787
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376259589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2376259589
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2952882032
Short name T240
Test name
Test status
Simulation time 493865988130 ps
CPU time 307.42 seconds
Started May 23 03:21:26 PM PDT 24
Finished May 23 03:26:38 PM PDT 24
Peak memory 201796 kb
Host smart-0c95b0e9-29ba-487c-8a44-905e1c7c0109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952882032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2952882032
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.745737869
Short name T218
Test name
Test status
Simulation time 619023538985 ps
CPU time 106.75 seconds
Started May 23 03:23:28 PM PDT 24
Finished May 23 03:25:16 PM PDT 24
Peak memory 201844 kb
Host smart-f3cd3b33-4121-47e7-96ef-2d8ade65f4dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745737869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.745737869
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2105045151
Short name T263
Test name
Test status
Simulation time 491860394942 ps
CPU time 163.7 seconds
Started May 23 03:22:15 PM PDT 24
Finished May 23 03:25:00 PM PDT 24
Peak memory 201892 kb
Host smart-1723f3f3-833f-4121-aee0-843c8134eb7c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105045151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2105045151
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2816981580
Short name T52
Test name
Test status
Simulation time 333599267053 ps
CPU time 843.42 seconds
Started May 23 03:22:15 PM PDT 24
Finished May 23 03:36:20 PM PDT 24
Peak memory 201896 kb
Host smart-e49be504-c0b2-426f-aee8-97d8a76ae577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816981580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2816981580
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3244507413
Short name T236
Test name
Test status
Simulation time 493302757885 ps
CPU time 526.68 seconds
Started May 23 03:21:43 PM PDT 24
Finished May 23 03:30:32 PM PDT 24
Peak memory 201928 kb
Host smart-70264032-0556-483d-8d70-10be0b95c61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244507413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3244507413
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3059136922
Short name T201
Test name
Test status
Simulation time 538885880262 ps
CPU time 369.77 seconds
Started May 23 03:28:30 PM PDT 24
Finished May 23 03:34:41 PM PDT 24
Peak memory 201832 kb
Host smart-30ebe5b3-1420-4a6c-96ec-92e4c90f9056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059136922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3059136922
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.2137183170
Short name T313
Test name
Test status
Simulation time 532472386120 ps
CPU time 958.94 seconds
Started May 23 03:24:51 PM PDT 24
Finished May 23 03:40:51 PM PDT 24
Peak memory 201832 kb
Host smart-1ffd9b1a-53bf-4474-a0bc-6451edac369a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137183170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.2137183170
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3873754103
Short name T305
Test name
Test status
Simulation time 494809359324 ps
CPU time 1145.89 seconds
Started May 23 03:23:02 PM PDT 24
Finished May 23 03:42:10 PM PDT 24
Peak memory 201892 kb
Host smart-157b32a0-6eb1-44bd-a15a-217b78efb06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873754103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3873754103
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3435351887
Short name T275
Test name
Test status
Simulation time 504170127165 ps
CPU time 1165.25 seconds
Started May 23 03:22:42 PM PDT 24
Finished May 23 03:42:10 PM PDT 24
Peak memory 201848 kb
Host smart-657dd0ee-20a0-4f6f-8cd3-af3c05b16fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435351887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3435351887
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3802725609
Short name T273
Test name
Test status
Simulation time 348785944604 ps
CPU time 801.79 seconds
Started May 23 03:23:12 PM PDT 24
Finished May 23 03:36:35 PM PDT 24
Peak memory 201852 kb
Host smart-92ca3f2e-7c62-443c-8419-491525250a35
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802725609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3802725609
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1056097225
Short name T253
Test name
Test status
Simulation time 324811539099 ps
CPU time 310.15 seconds
Started May 23 03:21:41 PM PDT 24
Finished May 23 03:26:54 PM PDT 24
Peak memory 201832 kb
Host smart-3cd75420-08be-4088-a53a-5099ff28ced0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056097225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1056097225
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3981756921
Short name T62
Test name
Test status
Simulation time 4413894301 ps
CPU time 6.59 seconds
Started May 23 03:34:41 PM PDT 24
Finished May 23 03:34:51 PM PDT 24
Peak memory 201944 kb
Host smart-b61fd9bd-cc4b-4440-90a3-be655c4a1498
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981756921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3981756921
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.196178807
Short name T181
Test name
Test status
Simulation time 421151374177 ps
CPU time 989.34 seconds
Started May 23 03:25:10 PM PDT 24
Finished May 23 03:41:42 PM PDT 24
Peak memory 201844 kb
Host smart-06fadc56-8ad8-489a-958a-2a478fd25375
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196178807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.196178807
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.4272556328
Short name T246
Test name
Test status
Simulation time 374436067676 ps
CPU time 829.35 seconds
Started May 23 03:28:46 PM PDT 24
Finished May 23 03:42:37 PM PDT 24
Peak memory 201884 kb
Host smart-261098b5-1c8a-4e83-b2b5-dc2498a8a7d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272556328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.4272556328
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4260634721
Short name T143
Test name
Test status
Simulation time 569286975 ps
CPU time 0.98 seconds
Started May 23 03:34:30 PM PDT 24
Finished May 23 03:34:34 PM PDT 24
Peak memory 201748 kb
Host smart-46ba44c2-6882-4f81-9f39-07b96ea227a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260634721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.4260634721
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.1135298348
Short name T198
Test name
Test status
Simulation time 543317057954 ps
CPU time 209.09 seconds
Started May 23 03:22:40 PM PDT 24
Finished May 23 03:26:10 PM PDT 24
Peak memory 201884 kb
Host smart-d8114fbe-7659-46e7-bf0f-f4181c8d6e85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135298348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.1135298348
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3104401191
Short name T149
Test name
Test status
Simulation time 526688160332 ps
CPU time 822.96 seconds
Started May 23 03:29:04 PM PDT 24
Finished May 23 03:42:48 PM PDT 24
Peak memory 201868 kb
Host smart-7e695086-d676-428d-b153-2a3331061355
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104401191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3104401191
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3642759511
Short name T166
Test name
Test status
Simulation time 489792715213 ps
CPU time 1068.17 seconds
Started May 23 03:23:28 PM PDT 24
Finished May 23 03:41:18 PM PDT 24
Peak memory 201880 kb
Host smart-37bf60f4-cb8a-4ff5-9b51-fdb8ac1807e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642759511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3642759511
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3018314708
Short name T284
Test name
Test status
Simulation time 501289937626 ps
CPU time 595.66 seconds
Started May 23 03:22:55 PM PDT 24
Finished May 23 03:32:52 PM PDT 24
Peak memory 201824 kb
Host smart-bdc71ac8-9505-4b0b-9c8a-419c371e874c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018314708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3018314708
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1798095228
Short name T269
Test name
Test status
Simulation time 329591508671 ps
CPU time 573.9 seconds
Started May 23 03:22:38 PM PDT 24
Finished May 23 03:32:15 PM PDT 24
Peak memory 201980 kb
Host smart-8c05072d-0506-4eb9-b561-40cdb744a4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798095228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1798095228
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1818451138
Short name T214
Test name
Test status
Simulation time 616757108136 ps
CPU time 930.6 seconds
Started May 23 03:23:00 PM PDT 24
Finished May 23 03:38:33 PM PDT 24
Peak memory 201912 kb
Host smart-b2b9c8ea-96c0-4791-aa21-0f1975c59511
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818451138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1818451138
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.4072436822
Short name T329
Test name
Test status
Simulation time 498102452790 ps
CPU time 591.97 seconds
Started May 23 03:24:15 PM PDT 24
Finished May 23 03:34:09 PM PDT 24
Peak memory 201828 kb
Host smart-7ab1b620-0888-4ab2-90d5-72ecddd716a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072436822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.4072436822
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3356165828
Short name T97
Test name
Test status
Simulation time 499777779406 ps
CPU time 601.74 seconds
Started May 23 03:21:24 PM PDT 24
Finished May 23 03:31:31 PM PDT 24
Peak memory 201868 kb
Host smart-52a44704-61b0-4889-bfd7-2e77ad2b88d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356165828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3356165828
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.4048010757
Short name T340
Test name
Test status
Simulation time 443706361772 ps
CPU time 1063.23 seconds
Started May 23 03:22:17 PM PDT 24
Finished May 23 03:40:03 PM PDT 24
Peak memory 201848 kb
Host smart-4f2171a2-cd1c-40b5-869e-4c1eadcfa743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048010757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.4048010757
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3757829341
Short name T86
Test name
Test status
Simulation time 500348623482 ps
CPU time 491.7 seconds
Started May 23 03:24:55 PM PDT 24
Finished May 23 03:33:08 PM PDT 24
Peak memory 201916 kb
Host smart-398069e7-a35f-456c-8846-071271d41fb9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757829341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3757829341
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2243589937
Short name T251
Test name
Test status
Simulation time 419209177761 ps
CPU time 479.18 seconds
Started May 23 03:25:27 PM PDT 24
Finished May 23 03:33:29 PM PDT 24
Peak memory 201904 kb
Host smart-2e55e453-af15-4943-9424-dc42007959b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243589937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2243589937
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2792478614
Short name T232
Test name
Test status
Simulation time 134456285924 ps
CPU time 501.18 seconds
Started May 23 03:24:52 PM PDT 24
Finished May 23 03:33:15 PM PDT 24
Peak memory 202228 kb
Host smart-e85ced6b-c005-4988-87ce-1e0d604ab88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792478614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2792478614
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1757684683
Short name T298
Test name
Test status
Simulation time 500007451132 ps
CPU time 1219.09 seconds
Started May 23 03:25:09 PM PDT 24
Finished May 23 03:45:31 PM PDT 24
Peak memory 201824 kb
Host smart-b2edff34-a652-484f-8744-6d5286c4994c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757684683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1757684683
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2643872948
Short name T293
Test name
Test status
Simulation time 155829719281 ps
CPU time 186.5 seconds
Started May 23 03:21:26 PM PDT 24
Finished May 23 03:24:37 PM PDT 24
Peak memory 201836 kb
Host smart-ff4b6568-7b02-45a1-8a66-5bc72a5139b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643872948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2643872948
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1412707846
Short name T312
Test name
Test status
Simulation time 488404572645 ps
CPU time 427.36 seconds
Started May 23 03:22:16 PM PDT 24
Finished May 23 03:29:25 PM PDT 24
Peak memory 201940 kb
Host smart-db40456d-bd41-4c4f-8243-e4f35026b42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412707846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1412707846
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.977153387
Short name T271
Test name
Test status
Simulation time 335489324260 ps
CPU time 752.25 seconds
Started May 23 03:24:31 PM PDT 24
Finished May 23 03:37:06 PM PDT 24
Peak memory 201788 kb
Host smart-70f3b189-387f-459c-8993-4d52b5532e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977153387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.977153387
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2294454100
Short name T327
Test name
Test status
Simulation time 171351935294 ps
CPU time 424.61 seconds
Started May 23 03:25:27 PM PDT 24
Finished May 23 03:32:35 PM PDT 24
Peak memory 201848 kb
Host smart-5d630653-d7e0-47bc-af09-9912955a28cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294454100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2294454100
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.830664995
Short name T816
Test name
Test status
Simulation time 315036797 ps
CPU time 1.47 seconds
Started May 23 03:34:04 PM PDT 24
Finished May 23 03:34:13 PM PDT 24
Peak memory 201732 kb
Host smart-36e428b3-c358-49e7-a181-62958cc73f05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830664995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.830664995
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.412703684
Short name T296
Test name
Test status
Simulation time 548309587585 ps
CPU time 824.41 seconds
Started May 23 03:21:29 PM PDT 24
Finished May 23 03:35:17 PM PDT 24
Peak memory 201908 kb
Host smart-a6c6782e-4862-4728-81c8-6859e0621386
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412703684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.412703684
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2294289283
Short name T241
Test name
Test status
Simulation time 331427282536 ps
CPU time 180.82 seconds
Started May 23 03:22:16 PM PDT 24
Finished May 23 03:25:20 PM PDT 24
Peak memory 201932 kb
Host smart-08774be2-28a3-424f-a114-a9ea0af99433
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294289283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2294289283
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1932222373
Short name T325
Test name
Test status
Simulation time 163228030994 ps
CPU time 94.25 seconds
Started May 23 03:22:15 PM PDT 24
Finished May 23 03:23:52 PM PDT 24
Peak memory 213064 kb
Host smart-1d5786b0-bb34-4a11-8c5a-020d847653cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932222373 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1932222373
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2852200593
Short name T35
Test name
Test status
Simulation time 162844604965 ps
CPU time 385.21 seconds
Started May 23 03:24:30 PM PDT 24
Finished May 23 03:30:58 PM PDT 24
Peak memory 201832 kb
Host smart-db493a75-b570-4d7b-bf43-20cd6a6ee5fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852200593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2852200593
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1621734215
Short name T245
Test name
Test status
Simulation time 352307625902 ps
CPU time 130.16 seconds
Started May 23 03:22:01 PM PDT 24
Finished May 23 03:24:12 PM PDT 24
Peak memory 201904 kb
Host smart-8110953d-3a55-4d86-b80a-1bf32c383c91
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621734215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1621734215
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.919292796
Short name T81
Test name
Test status
Simulation time 8269723016 ps
CPU time 7.44 seconds
Started May 23 03:34:27 PM PDT 24
Finished May 23 03:34:39 PM PDT 24
Peak memory 201976 kb
Host smart-3c2fbf9d-0bd1-44f1-995c-d6d6c63d8e18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919292796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.919292796
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3894711048
Short name T282
Test name
Test status
Simulation time 490839823837 ps
CPU time 1104.91 seconds
Started May 23 03:22:16 PM PDT 24
Finished May 23 03:40:44 PM PDT 24
Peak memory 201852 kb
Host smart-c1215a71-1279-44ff-9f48-4fe54438ff65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894711048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3894711048
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.259045688
Short name T362
Test name
Test status
Simulation time 128743649989 ps
CPU time 637.68 seconds
Started May 23 03:22:21 PM PDT 24
Finished May 23 03:33:00 PM PDT 24
Peak memory 202196 kb
Host smart-686f5f19-2523-4ced-8cfb-8d0590774ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259045688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.259045688
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2440616592
Short name T314
Test name
Test status
Simulation time 306208426755 ps
CPU time 112.69 seconds
Started May 23 03:22:21 PM PDT 24
Finished May 23 03:24:15 PM PDT 24
Peak memory 210128 kb
Host smart-c83f558c-5549-40d6-8d56-f63806ab8679
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440616592 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2440616592
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3932869850
Short name T288
Test name
Test status
Simulation time 347179000815 ps
CPU time 101.47 seconds
Started May 23 03:22:41 PM PDT 24
Finished May 23 03:24:24 PM PDT 24
Peak memory 201848 kb
Host smart-436ec83f-62f3-49b5-aee3-337e5bab20f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932869850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3932869850
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3140543381
Short name T220
Test name
Test status
Simulation time 335729176643 ps
CPU time 212.3 seconds
Started May 23 03:24:16 PM PDT 24
Finished May 23 03:27:50 PM PDT 24
Peak memory 201892 kb
Host smart-4935c4f9-6b6b-479b-a335-55e2a04c784f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140543381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3140543381
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2413819370
Short name T184
Test name
Test status
Simulation time 336816563845 ps
CPU time 155.5 seconds
Started May 23 03:25:13 PM PDT 24
Finished May 23 03:27:50 PM PDT 24
Peak memory 201900 kb
Host smart-7bebd6b3-a32e-4db9-a9f0-ba12920bfdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413819370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2413819370
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.4222377668
Short name T264
Test name
Test status
Simulation time 490914582535 ps
CPU time 803.42 seconds
Started May 23 03:26:32 PM PDT 24
Finished May 23 03:39:57 PM PDT 24
Peak memory 201808 kb
Host smart-16e37b07-b4e4-4dd0-a15c-b0cbb2229903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222377668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.4222377668
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.602716414
Short name T332
Test name
Test status
Simulation time 534906206613 ps
CPU time 1295.93 seconds
Started May 23 03:27:30 PM PDT 24
Finished May 23 03:49:08 PM PDT 24
Peak memory 201964 kb
Host smart-f403ea50-5896-4bb9-ad49-c667051162d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602716414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.602716414
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2010752611
Short name T274
Test name
Test status
Simulation time 661676620972 ps
CPU time 392.07 seconds
Started May 23 03:21:58 PM PDT 24
Finished May 23 03:28:31 PM PDT 24
Peak memory 201852 kb
Host smart-f8351842-3b27-4d79-a64b-6623130c8365
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010752611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2010752611
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1115290687
Short name T192
Test name
Test status
Simulation time 499073858206 ps
CPU time 1064.62 seconds
Started May 23 03:22:00 PM PDT 24
Finished May 23 03:39:46 PM PDT 24
Peak memory 201852 kb
Host smart-2c58eeb7-ce3f-4ebe-bd37-5266a508cbbd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115290687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1115290687
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1544903340
Short name T837
Test name
Test status
Simulation time 4290965048 ps
CPU time 12.82 seconds
Started May 23 03:34:04 PM PDT 24
Finished May 23 03:34:24 PM PDT 24
Peak memory 202008 kb
Host smart-59526c85-bd1c-4a98-9e01-8efd3e802432
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544903340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1544903340
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2679642450
Short name T310
Test name
Test status
Simulation time 323212529748 ps
CPU time 394.71 seconds
Started May 23 03:22:19 PM PDT 24
Finished May 23 03:28:55 PM PDT 24
Peak memory 201812 kb
Host smart-0fc94fb5-4727-40c9-8170-a3cfbfbc3638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679642450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2679642450
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1104441972
Short name T295
Test name
Test status
Simulation time 181291418922 ps
CPU time 450.68 seconds
Started May 23 03:22:17 PM PDT 24
Finished May 23 03:29:51 PM PDT 24
Peak memory 201760 kb
Host smart-ace518ad-1d04-41f3-ad7a-5c6cb6f75e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104441972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1104441972
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.289930315
Short name T717
Test name
Test status
Simulation time 119769177684 ps
CPU time 395.35 seconds
Started May 23 03:22:35 PM PDT 24
Finished May 23 03:29:11 PM PDT 24
Peak memory 210356 kb
Host smart-a9777dbc-6f0d-40b7-9a66-1eddbdce37ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289930315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
289930315
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1460704260
Short name T252
Test name
Test status
Simulation time 209639058450 ps
CPU time 411.29 seconds
Started May 23 03:22:40 PM PDT 24
Finished May 23 03:29:33 PM PDT 24
Peak memory 201848 kb
Host smart-642fdf4c-1277-4496-995f-318d11d80265
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460704260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1460704260
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.868858105
Short name T337
Test name
Test status
Simulation time 359042546837 ps
CPU time 852.93 seconds
Started May 23 03:22:57 PM PDT 24
Finished May 23 03:37:11 PM PDT 24
Peak memory 201864 kb
Host smart-67fcfda0-0c37-433e-83c4-ff7e25a4193c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868858105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.868858105
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2624463431
Short name T39
Test name
Test status
Simulation time 188713329435 ps
CPU time 214.79 seconds
Started May 23 03:24:01 PM PDT 24
Finished May 23 03:27:38 PM PDT 24
Peak memory 201956 kb
Host smart-5285ba87-ade6-4a17-98e8-c68baf85c3b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624463431 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2624463431
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2910182028
Short name T235
Test name
Test status
Simulation time 242308208981 ps
CPU time 372.96 seconds
Started May 23 03:24:30 PM PDT 24
Finished May 23 03:30:46 PM PDT 24
Peak memory 202232 kb
Host smart-a90bd537-d1ca-4c80-b6df-5b0217a27ea5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910182028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2910182028
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.984516654
Short name T262
Test name
Test status
Simulation time 542441315304 ps
CPU time 1218.33 seconds
Started May 23 03:27:12 PM PDT 24
Finished May 23 03:47:35 PM PDT 24
Peak memory 201908 kb
Host smart-43818d57-6835-4c76-86a5-97186c97944a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984516654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.984516654
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1559248325
Short name T47
Test name
Test status
Simulation time 551738325708 ps
CPU time 863.2 seconds
Started May 23 03:27:17 PM PDT 24
Finished May 23 03:41:44 PM PDT 24
Peak memory 210536 kb
Host smart-d1366604-3520-4621-8aa0-8539e8c315a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559248325 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1559248325
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3159639789
Short name T228
Test name
Test status
Simulation time 466401453597 ps
CPU time 660.74 seconds
Started May 23 03:29:06 PM PDT 24
Finished May 23 03:40:08 PM PDT 24
Peak memory 210520 kb
Host smart-6cf39a45-4633-436e-9c34-f2ba7022764d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159639789 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3159639789
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2826154877
Short name T302
Test name
Test status
Simulation time 174640674082 ps
CPU time 388.42 seconds
Started May 23 03:21:58 PM PDT 24
Finished May 23 03:28:27 PM PDT 24
Peak memory 201836 kb
Host smart-5810f723-952e-4836-8c2d-5fb62e3f1cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826154877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2826154877
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.137765467
Short name T846
Test name
Test status
Simulation time 1318517051 ps
CPU time 5.85 seconds
Started May 23 03:34:06 PM PDT 24
Finished May 23 03:34:23 PM PDT 24
Peak memory 201904 kb
Host smart-660dd843-e58d-4091-a4cf-b6c2ed30613d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137765467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.137765467
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2612803341
Short name T58
Test name
Test status
Simulation time 2068891170 ps
CPU time 5.91 seconds
Started May 23 03:34:04 PM PDT 24
Finished May 23 03:34:18 PM PDT 24
Peak memory 201860 kb
Host smart-9077f27e-a593-4d0d-bd6d-2fa7a6a3b039
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612803341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2612803341
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.4047118799
Short name T871
Test name
Test status
Simulation time 845837233 ps
CPU time 1.16 seconds
Started May 23 03:34:04 PM PDT 24
Finished May 23 03:34:12 PM PDT 24
Peak memory 201740 kb
Host smart-73bab873-a6da-473c-85a2-9dcc50312ab0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047118799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.4047118799
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3272362686
Short name T825
Test name
Test status
Simulation time 405112636 ps
CPU time 1.03 seconds
Started May 23 03:34:14 PM PDT 24
Finished May 23 03:34:22 PM PDT 24
Peak memory 201776 kb
Host smart-0d86818c-05ea-49dd-90f9-51784a7bd1fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272362686 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3272362686
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2645380087
Short name T139
Test name
Test status
Simulation time 523959698 ps
CPU time 1.51 seconds
Started May 23 03:34:03 PM PDT 24
Finished May 23 03:34:11 PM PDT 24
Peak memory 201684 kb
Host smart-6a242e3f-fc58-48b7-9ed3-7e7b3d055dfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645380087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2645380087
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3871652002
Short name T803
Test name
Test status
Simulation time 435056507 ps
CPU time 0.92 seconds
Started May 23 03:34:04 PM PDT 24
Finished May 23 03:34:12 PM PDT 24
Peak memory 201512 kb
Host smart-29fb8a4d-ae52-47e8-a422-7a971a2299f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871652002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3871652002
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3018092627
Short name T916
Test name
Test status
Simulation time 4139765640 ps
CPU time 4.57 seconds
Started May 23 03:34:06 PM PDT 24
Finished May 23 03:34:18 PM PDT 24
Peak memory 202068 kb
Host smart-300492b2-57b2-4932-a81e-d0deead08f54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018092627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3018092627
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4217594306
Short name T912
Test name
Test status
Simulation time 1072904980 ps
CPU time 1.66 seconds
Started May 23 03:34:06 PM PDT 24
Finished May 23 03:34:16 PM PDT 24
Peak memory 201936 kb
Host smart-2d428df0-7710-44e8-8fcf-0a446602ded5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217594306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.4217594306
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.598813871
Short name T880
Test name
Test status
Simulation time 1583362224 ps
CPU time 1.06 seconds
Started May 23 03:34:07 PM PDT 24
Finished May 23 03:34:16 PM PDT 24
Peak memory 201712 kb
Host smart-950634cd-0c9e-479a-b274-266236cd75fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598813871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.598813871
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1386052931
Short name T105
Test name
Test status
Simulation time 552961050 ps
CPU time 1.99 seconds
Started May 23 03:34:07 PM PDT 24
Finished May 23 03:34:17 PM PDT 24
Peak memory 201752 kb
Host smart-8620f234-9ac3-4137-b432-d5c29326b497
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386052931 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1386052931
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2360513135
Short name T135
Test name
Test status
Simulation time 554713827 ps
CPU time 2.22 seconds
Started May 23 03:34:06 PM PDT 24
Finished May 23 03:34:17 PM PDT 24
Peak memory 201604 kb
Host smart-11eebb55-2fae-4af2-a4c6-48741064226d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360513135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2360513135
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2543518915
Short name T883
Test name
Test status
Simulation time 351458387 ps
CPU time 0.8 seconds
Started May 23 03:34:04 PM PDT 24
Finished May 23 03:34:12 PM PDT 24
Peak memory 201728 kb
Host smart-724796a7-5e18-4de2-be22-e38b8fe646d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543518915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2543518915
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1345612653
Short name T856
Test name
Test status
Simulation time 2724640801 ps
CPU time 14.24 seconds
Started May 23 03:34:06 PM PDT 24
Finished May 23 03:34:28 PM PDT 24
Peak memory 201776 kb
Host smart-9599bd2e-0b27-4f91-b7ab-807c9e3dbb89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345612653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1345612653
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2797793117
Short name T903
Test name
Test status
Simulation time 393704239 ps
CPU time 1.77 seconds
Started May 23 03:34:09 PM PDT 24
Finished May 23 03:34:19 PM PDT 24
Peak memory 202012 kb
Host smart-bec05a78-4e96-43b1-a0b5-b07b1f55a2b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797793117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2797793117
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1576208387
Short name T63
Test name
Test status
Simulation time 4426973639 ps
CPU time 7.27 seconds
Started May 23 03:34:08 PM PDT 24
Finished May 23 03:34:24 PM PDT 24
Peak memory 201920 kb
Host smart-306cc978-845e-4c13-ad47-ddfd2f6c904f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576208387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1576208387
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2692893545
Short name T891
Test name
Test status
Simulation time 435807453 ps
CPU time 0.98 seconds
Started May 23 03:34:24 PM PDT 24
Finished May 23 03:34:29 PM PDT 24
Peak memory 201732 kb
Host smart-6559629f-0195-4af5-bfb8-bd516ba6f5f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692893545 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2692893545
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3922621098
Short name T812
Test name
Test status
Simulation time 569421779 ps
CPU time 1.41 seconds
Started May 23 03:34:27 PM PDT 24
Finished May 23 03:34:33 PM PDT 24
Peak memory 201724 kb
Host smart-11adb515-57cd-46fd-9b8b-255331a096a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922621098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3922621098
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3484539890
Short name T908
Test name
Test status
Simulation time 345695626 ps
CPU time 1.47 seconds
Started May 23 03:34:25 PM PDT 24
Finished May 23 03:34:31 PM PDT 24
Peak memory 201744 kb
Host smart-026dc3c7-f97a-42ec-84c9-d23002bde479
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484539890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3484539890
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1483506500
Short name T818
Test name
Test status
Simulation time 4421758685 ps
CPU time 10.43 seconds
Started May 23 03:34:29 PM PDT 24
Finished May 23 03:34:43 PM PDT 24
Peak memory 201988 kb
Host smart-e29b1bc1-a7c6-49af-8ed6-e72de7927c49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483506500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1483506500
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2006153817
Short name T918
Test name
Test status
Simulation time 565414929 ps
CPU time 1.69 seconds
Started May 23 03:34:24 PM PDT 24
Finished May 23 03:34:30 PM PDT 24
Peak memory 201872 kb
Host smart-b395d8bf-3ccd-4c1b-9300-4632fb9728e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006153817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2006153817
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2437078964
Short name T893
Test name
Test status
Simulation time 540415911 ps
CPU time 2.07 seconds
Started May 23 03:34:27 PM PDT 24
Finished May 23 03:34:34 PM PDT 24
Peak memory 201784 kb
Host smart-04bd0fec-a9ea-4424-ae1c-9aacd8ce6406
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437078964 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2437078964
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1143091948
Short name T137
Test name
Test status
Simulation time 421424424 ps
CPU time 0.94 seconds
Started May 23 03:34:27 PM PDT 24
Finished May 23 03:34:33 PM PDT 24
Peak memory 201744 kb
Host smart-08a598cb-793e-4191-a3a1-e179afa8c7b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143091948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1143091948
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3784443240
Short name T866
Test name
Test status
Simulation time 522233159 ps
CPU time 0.94 seconds
Started May 23 03:34:27 PM PDT 24
Finished May 23 03:34:32 PM PDT 24
Peak memory 201696 kb
Host smart-bf805d60-589d-484c-94cf-0b6e7f89f807
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784443240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3784443240
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.4216156395
Short name T144
Test name
Test status
Simulation time 4143415255 ps
CPU time 10.03 seconds
Started May 23 03:34:26 PM PDT 24
Finished May 23 03:34:40 PM PDT 24
Peak memory 201996 kb
Host smart-73ded65e-1845-4436-bc29-2afa848d9cf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216156395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.4216156395
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2000098364
Short name T74
Test name
Test status
Simulation time 574171456 ps
CPU time 3.71 seconds
Started May 23 03:34:27 PM PDT 24
Finished May 23 03:34:35 PM PDT 24
Peak memory 201972 kb
Host smart-de70b948-c57e-4db0-9921-2a1eec54714f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000098364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2000098364
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2145355919
Short name T849
Test name
Test status
Simulation time 4680506805 ps
CPU time 12.67 seconds
Started May 23 03:34:32 PM PDT 24
Finished May 23 03:34:47 PM PDT 24
Peak memory 201988 kb
Host smart-f27d39e4-6708-48ee-adbb-f931b3efd914
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145355919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2145355919
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2508883785
Short name T66
Test name
Test status
Simulation time 661361759 ps
CPU time 2.4 seconds
Started May 23 03:34:27 PM PDT 24
Finished May 23 03:34:33 PM PDT 24
Peak memory 201776 kb
Host smart-4d41e2d4-de51-4857-97c7-8d5543c1f385
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508883785 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2508883785
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.196550241
Short name T800
Test name
Test status
Simulation time 468444094 ps
CPU time 0.75 seconds
Started May 23 03:34:29 PM PDT 24
Finished May 23 03:34:33 PM PDT 24
Peak memory 201720 kb
Host smart-b6b89b6d-9e82-4907-b738-bcc7667422ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196550241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.196550241
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3736811071
Short name T899
Test name
Test status
Simulation time 4527503800 ps
CPU time 10.99 seconds
Started May 23 03:34:31 PM PDT 24
Finished May 23 03:34:45 PM PDT 24
Peak memory 202000 kb
Host smart-bf424cda-833a-479c-b981-439a455b8944
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736811071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3736811071
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3404841408
Short name T824
Test name
Test status
Simulation time 383105949 ps
CPU time 2.33 seconds
Started May 23 03:34:30 PM PDT 24
Finished May 23 03:34:36 PM PDT 24
Peak memory 202036 kb
Host smart-1ad7bcb7-624a-4070-8770-de9344484062
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404841408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3404841408
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2970349337
Short name T838
Test name
Test status
Simulation time 8605783164 ps
CPU time 23.45 seconds
Started May 23 03:34:31 PM PDT 24
Finished May 23 03:34:57 PM PDT 24
Peak memory 202016 kb
Host smart-99d97dea-7af5-484a-901d-b1d26c5ee55a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970349337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.2970349337
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1180911325
Short name T901
Test name
Test status
Simulation time 412136330 ps
CPU time 1.73 seconds
Started May 23 03:34:37 PM PDT 24
Finished May 23 03:34:40 PM PDT 24
Peak memory 201728 kb
Host smart-cbbc6705-f1b0-4140-9a84-40d0c7539a8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180911325 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1180911325
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.675973586
Short name T142
Test name
Test status
Simulation time 398118838 ps
CPU time 0.96 seconds
Started May 23 03:34:26 PM PDT 24
Finished May 23 03:34:31 PM PDT 24
Peak memory 201732 kb
Host smart-d4737a70-ef25-4e74-a5f2-3f1e655d7be9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675973586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.675973586
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1780583428
Short name T878
Test name
Test status
Simulation time 512169300 ps
CPU time 0.93 seconds
Started May 23 03:34:27 PM PDT 24
Finished May 23 03:34:32 PM PDT 24
Peak memory 201720 kb
Host smart-3914541a-8f88-4250-bacf-03c3d0eeed79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780583428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1780583428
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1488815393
Short name T873
Test name
Test status
Simulation time 5060203658 ps
CPU time 12.03 seconds
Started May 23 03:34:40 PM PDT 24
Finished May 23 03:34:56 PM PDT 24
Peak memory 202008 kb
Host smart-4ba27e97-2d9e-4c7a-9396-34bda1179677
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488815393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1488815393
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.748564952
Short name T810
Test name
Test status
Simulation time 470389991 ps
CPU time 2.89 seconds
Started May 23 03:34:25 PM PDT 24
Finished May 23 03:34:32 PM PDT 24
Peak memory 201972 kb
Host smart-ef06b179-ebb3-47f2-bf32-d164aa91a73f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748564952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.748564952
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3889633758
Short name T833
Test name
Test status
Simulation time 8667801430 ps
CPU time 7.79 seconds
Started May 23 03:34:23 PM PDT 24
Finished May 23 03:34:35 PM PDT 24
Peak memory 202004 kb
Host smart-3e011647-47f5-4613-a2fa-2519b2fe2763
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889633758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3889633758
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1921293039
Short name T865
Test name
Test status
Simulation time 417978590 ps
CPU time 1.27 seconds
Started May 23 03:34:41 PM PDT 24
Finished May 23 03:34:46 PM PDT 24
Peak memory 201728 kb
Host smart-ab4c58b1-1896-4b4d-9e29-4926f5054816
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921293039 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1921293039
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1858844748
Short name T874
Test name
Test status
Simulation time 384216974 ps
CPU time 1.63 seconds
Started May 23 03:34:40 PM PDT 24
Finished May 23 03:34:46 PM PDT 24
Peak memory 201740 kb
Host smart-a232114a-1d3a-4eaf-94a4-188fe035dc74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858844748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1858844748
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.404617536
Short name T895
Test name
Test status
Simulation time 522690693 ps
CPU time 1.73 seconds
Started May 23 03:34:50 PM PDT 24
Finished May 23 03:34:53 PM PDT 24
Peak memory 201728 kb
Host smart-c7283f78-8bde-463e-ba3f-2fdb69d65b27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404617536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.404617536
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.450295693
Short name T855
Test name
Test status
Simulation time 4572656343 ps
CPU time 3.55 seconds
Started May 23 03:34:40 PM PDT 24
Finished May 23 03:34:48 PM PDT 24
Peak memory 202020 kb
Host smart-bfdc0c4b-6290-4a85-b485-05a2bb72c458
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450295693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.450295693
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4268069855
Short name T832
Test name
Test status
Simulation time 8715537902 ps
CPU time 12.56 seconds
Started May 23 03:34:38 PM PDT 24
Finished May 23 03:34:53 PM PDT 24
Peak memory 202004 kb
Host smart-9001b45b-1c2c-429b-bfda-6d56ce9ea19c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268069855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.4268069855
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1857177234
Short name T892
Test name
Test status
Simulation time 518982343 ps
CPU time 1.88 seconds
Started May 23 03:34:45 PM PDT 24
Finished May 23 03:34:49 PM PDT 24
Peak memory 201768 kb
Host smart-97418839-9195-435b-8f66-7786f97c9fbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857177234 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1857177234
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1776454657
Short name T888
Test name
Test status
Simulation time 580840408 ps
CPU time 1.2 seconds
Started May 23 03:34:40 PM PDT 24
Finished May 23 03:34:45 PM PDT 24
Peak memory 201724 kb
Host smart-4e605619-b2a3-4a1a-8371-54ef8be87031
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776454657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1776454657
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1183987836
Short name T830
Test name
Test status
Simulation time 425658688 ps
CPU time 1.8 seconds
Started May 23 03:34:40 PM PDT 24
Finished May 23 03:34:45 PM PDT 24
Peak memory 201712 kb
Host smart-39946778-97f7-4e23-8202-0b317204d7e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183987836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1183987836
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2191995818
Short name T913
Test name
Test status
Simulation time 2031585658 ps
CPU time 3.37 seconds
Started May 23 03:34:46 PM PDT 24
Finished May 23 03:34:52 PM PDT 24
Peak memory 201740 kb
Host smart-be94820e-b8fd-4bc4-9135-7f9ad03ceb0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191995818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2191995818
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1972204513
Short name T881
Test name
Test status
Simulation time 592128027 ps
CPU time 1.8 seconds
Started May 23 03:34:38 PM PDT 24
Finished May 23 03:34:42 PM PDT 24
Peak memory 201960 kb
Host smart-7a65f046-e6cf-47c1-aaa4-f2621a6e3eae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972204513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1972204513
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.612369543
Short name T864
Test name
Test status
Simulation time 3998296819 ps
CPU time 6.09 seconds
Started May 23 03:34:40 PM PDT 24
Finished May 23 03:34:50 PM PDT 24
Peak memory 201956 kb
Host smart-2eefad8b-efb6-414b-b0a6-26f4e093fd68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612369543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.612369543
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.589997736
Short name T896
Test name
Test status
Simulation time 665472188 ps
CPU time 2.53 seconds
Started May 23 03:34:39 PM PDT 24
Finished May 23 03:34:45 PM PDT 24
Peak memory 201672 kb
Host smart-a4cf19de-371e-4fb1-8344-ed95dd678b40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589997736 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.589997736
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1155362793
Short name T820
Test name
Test status
Simulation time 490848519 ps
CPU time 1.31 seconds
Started May 23 03:34:35 PM PDT 24
Finished May 23 03:34:38 PM PDT 24
Peak memory 201764 kb
Host smart-10a18c61-cb10-42da-8173-020b61db96ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155362793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1155362793
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3921406423
Short name T848
Test name
Test status
Simulation time 327493110 ps
CPU time 0.93 seconds
Started May 23 03:34:40 PM PDT 24
Finished May 23 03:34:45 PM PDT 24
Peak memory 201712 kb
Host smart-166fe737-719b-45b9-9fa9-8fd82b34d432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921406423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3921406423
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.199230255
Short name T850
Test name
Test status
Simulation time 2318235988 ps
CPU time 2.33 seconds
Started May 23 03:34:47 PM PDT 24
Finished May 23 03:34:51 PM PDT 24
Peak memory 201756 kb
Host smart-869c1965-177e-4fd4-bf7c-1bc2b7c93a60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199230255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.199230255
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.948343290
Short name T905
Test name
Test status
Simulation time 1193857489 ps
CPU time 2.08 seconds
Started May 23 03:34:38 PM PDT 24
Finished May 23 03:34:43 PM PDT 24
Peak memory 201940 kb
Host smart-4fe850e8-e631-4dee-9f6b-c293b7918083
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948343290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.948343290
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3534672312
Short name T64
Test name
Test status
Simulation time 4136756595 ps
CPU time 7.17 seconds
Started May 23 03:34:49 PM PDT 24
Finished May 23 03:34:58 PM PDT 24
Peak memory 202052 kb
Host smart-8e9c264e-f637-474e-a302-4b274abb0e98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534672312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3534672312
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3261784638
Short name T828
Test name
Test status
Simulation time 825169919 ps
CPU time 0.96 seconds
Started May 23 03:34:41 PM PDT 24
Finished May 23 03:34:46 PM PDT 24
Peak memory 201752 kb
Host smart-05f6db37-3541-4bdd-aaa3-8809cc4930c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261784638 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3261784638
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.142484315
Short name T136
Test name
Test status
Simulation time 399099926 ps
CPU time 1.01 seconds
Started May 23 03:34:41 PM PDT 24
Finished May 23 03:34:46 PM PDT 24
Peak memory 201756 kb
Host smart-c0a26ab8-4d53-4c47-b716-2b6512a83690
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142484315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.142484315
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2062543798
Short name T821
Test name
Test status
Simulation time 450331968 ps
CPU time 0.78 seconds
Started May 23 03:34:39 PM PDT 24
Finished May 23 03:34:44 PM PDT 24
Peak memory 201724 kb
Host smart-02f68e33-2195-4899-a9a3-c855f385fea4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062543798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2062543798
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.545046471
Short name T61
Test name
Test status
Simulation time 2347761639 ps
CPU time 2.27 seconds
Started May 23 03:34:38 PM PDT 24
Finished May 23 03:34:43 PM PDT 24
Peak memory 201776 kb
Host smart-3c43dcb8-2c81-494f-bf09-d6e91b02402f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545046471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.545046471
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1769127665
Short name T814
Test name
Test status
Simulation time 416116136 ps
CPU time 2.05 seconds
Started May 23 03:34:41 PM PDT 24
Finished May 23 03:34:47 PM PDT 24
Peak memory 201928 kb
Host smart-ee0730d0-acfb-432a-8ac5-65d5ee1a0d5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769127665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1769127665
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2662509830
Short name T823
Test name
Test status
Simulation time 470902102 ps
CPU time 1.31 seconds
Started May 23 03:34:41 PM PDT 24
Finished May 23 03:34:46 PM PDT 24
Peak memory 201716 kb
Host smart-2e279acb-a842-4dd9-9f01-a70e6c3fcd67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662509830 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2662509830
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1123482334
Short name T826
Test name
Test status
Simulation time 460243469 ps
CPU time 0.83 seconds
Started May 23 03:34:40 PM PDT 24
Finished May 23 03:34:45 PM PDT 24
Peak memory 201728 kb
Host smart-b69f1165-ea64-4a49-aacd-e4a6add6dc10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123482334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1123482334
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3850778750
Short name T843
Test name
Test status
Simulation time 364249217 ps
CPU time 0.85 seconds
Started May 23 03:34:36 PM PDT 24
Finished May 23 03:34:38 PM PDT 24
Peak memory 201760 kb
Host smart-d704c0d3-d80b-492c-97a0-3a1ea0ab9de4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850778750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3850778750
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3306952282
Short name T845
Test name
Test status
Simulation time 2846047266 ps
CPU time 3.18 seconds
Started May 23 03:34:39 PM PDT 24
Finished May 23 03:34:46 PM PDT 24
Peak memory 201768 kb
Host smart-78ab8a06-b5c6-4429-adb7-0573a0d11d79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306952282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3306952282
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2707763235
Short name T868
Test name
Test status
Simulation time 405813290 ps
CPU time 3.22 seconds
Started May 23 03:34:48 PM PDT 24
Finished May 23 03:34:53 PM PDT 24
Peak memory 202024 kb
Host smart-930befb5-58e8-4782-9865-045481c92da9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707763235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2707763235
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1169440766
Short name T836
Test name
Test status
Simulation time 4334941187 ps
CPU time 3.89 seconds
Started May 23 03:34:38 PM PDT 24
Finished May 23 03:34:44 PM PDT 24
Peak memory 202008 kb
Host smart-191b1a37-89e2-4eb6-b814-e2b19e66f70b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169440766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1169440766
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3042771794
Short name T854
Test name
Test status
Simulation time 580517663 ps
CPU time 1.55 seconds
Started May 23 03:34:38 PM PDT 24
Finished May 23 03:34:41 PM PDT 24
Peak memory 201780 kb
Host smart-6dd4b950-d1cd-46a4-8765-4b762203687d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042771794 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3042771794
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2320934255
Short name T134
Test name
Test status
Simulation time 431099747 ps
CPU time 1.09 seconds
Started May 23 03:34:46 PM PDT 24
Finished May 23 03:34:50 PM PDT 24
Peak memory 201740 kb
Host smart-35096b5c-ab43-4057-85bc-cf852a6dc33d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320934255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2320934255
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1262484003
Short name T852
Test name
Test status
Simulation time 440718428 ps
CPU time 1.63 seconds
Started May 23 03:34:39 PM PDT 24
Finished May 23 03:34:44 PM PDT 24
Peak memory 201744 kb
Host smart-37b0bb2c-81d5-47cb-a6f3-1ec2faa4cecc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262484003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1262484003
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.581216699
Short name T59
Test name
Test status
Simulation time 4990041395 ps
CPU time 4.98 seconds
Started May 23 03:34:38 PM PDT 24
Finished May 23 03:34:46 PM PDT 24
Peak memory 202016 kb
Host smart-6dbab9dd-35d1-4c8f-be87-263fcb4d6fed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581216699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.581216699
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2521946066
Short name T890
Test name
Test status
Simulation time 453754018 ps
CPU time 2.01 seconds
Started May 23 03:34:41 PM PDT 24
Finished May 23 03:34:47 PM PDT 24
Peak memory 218304 kb
Host smart-27b11087-3ed1-47a3-ad7f-656bd92835d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521946066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2521946066
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1891506199
Short name T353
Test name
Test status
Simulation time 4104604801 ps
CPU time 11.27 seconds
Started May 23 03:34:37 PM PDT 24
Finished May 23 03:34:51 PM PDT 24
Peak memory 201980 kb
Host smart-d84706f8-cc30-4d82-a0ce-5b2c7d6cf998
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891506199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1891506199
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.669349638
Short name T894
Test name
Test status
Simulation time 619873471 ps
CPU time 2.99 seconds
Started May 23 03:34:09 PM PDT 24
Finished May 23 03:34:20 PM PDT 24
Peak memory 201984 kb
Host smart-1af8b705-d3b5-45e4-afed-ea6ba975156b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669349638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.669349638
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2117229257
Short name T140
Test name
Test status
Simulation time 12784090115 ps
CPU time 16.05 seconds
Started May 23 03:34:08 PM PDT 24
Finished May 23 03:34:33 PM PDT 24
Peak memory 201996 kb
Host smart-ff51f853-c88d-49bc-bcfa-8f673186aeaf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117229257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2117229257
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.4119326669
Short name T867
Test name
Test status
Simulation time 851999506 ps
CPU time 1.22 seconds
Started May 23 03:34:14 PM PDT 24
Finished May 23 03:34:23 PM PDT 24
Peak memory 201752 kb
Host smart-a5de6546-a298-4f57-a747-338bf22a2f5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119326669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.4119326669
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.4068084941
Short name T831
Test name
Test status
Simulation time 583822641 ps
CPU time 2 seconds
Started May 23 03:34:07 PM PDT 24
Finished May 23 03:34:17 PM PDT 24
Peak memory 201740 kb
Host smart-a3ba9e13-fb4d-4f92-a852-fcfa7b95b77f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068084941 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.4068084941
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3672123419
Short name T125
Test name
Test status
Simulation time 346414374 ps
CPU time 1.65 seconds
Started May 23 03:34:08 PM PDT 24
Finished May 23 03:34:18 PM PDT 24
Peak memory 201728 kb
Host smart-79b34583-0fe0-4cf7-afa8-6887694bd921
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672123419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3672123419
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2290180235
Short name T819
Test name
Test status
Simulation time 478642518 ps
CPU time 0.71 seconds
Started May 23 03:34:13 PM PDT 24
Finished May 23 03:34:21 PM PDT 24
Peak memory 201736 kb
Host smart-f9610d6d-7a46-40c9-abf0-ab0d5085f998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290180235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2290180235
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3153004072
Short name T859
Test name
Test status
Simulation time 4323616099 ps
CPU time 3.31 seconds
Started May 23 03:34:08 PM PDT 24
Finished May 23 03:34:20 PM PDT 24
Peak memory 201988 kb
Host smart-deec06d7-281c-41fb-8b63-6650fa46efea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153004072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3153004072
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1164372301
Short name T813
Test name
Test status
Simulation time 383453078 ps
CPU time 2.91 seconds
Started May 23 03:34:07 PM PDT 24
Finished May 23 03:34:18 PM PDT 24
Peak memory 210172 kb
Host smart-9e6065cd-8353-475c-9612-50873e4602f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164372301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1164372301
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2124760705
Short name T355
Test name
Test status
Simulation time 8675063660 ps
CPU time 10.47 seconds
Started May 23 03:34:06 PM PDT 24
Finished May 23 03:34:25 PM PDT 24
Peak memory 201964 kb
Host smart-6d66c092-308c-4401-9bf8-435ac6041cce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124760705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2124760705
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.417324572
Short name T902
Test name
Test status
Simulation time 386552109 ps
CPU time 1.57 seconds
Started May 23 03:34:38 PM PDT 24
Finished May 23 03:34:43 PM PDT 24
Peak memory 201716 kb
Host smart-a969bd17-f9cf-4c8d-92b5-1aae3f522c4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417324572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.417324572
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1878704336
Short name T844
Test name
Test status
Simulation time 489909746 ps
CPU time 1.78 seconds
Started May 23 03:34:40 PM PDT 24
Finished May 23 03:34:45 PM PDT 24
Peak memory 201740 kb
Host smart-14c9d6bf-c0fb-497e-9f8d-bae19799b418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878704336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1878704336
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.4098533701
Short name T862
Test name
Test status
Simulation time 488678776 ps
CPU time 1.72 seconds
Started May 23 03:34:39 PM PDT 24
Finished May 23 03:34:44 PM PDT 24
Peak memory 201696 kb
Host smart-4b203ba3-14fa-4e35-812e-83b5afa21439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098533701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.4098533701
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.158614865
Short name T897
Test name
Test status
Simulation time 431991264 ps
CPU time 0.9 seconds
Started May 23 03:34:39 PM PDT 24
Finished May 23 03:34:42 PM PDT 24
Peak memory 201740 kb
Host smart-34a008cf-8efd-4a66-8fbb-19f1612f342c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158614865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.158614865
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2576351772
Short name T835
Test name
Test status
Simulation time 476559004 ps
CPU time 1 seconds
Started May 23 03:34:36 PM PDT 24
Finished May 23 03:34:39 PM PDT 24
Peak memory 201740 kb
Host smart-d79cb074-073d-4e17-868e-a816bffc6c6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576351772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2576351772
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3232443197
Short name T811
Test name
Test status
Simulation time 368609659 ps
CPU time 1.51 seconds
Started May 23 03:34:40 PM PDT 24
Finished May 23 03:34:46 PM PDT 24
Peak memory 201712 kb
Host smart-c94460da-bd65-40c8-bc2c-0ef9f9671662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232443197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3232443197
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.4250152581
Short name T909
Test name
Test status
Simulation time 444730773 ps
CPU time 1.63 seconds
Started May 23 03:34:36 PM PDT 24
Finished May 23 03:34:40 PM PDT 24
Peak memory 201668 kb
Host smart-a861e315-17c1-449b-b57f-5d348d2de902
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250152581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.4250152581
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3829782377
Short name T804
Test name
Test status
Simulation time 360520016 ps
CPU time 0.77 seconds
Started May 23 03:34:37 PM PDT 24
Finished May 23 03:34:40 PM PDT 24
Peak memory 201676 kb
Host smart-ea8fc7bb-f772-44fc-9f5e-b72b33479a8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829782377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3829782377
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2885435405
Short name T911
Test name
Test status
Simulation time 489585658 ps
CPU time 1.94 seconds
Started May 23 03:34:41 PM PDT 24
Finished May 23 03:34:47 PM PDT 24
Peak memory 201700 kb
Host smart-908d9eb5-17af-4d80-b605-698925aa684b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885435405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2885435405
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3406803103
Short name T876
Test name
Test status
Simulation time 452231729 ps
CPU time 1.67 seconds
Started May 23 03:34:35 PM PDT 24
Finished May 23 03:34:39 PM PDT 24
Peak memory 201736 kb
Host smart-3543e560-b172-4538-a964-2dd97e07917f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406803103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3406803103
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2832616274
Short name T875
Test name
Test status
Simulation time 747119538 ps
CPU time 3.56 seconds
Started May 23 03:34:08 PM PDT 24
Finished May 23 03:34:20 PM PDT 24
Peak memory 201864 kb
Host smart-d6a49d59-4c72-4b36-97c4-9dc27b8c7e6c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832616274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2832616274
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2827875947
Short name T131
Test name
Test status
Simulation time 9717360135 ps
CPU time 12.9 seconds
Started May 23 03:34:13 PM PDT 24
Finished May 23 03:34:33 PM PDT 24
Peak memory 202024 kb
Host smart-56867adf-2d7b-4d73-9f0d-9d4b8768e7a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827875947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2827875947
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2821321309
Short name T127
Test name
Test status
Simulation time 993608542 ps
CPU time 1.81 seconds
Started May 23 03:34:06 PM PDT 24
Finished May 23 03:34:16 PM PDT 24
Peak memory 201600 kb
Host smart-1e93444d-d12b-43dc-880b-31cc47e566fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821321309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2821321309
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1847498694
Short name T882
Test name
Test status
Simulation time 570483864 ps
CPU time 2.37 seconds
Started May 23 03:34:09 PM PDT 24
Finished May 23 03:34:19 PM PDT 24
Peak memory 201748 kb
Host smart-05bc7a0c-d9d5-4a40-b9c0-df027b467d61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847498694 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1847498694
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3585934857
Short name T133
Test name
Test status
Simulation time 610473913 ps
CPU time 1.15 seconds
Started May 23 03:34:05 PM PDT 24
Finished May 23 03:34:14 PM PDT 24
Peak memory 201712 kb
Host smart-0a9f6160-3e34-4388-bc8a-3c8549313a30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585934857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3585934857
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3090935083
Short name T853
Test name
Test status
Simulation time 543652796 ps
CPU time 0.92 seconds
Started May 23 03:34:05 PM PDT 24
Finished May 23 03:34:14 PM PDT 24
Peak memory 201696 kb
Host smart-7b229516-0dee-4157-8edb-927546c2c4cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090935083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3090935083
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4009228879
Short name T858
Test name
Test status
Simulation time 5066880131 ps
CPU time 8.81 seconds
Started May 23 03:34:07 PM PDT 24
Finished May 23 03:34:24 PM PDT 24
Peak memory 202036 kb
Host smart-93860db4-5159-493d-a8dc-a249a64e9a5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009228879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.4009228879
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3161100395
Short name T73
Test name
Test status
Simulation time 752702503 ps
CPU time 3.13 seconds
Started May 23 03:34:09 PM PDT 24
Finished May 23 03:34:20 PM PDT 24
Peak memory 218112 kb
Host smart-1970296d-ff31-4d77-88e9-ddde758ab005
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161100395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3161100395
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3028949713
Short name T80
Test name
Test status
Simulation time 4500826102 ps
CPU time 7.44 seconds
Started May 23 03:34:08 PM PDT 24
Finished May 23 03:34:24 PM PDT 24
Peak memory 201956 kb
Host smart-ef403509-d83d-4b54-9d3e-d24b9f5e868f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028949713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3028949713
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2000168628
Short name T815
Test name
Test status
Simulation time 486048592 ps
CPU time 1.11 seconds
Started May 23 03:34:39 PM PDT 24
Finished May 23 03:34:42 PM PDT 24
Peak memory 201720 kb
Host smart-2535258c-eb3b-4131-9519-45c26b7cb828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000168628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2000168628
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.282279664
Short name T919
Test name
Test status
Simulation time 427949719 ps
CPU time 1.61 seconds
Started May 23 03:34:44 PM PDT 24
Finished May 23 03:34:49 PM PDT 24
Peak memory 201688 kb
Host smart-b480eaa8-52c9-4073-92db-5e932a115475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282279664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.282279664
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3585051600
Short name T863
Test name
Test status
Simulation time 366968689 ps
CPU time 0.83 seconds
Started May 23 03:34:44 PM PDT 24
Finished May 23 03:34:48 PM PDT 24
Peak memory 201696 kb
Host smart-aa1f2a36-2fb7-40d2-8458-f33fb560b95f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585051600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3585051600
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.914222603
Short name T817
Test name
Test status
Simulation time 487677011 ps
CPU time 1.17 seconds
Started May 23 03:34:39 PM PDT 24
Finished May 23 03:34:44 PM PDT 24
Peak memory 201720 kb
Host smart-940f5707-d579-4818-b038-9609718c7202
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914222603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.914222603
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1940394088
Short name T801
Test name
Test status
Simulation time 388565914 ps
CPU time 1.52 seconds
Started May 23 03:34:46 PM PDT 24
Finished May 23 03:34:50 PM PDT 24
Peak memory 201720 kb
Host smart-e44765f9-4fe6-454a-9561-e1377fe10f81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940394088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1940394088
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.826076412
Short name T877
Test name
Test status
Simulation time 533033640 ps
CPU time 1.07 seconds
Started May 23 03:34:39 PM PDT 24
Finished May 23 03:34:44 PM PDT 24
Peak memory 201708 kb
Host smart-7427a592-2a06-4f8d-8bda-79ba65a93006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826076412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.826076412
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2008577666
Short name T841
Test name
Test status
Simulation time 390555364 ps
CPU time 1.51 seconds
Started May 23 03:34:41 PM PDT 24
Finished May 23 03:34:46 PM PDT 24
Peak memory 201700 kb
Host smart-04e676d6-9e4d-44f4-bfc5-26e84f944b12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008577666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2008577666
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3764603774
Short name T910
Test name
Test status
Simulation time 421180298 ps
CPU time 1.68 seconds
Started May 23 03:34:46 PM PDT 24
Finished May 23 03:34:51 PM PDT 24
Peak memory 201676 kb
Host smart-f7b27b54-0b4b-4725-82b0-59632bed1bf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764603774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3764603774
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3568829415
Short name T887
Test name
Test status
Simulation time 370490826 ps
CPU time 1.49 seconds
Started May 23 03:34:39 PM PDT 24
Finished May 23 03:34:43 PM PDT 24
Peak memory 201724 kb
Host smart-57c58412-23de-44c0-9b97-c29c3e952a2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568829415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3568829415
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3914825879
Short name T884
Test name
Test status
Simulation time 474728693 ps
CPU time 0.92 seconds
Started May 23 03:34:47 PM PDT 24
Finished May 23 03:34:50 PM PDT 24
Peak memory 201720 kb
Host smart-d60562c4-450a-4273-9d31-549eabc0c8e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914825879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3914825879
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.686897961
Short name T138
Test name
Test status
Simulation time 994424809 ps
CPU time 2.63 seconds
Started May 23 03:34:08 PM PDT 24
Finished May 23 03:34:19 PM PDT 24
Peak memory 201908 kb
Host smart-65aea381-a445-4011-a05a-806170511f7c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686897961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.686897961
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.108282687
Short name T60
Test name
Test status
Simulation time 12420680219 ps
CPU time 10.87 seconds
Started May 23 03:34:10 PM PDT 24
Finished May 23 03:34:28 PM PDT 24
Peak memory 202000 kb
Host smart-a78f7d32-7363-471c-871e-55d694345062
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108282687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_b
ash.108282687
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2481288739
Short name T132
Test name
Test status
Simulation time 1145373524 ps
CPU time 2.17 seconds
Started May 23 03:34:09 PM PDT 24
Finished May 23 03:34:19 PM PDT 24
Peak memory 201736 kb
Host smart-b304fa06-70cd-4f51-8619-c08dc5bd094e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481288739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2481288739
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.4017184098
Short name T904
Test name
Test status
Simulation time 637175315 ps
CPU time 1.36 seconds
Started May 23 03:34:10 PM PDT 24
Finished May 23 03:34:19 PM PDT 24
Peak memory 201784 kb
Host smart-4512b8f5-e9e9-420d-849b-f26098a7f582
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017184098 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.4017184098
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3422542753
Short name T126
Test name
Test status
Simulation time 450990400 ps
CPU time 1 seconds
Started May 23 03:34:06 PM PDT 24
Finished May 23 03:34:15 PM PDT 24
Peak memory 201744 kb
Host smart-960ad422-6a4c-43f5-ad60-db62af5334a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422542753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3422542753
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3039444927
Short name T861
Test name
Test status
Simulation time 446718877 ps
CPU time 1.69 seconds
Started May 23 03:34:08 PM PDT 24
Finished May 23 03:34:18 PM PDT 24
Peak memory 201692 kb
Host smart-b58c2047-5b95-4e75-8212-adb640c4e9cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039444927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3039444927
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2911901833
Short name T885
Test name
Test status
Simulation time 2074527051 ps
CPU time 3.39 seconds
Started May 23 03:34:08 PM PDT 24
Finished May 23 03:34:19 PM PDT 24
Peak memory 201740 kb
Host smart-ba8b2e1e-5b81-4f89-80ba-9bd7c3c47211
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911901833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2911901833
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1014557948
Short name T808
Test name
Test status
Simulation time 624740602 ps
CPU time 1.94 seconds
Started May 23 03:34:07 PM PDT 24
Finished May 23 03:34:17 PM PDT 24
Peak memory 210200 kb
Host smart-fce64b01-f2b5-4d09-a577-ec628909dcf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014557948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1014557948
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3034388546
Short name T69
Test name
Test status
Simulation time 8348146392 ps
CPU time 21.44 seconds
Started May 23 03:34:13 PM PDT 24
Finished May 23 03:34:42 PM PDT 24
Peak memory 202008 kb
Host smart-0a145865-892c-47d1-b772-0ced3799c2f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034388546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3034388546
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.4062500900
Short name T869
Test name
Test status
Simulation time 454544382 ps
CPU time 0.91 seconds
Started May 23 03:34:41 PM PDT 24
Finished May 23 03:34:45 PM PDT 24
Peak memory 201664 kb
Host smart-2137ee9f-8fc4-4f62-a96a-04991a77b611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062500900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.4062500900
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.663499362
Short name T906
Test name
Test status
Simulation time 336232148 ps
CPU time 0.98 seconds
Started May 23 03:34:42 PM PDT 24
Finished May 23 03:34:46 PM PDT 24
Peak memory 201688 kb
Host smart-d9339250-d0d0-401d-97a3-fd27f0ed140c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663499362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.663499362
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1607356989
Short name T834
Test name
Test status
Simulation time 339367297 ps
CPU time 1.27 seconds
Started May 23 03:34:37 PM PDT 24
Finished May 23 03:34:41 PM PDT 24
Peak memory 201736 kb
Host smart-e7485ed3-1eab-400c-af19-326a2c077fd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607356989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1607356989
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.534404613
Short name T857
Test name
Test status
Simulation time 278276906 ps
CPU time 1.18 seconds
Started May 23 03:34:40 PM PDT 24
Finished May 23 03:34:45 PM PDT 24
Peak memory 201696 kb
Host smart-82a74918-cdaa-4ef5-9882-725f192fa331
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534404613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.534404613
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1352316608
Short name T886
Test name
Test status
Simulation time 504849291 ps
CPU time 1.07 seconds
Started May 23 03:34:40 PM PDT 24
Finished May 23 03:34:45 PM PDT 24
Peak memory 201708 kb
Host smart-7a958c74-1f98-42a8-a932-1fb026b99757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352316608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1352316608
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3373335525
Short name T827
Test name
Test status
Simulation time 535643912 ps
CPU time 0.95 seconds
Started May 23 03:34:49 PM PDT 24
Finished May 23 03:34:51 PM PDT 24
Peak memory 201736 kb
Host smart-e069e152-bbed-4fca-a4c4-fbe28ee0b6ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373335525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3373335525
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.712383798
Short name T917
Test name
Test status
Simulation time 411625629 ps
CPU time 1.6 seconds
Started May 23 03:34:41 PM PDT 24
Finished May 23 03:34:46 PM PDT 24
Peak memory 201732 kb
Host smart-a8ce6b94-9964-4a46-88d4-79daf8c53a77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712383798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.712383798
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2036509540
Short name T907
Test name
Test status
Simulation time 363575697 ps
CPU time 1.39 seconds
Started May 23 03:34:52 PM PDT 24
Finished May 23 03:34:54 PM PDT 24
Peak memory 201716 kb
Host smart-b752e61e-06bc-448d-abbf-5ec0d25eac52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036509540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2036509540
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3551681483
Short name T851
Test name
Test status
Simulation time 398040727 ps
CPU time 1.38 seconds
Started May 23 03:34:53 PM PDT 24
Finished May 23 03:34:57 PM PDT 24
Peak memory 201732 kb
Host smart-8d76d42e-4147-47e4-87d4-8f0c97f21504
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551681483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3551681483
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3982352839
Short name T900
Test name
Test status
Simulation time 467517858 ps
CPU time 1.71 seconds
Started May 23 03:34:52 PM PDT 24
Finished May 23 03:34:55 PM PDT 24
Peak memory 201724 kb
Host smart-49ec8338-38b7-4fad-828d-edd8fe85a0b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982352839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3982352839
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3178736743
Short name T889
Test name
Test status
Simulation time 347934604 ps
CPU time 1.25 seconds
Started May 23 03:34:22 PM PDT 24
Finished May 23 03:34:28 PM PDT 24
Peak memory 201736 kb
Host smart-418090ad-2eb4-4b52-a3b6-4750628ca274
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178736743 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3178736743
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1743755798
Short name T914
Test name
Test status
Simulation time 466462594 ps
CPU time 1.06 seconds
Started May 23 03:34:08 PM PDT 24
Finished May 23 03:34:18 PM PDT 24
Peak memory 201720 kb
Host smart-5e2dfddd-e0bf-4c91-9a7e-5f851071ca56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743755798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1743755798
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2337879801
Short name T805
Test name
Test status
Simulation time 507048737 ps
CPU time 1.78 seconds
Started May 23 03:34:14 PM PDT 24
Finished May 23 03:34:23 PM PDT 24
Peak memory 201616 kb
Host smart-39a7405c-6da9-4ab9-b425-9afbeb19638d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337879801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2337879801
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3021486878
Short name T839
Test name
Test status
Simulation time 5312736143 ps
CPU time 17.42 seconds
Started May 23 03:34:25 PM PDT 24
Finished May 23 03:34:47 PM PDT 24
Peak memory 202040 kb
Host smart-4e4b8ddf-7cf6-4aeb-8df9-371ef817c4ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021486878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3021486878
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1714542901
Short name T67
Test name
Test status
Simulation time 660876493 ps
CPU time 1.69 seconds
Started May 23 03:34:13 PM PDT 24
Finished May 23 03:34:22 PM PDT 24
Peak memory 202028 kb
Host smart-4a2962d6-3f78-425f-9328-4bcbde7e353f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714542901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1714542901
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2714991652
Short name T354
Test name
Test status
Simulation time 8588635464 ps
CPU time 4.02 seconds
Started May 23 03:34:13 PM PDT 24
Finished May 23 03:34:25 PM PDT 24
Peak memory 201856 kb
Host smart-55687124-1d11-48f8-9c80-814de7abe9a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714991652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2714991652
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2252337392
Short name T93
Test name
Test status
Simulation time 471805520 ps
CPU time 1.26 seconds
Started May 23 03:34:26 PM PDT 24
Finished May 23 03:34:32 PM PDT 24
Peak memory 201776 kb
Host smart-ab5c4fb5-f741-434f-8fa6-a9a43324fd82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252337392 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2252337392
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1975917792
Short name T141
Test name
Test status
Simulation time 544208161 ps
CPU time 1.36 seconds
Started May 23 03:34:22 PM PDT 24
Finished May 23 03:34:27 PM PDT 24
Peak memory 201728 kb
Host smart-e5ad6099-d49a-4e6b-8d10-df3d3af77ad0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975917792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1975917792
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4174260975
Short name T802
Test name
Test status
Simulation time 457693496 ps
CPU time 1.72 seconds
Started May 23 03:34:25 PM PDT 24
Finished May 23 03:34:31 PM PDT 24
Peak memory 201704 kb
Host smart-78fc24f5-de1c-443a-81eb-0052a30008a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174260975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.4174260975
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1746977414
Short name T809
Test name
Test status
Simulation time 2521647607 ps
CPU time 1.58 seconds
Started May 23 03:34:23 PM PDT 24
Finished May 23 03:34:29 PM PDT 24
Peak memory 201804 kb
Host smart-6ce992ab-18d1-4a47-b129-04175590f0e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746977414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1746977414
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3212742833
Short name T915
Test name
Test status
Simulation time 392483008 ps
CPU time 2.83 seconds
Started May 23 03:34:25 PM PDT 24
Finished May 23 03:34:32 PM PDT 24
Peak memory 201960 kb
Host smart-306b97bb-62d6-490a-9ded-9752510cb145
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212742833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3212742833
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.911970569
Short name T898
Test name
Test status
Simulation time 8314702142 ps
CPU time 20.59 seconds
Started May 23 03:34:25 PM PDT 24
Finished May 23 03:34:50 PM PDT 24
Peak memory 202044 kb
Host smart-c41a76bc-938d-45d9-881d-6859a9e3c2c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911970569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.911970569
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.23902129
Short name T807
Test name
Test status
Simulation time 477220948 ps
CPU time 1.18 seconds
Started May 23 03:34:23 PM PDT 24
Finished May 23 03:34:28 PM PDT 24
Peak memory 201784 kb
Host smart-15c2f071-0c12-4b84-b329-0cd3e85c68f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23902129 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.23902129
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3750448315
Short name T129
Test name
Test status
Simulation time 437476769 ps
CPU time 1.03 seconds
Started May 23 03:34:24 PM PDT 24
Finished May 23 03:34:30 PM PDT 24
Peak memory 201752 kb
Host smart-98b315e3-d98e-4e08-ac52-1a1412d5deba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750448315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3750448315
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.413502208
Short name T879
Test name
Test status
Simulation time 482815643 ps
CPU time 0.88 seconds
Started May 23 03:34:23 PM PDT 24
Finished May 23 03:34:28 PM PDT 24
Peak memory 201676 kb
Host smart-46fd33f2-0426-40e5-ac59-b68d38a3cde0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413502208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.413502208
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1968609402
Short name T829
Test name
Test status
Simulation time 2307671017 ps
CPU time 5.56 seconds
Started May 23 03:34:23 PM PDT 24
Finished May 23 03:34:33 PM PDT 24
Peak memory 201756 kb
Host smart-2d5603e5-b3ac-43ff-92df-ae5351f243e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968609402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1968609402
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1455228702
Short name T847
Test name
Test status
Simulation time 527254776 ps
CPU time 1.89 seconds
Started May 23 03:34:31 PM PDT 24
Finished May 23 03:34:35 PM PDT 24
Peak memory 218312 kb
Host smart-019b1bf4-db5f-4475-9afb-98b3311d21e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455228702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1455228702
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2611697154
Short name T356
Test name
Test status
Simulation time 3798988582 ps
CPU time 11.25 seconds
Started May 23 03:34:23 PM PDT 24
Finished May 23 03:34:38 PM PDT 24
Peak memory 201968 kb
Host smart-d2e33f59-eba3-4286-95b7-39c93b042538
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611697154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2611697154
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2978995881
Short name T94
Test name
Test status
Simulation time 529631843 ps
CPU time 1.31 seconds
Started May 23 03:34:26 PM PDT 24
Finished May 23 03:34:32 PM PDT 24
Peak memory 201788 kb
Host smart-85aa6aae-691d-4447-a6eb-d7fc79e55e7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978995881 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2978995881
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2146656747
Short name T842
Test name
Test status
Simulation time 514075803 ps
CPU time 1.91 seconds
Started May 23 03:34:21 PM PDT 24
Finished May 23 03:34:27 PM PDT 24
Peak memory 201744 kb
Host smart-0ca5331a-0901-4e30-b5a1-7eab6207c1c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146656747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2146656747
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4145763152
Short name T822
Test name
Test status
Simulation time 379075927 ps
CPU time 1.56 seconds
Started May 23 03:34:27 PM PDT 24
Finished May 23 03:34:33 PM PDT 24
Peak memory 201704 kb
Host smart-b4a29fe2-4d6c-442a-bcba-0a6c3bc374bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145763152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.4145763152
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1584869973
Short name T872
Test name
Test status
Simulation time 4177696273 ps
CPU time 10.14 seconds
Started May 23 03:34:25 PM PDT 24
Finished May 23 03:34:39 PM PDT 24
Peak memory 201984 kb
Host smart-5be1bd8b-05cd-465e-a850-85e7481683c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584869973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1584869973
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2714390443
Short name T870
Test name
Test status
Simulation time 435247313 ps
CPU time 1.82 seconds
Started May 23 03:34:21 PM PDT 24
Finished May 23 03:34:27 PM PDT 24
Peak memory 202008 kb
Host smart-1c739e60-8f59-4d9d-89e7-527189a484f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714390443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2714390443
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3450855415
Short name T840
Test name
Test status
Simulation time 8513636034 ps
CPU time 22.49 seconds
Started May 23 03:34:24 PM PDT 24
Finished May 23 03:34:50 PM PDT 24
Peak memory 202000 kb
Host smart-5e6ee7d2-84e7-4b23-acb4-4fac28eb1981
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450855415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3450855415
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3338341171
Short name T920
Test name
Test status
Simulation time 427474072 ps
CPU time 1.11 seconds
Started May 23 03:34:24 PM PDT 24
Finished May 23 03:34:29 PM PDT 24
Peak memory 201772 kb
Host smart-3c71761f-4646-4013-9896-dc38b1fad65d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338341171 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3338341171
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2203440354
Short name T128
Test name
Test status
Simulation time 479237151 ps
CPU time 0.86 seconds
Started May 23 03:34:29 PM PDT 24
Finished May 23 03:34:33 PM PDT 24
Peak memory 201732 kb
Host smart-a1c354eb-8073-4f48-8693-5c3dacde4dc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203440354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2203440354
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2579396449
Short name T806
Test name
Test status
Simulation time 516930730 ps
CPU time 2.01 seconds
Started May 23 03:34:24 PM PDT 24
Finished May 23 03:34:31 PM PDT 24
Peak memory 201740 kb
Host smart-c6f3d2ff-5b8b-40fd-9cc1-c7a5e459469a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579396449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2579396449
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4263327729
Short name T860
Test name
Test status
Simulation time 2323502283 ps
CPU time 3.93 seconds
Started May 23 03:34:25 PM PDT 24
Finished May 23 03:34:34 PM PDT 24
Peak memory 201772 kb
Host smart-918c8593-f9b0-46c6-9e8e-709501ba69f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263327729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.4263327729
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1708306209
Short name T76
Test name
Test status
Simulation time 532262034 ps
CPU time 3.29 seconds
Started May 23 03:34:21 PM PDT 24
Finished May 23 03:34:28 PM PDT 24
Peak memory 201952 kb
Host smart-b8109d5c-9a99-4be9-b658-8974abdbd533
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708306209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1708306209
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.884640222
Short name T68
Test name
Test status
Simulation time 4576922345 ps
CPU time 4.02 seconds
Started May 23 03:34:24 PM PDT 24
Finished May 23 03:34:32 PM PDT 24
Peak memory 201996 kb
Host smart-664e11a2-1f10-429e-b7a2-11b6a4b598e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884640222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_int
g_err.884640222
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2241035276
Short name T780
Test name
Test status
Simulation time 350763510 ps
CPU time 1.52 seconds
Started May 23 03:21:22 PM PDT 24
Finished May 23 03:21:30 PM PDT 24
Peak memory 201508 kb
Host smart-24ab5393-8ec1-463d-8bfc-4e61b22f9e55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241035276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2241035276
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3409789037
Short name T568
Test name
Test status
Simulation time 164595145329 ps
CPU time 348.33 seconds
Started May 23 03:21:26 PM PDT 24
Finished May 23 03:27:19 PM PDT 24
Peak memory 201820 kb
Host smart-ec2d874e-d5d6-4cc7-b1ac-bc605c065b28
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409789037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3409789037
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3354289771
Short name T290
Test name
Test status
Simulation time 160972728883 ps
CPU time 360.04 seconds
Started May 23 03:21:26 PM PDT 24
Finished May 23 03:27:31 PM PDT 24
Peak memory 201940 kb
Host smart-6400f7a7-6487-42b1-b445-3ffff52b6431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354289771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3354289771
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1115907733
Short name T620
Test name
Test status
Simulation time 166560567105 ps
CPU time 378.13 seconds
Started May 23 03:21:31 PM PDT 24
Finished May 23 03:27:52 PM PDT 24
Peak memory 201748 kb
Host smart-4e08eab4-8abf-4ca9-af75-b8422770c37d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115907733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1115907733
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1866643637
Short name T107
Test name
Test status
Simulation time 588293326517 ps
CPU time 529.66 seconds
Started May 23 03:21:26 PM PDT 24
Finished May 23 03:30:21 PM PDT 24
Peak memory 201764 kb
Host smart-5cfe145f-c2d6-43c3-b013-bbbe667dcb0d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866643637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1866643637
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1715836826
Short name T56
Test name
Test status
Simulation time 88635351309 ps
CPU time 341.91 seconds
Started May 23 03:21:27 PM PDT 24
Finished May 23 03:27:13 PM PDT 24
Peak memory 202064 kb
Host smart-f4e74bdc-4b80-41f4-80c0-818abbcef941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715836826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1715836826
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.4278676719
Short name T708
Test name
Test status
Simulation time 40987115286 ps
CPU time 34.38 seconds
Started May 23 03:21:25 PM PDT 24
Finished May 23 03:22:04 PM PDT 24
Peak memory 201652 kb
Host smart-1016d151-e97f-4414-a14b-f4e70eab3276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278676719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.4278676719
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1101381913
Short name T745
Test name
Test status
Simulation time 5028887370 ps
CPU time 13.06 seconds
Started May 23 03:21:27 PM PDT 24
Finished May 23 03:21:45 PM PDT 24
Peak memory 201588 kb
Host smart-7abf84e0-7e70-4b29-8a0b-e562d68fda0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101381913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1101381913
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3950646293
Short name T404
Test name
Test status
Simulation time 5827213551 ps
CPU time 4.2 seconds
Started May 23 03:21:21 PM PDT 24
Finished May 23 03:21:31 PM PDT 24
Peak memory 201724 kb
Host smart-bee8ef28-a168-4aca-a364-223f4574a1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950646293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3950646293
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.861390237
Short name T27
Test name
Test status
Simulation time 142436439247 ps
CPU time 468.49 seconds
Started May 23 03:21:25 PM PDT 24
Finished May 23 03:29:19 PM PDT 24
Peak memory 210356 kb
Host smart-04327733-9eaf-49ca-81f6-fe9d003873a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861390237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.861390237
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1886249105
Short name T563
Test name
Test status
Simulation time 67281358511 ps
CPU time 133.25 seconds
Started May 23 03:21:26 PM PDT 24
Finished May 23 03:23:44 PM PDT 24
Peak memory 210208 kb
Host smart-f7c99cd6-6fb5-46b5-bdd9-efbea8540c19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886249105 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1886249105
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.788082142
Short name T200
Test name
Test status
Simulation time 325371086113 ps
CPU time 179.55 seconds
Started May 23 03:21:31 PM PDT 24
Finished May 23 03:24:34 PM PDT 24
Peak memory 201852 kb
Host smart-e3327e43-17df-470a-bdac-f32a8a7a4f3f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788082142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.788082142
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3231370413
Short name T557
Test name
Test status
Simulation time 329241466520 ps
CPU time 707.83 seconds
Started May 23 03:21:31 PM PDT 24
Finished May 23 03:33:22 PM PDT 24
Peak memory 201832 kb
Host smart-4803e286-97d6-499f-ac86-9b932175a128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231370413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3231370413
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.220608545
Short name T215
Test name
Test status
Simulation time 169522260496 ps
CPU time 114.8 seconds
Started May 23 03:21:31 PM PDT 24
Finished May 23 03:23:29 PM PDT 24
Peak memory 201828 kb
Host smart-87e80cd8-f6ea-4789-a0a8-16764eb717f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=220608545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.220608545
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1670564589
Short name T25
Test name
Test status
Simulation time 484394795218 ps
CPU time 1075.81 seconds
Started May 23 03:21:25 PM PDT 24
Finished May 23 03:39:26 PM PDT 24
Peak memory 201812 kb
Host smart-623ce59c-d64a-4fd4-9252-368e7a2f124a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670564589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1670564589
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1958694974
Short name T408
Test name
Test status
Simulation time 327786210851 ps
CPU time 149.33 seconds
Started May 23 03:21:25 PM PDT 24
Finished May 23 03:24:00 PM PDT 24
Peak memory 201832 kb
Host smart-ed0c4c5f-b2c0-4eb5-8854-61d59c3f81ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958694974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1958694974
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.606781527
Short name T207
Test name
Test status
Simulation time 350733135889 ps
CPU time 77.7 seconds
Started May 23 03:21:31 PM PDT 24
Finished May 23 03:22:52 PM PDT 24
Peak memory 201912 kb
Host smart-268516b2-acb7-4826-8cd5-1aea5f5384b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606781527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.606781527
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1507385425
Short name T466
Test name
Test status
Simulation time 386733995776 ps
CPU time 907.13 seconds
Started May 23 03:21:29 PM PDT 24
Finished May 23 03:36:40 PM PDT 24
Peak memory 201964 kb
Host smart-dedf9b94-9797-4f6c-bed4-549f19975515
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507385425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1507385425
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3326201278
Short name T54
Test name
Test status
Simulation time 74857045754 ps
CPU time 264.45 seconds
Started May 23 03:21:31 PM PDT 24
Finished May 23 03:25:58 PM PDT 24
Peak memory 202136 kb
Host smart-4a0adfcf-bab7-4b25-93e8-1f0e729a3f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326201278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3326201278
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.443886217
Short name T757
Test name
Test status
Simulation time 23997109367 ps
CPU time 58.09 seconds
Started May 23 03:21:29 PM PDT 24
Finished May 23 03:22:31 PM PDT 24
Peak memory 201720 kb
Host smart-9128b75e-defb-463d-ac75-0c26fb88556a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443886217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.443886217
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.587990716
Short name T642
Test name
Test status
Simulation time 3240760429 ps
CPU time 2.56 seconds
Started May 23 03:21:30 PM PDT 24
Finished May 23 03:21:36 PM PDT 24
Peak memory 201576 kb
Host smart-517b1da9-e6a5-44ca-9f0a-f6147d5515e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587990716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.587990716
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2600871957
Short name T70
Test name
Test status
Simulation time 3945266178 ps
CPU time 9.98 seconds
Started May 23 03:21:28 PM PDT 24
Finished May 23 03:21:42 PM PDT 24
Peak memory 217432 kb
Host smart-bdb512fc-fed9-47c9-9f5d-3530112b383f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600871957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2600871957
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.416729005
Short name T632
Test name
Test status
Simulation time 5864780057 ps
CPU time 3.44 seconds
Started May 23 03:21:25 PM PDT 24
Finished May 23 03:21:33 PM PDT 24
Peak memory 201612 kb
Host smart-677c33b9-e564-4734-a7fd-ba634a693168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416729005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.416729005
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1547027472
Short name T336
Test name
Test status
Simulation time 327670038046 ps
CPU time 789.55 seconds
Started May 23 03:21:23 PM PDT 24
Finished May 23 03:34:38 PM PDT 24
Peak memory 201912 kb
Host smart-f97f0404-cb04-4031-8ad3-ce212055a68c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547027472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1547027472
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.783285202
Short name T17
Test name
Test status
Simulation time 67659402642 ps
CPU time 80.32 seconds
Started May 23 03:21:30 PM PDT 24
Finished May 23 03:22:54 PM PDT 24
Peak memory 201948 kb
Host smart-37f0b751-f380-49dd-b6fa-96c70bb1e437
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783285202 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.783285202
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1812644087
Short name T99
Test name
Test status
Simulation time 344586481 ps
CPU time 1 seconds
Started May 23 03:22:17 PM PDT 24
Finished May 23 03:22:21 PM PDT 24
Peak memory 201496 kb
Host smart-5e353b5e-7e78-4078-b470-40e92422728e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812644087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1812644087
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2214733871
Short name T147
Test name
Test status
Simulation time 491398517106 ps
CPU time 1149.13 seconds
Started May 23 03:22:19 PM PDT 24
Finished May 23 03:41:30 PM PDT 24
Peak memory 201864 kb
Host smart-6f2a786b-6154-4cc2-b230-a99f1e867f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214733871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2214733871
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2926262695
Short name T574
Test name
Test status
Simulation time 159671682185 ps
CPU time 85.3 seconds
Started May 23 03:22:15 PM PDT 24
Finished May 23 03:23:42 PM PDT 24
Peak memory 201848 kb
Host smart-6b14a764-8772-4de3-81ee-9d7419695ca2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926262695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2926262695
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.606335064
Short name T718
Test name
Test status
Simulation time 167170531653 ps
CPU time 95.25 seconds
Started May 23 03:22:13 PM PDT 24
Finished May 23 03:23:50 PM PDT 24
Peak memory 201860 kb
Host smart-2b8a27d5-7f1b-4f7d-8f92-48c686324bfc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=606335064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.606335064
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3915725355
Short name T591
Test name
Test status
Simulation time 522074939158 ps
CPU time 1261.77 seconds
Started May 23 03:22:14 PM PDT 24
Finished May 23 03:43:18 PM PDT 24
Peak memory 201900 kb
Host smart-0fadd5c3-c750-40f3-9faa-492179fcb97a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915725355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3915725355
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.455790806
Short name T703
Test name
Test status
Simulation time 189057597124 ps
CPU time 397.62 seconds
Started May 23 03:22:14 PM PDT 24
Finished May 23 03:28:54 PM PDT 24
Peak memory 201848 kb
Host smart-4d62eefd-2c00-4248-bb18-b140114ef28c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455790806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.455790806
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2179164406
Short name T698
Test name
Test status
Simulation time 90690586367 ps
CPU time 322.84 seconds
Started May 23 03:22:17 PM PDT 24
Finished May 23 03:27:43 PM PDT 24
Peak memory 202232 kb
Host smart-319d3d25-4fd1-47ff-8452-03a664efcada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179164406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2179164406
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3909735224
Short name T432
Test name
Test status
Simulation time 29540161802 ps
CPU time 23.48 seconds
Started May 23 03:22:19 PM PDT 24
Finished May 23 03:22:44 PM PDT 24
Peak memory 201704 kb
Host smart-b7fccf9c-c8f3-4014-a0ac-ea273998cb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909735224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3909735224
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3957237975
Short name T713
Test name
Test status
Simulation time 4724440162 ps
CPU time 3.31 seconds
Started May 23 03:22:15 PM PDT 24
Finished May 23 03:22:20 PM PDT 24
Peak memory 201672 kb
Host smart-ff916e44-e4d9-4f67-832f-5d745047e494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957237975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3957237975
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1414121856
Short name T661
Test name
Test status
Simulation time 5693246549 ps
CPU time 3.93 seconds
Started May 23 03:22:15 PM PDT 24
Finished May 23 03:22:21 PM PDT 24
Peak memory 201680 kb
Host smart-51fd68fa-b315-49c7-911e-c662a2ccf701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414121856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1414121856
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2324003368
Short name T421
Test name
Test status
Simulation time 445914780 ps
CPU time 1.75 seconds
Started May 23 03:22:19 PM PDT 24
Finished May 23 03:22:23 PM PDT 24
Peak memory 201524 kb
Host smart-ad9d1a41-eb69-48f7-9a1f-b1422c5da8d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324003368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2324003368
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3098253284
Short name T299
Test name
Test status
Simulation time 164448894212 ps
CPU time 366 seconds
Started May 23 03:22:16 PM PDT 24
Finished May 23 03:28:24 PM PDT 24
Peak memory 201844 kb
Host smart-68239e06-f731-4267-a4bf-af136f9af036
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098253284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3098253284
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2814517495
Short name T309
Test name
Test status
Simulation time 331480387125 ps
CPU time 391.5 seconds
Started May 23 03:22:16 PM PDT 24
Finished May 23 03:28:50 PM PDT 24
Peak memory 201864 kb
Host smart-f5ec4889-821f-467c-ba49-8b10dfbd1e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814517495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2814517495
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3721584161
Short name T755
Test name
Test status
Simulation time 165506862797 ps
CPU time 99.18 seconds
Started May 23 03:22:19 PM PDT 24
Finished May 23 03:24:00 PM PDT 24
Peak memory 201928 kb
Host smart-954d3399-3519-4bc9-b8dd-7aa827e65555
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721584161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3721584161
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1708959670
Short name T697
Test name
Test status
Simulation time 499151207721 ps
CPU time 1185.63 seconds
Started May 23 03:22:21 PM PDT 24
Finished May 23 03:42:08 PM PDT 24
Peak memory 201820 kb
Host smart-e3b9a45c-9f84-4c99-8bbf-73783d1666bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708959670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1708959670
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3997249547
Short name T450
Test name
Test status
Simulation time 329484528553 ps
CPU time 816.01 seconds
Started May 23 03:22:16 PM PDT 24
Finished May 23 03:35:54 PM PDT 24
Peak memory 201816 kb
Host smart-b1206483-a6f2-45a2-aba8-74d212ae8c18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997249547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3997249547
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2993718490
Short name T31
Test name
Test status
Simulation time 182949928486 ps
CPU time 208.79 seconds
Started May 23 03:22:16 PM PDT 24
Finished May 23 03:25:47 PM PDT 24
Peak memory 201848 kb
Host smart-e42183b2-e2d2-43a9-ad31-5ebf1e8a65cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993718490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2993718490
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.754727586
Short name T615
Test name
Test status
Simulation time 570805536654 ps
CPU time 1305.88 seconds
Started May 23 03:22:18 PM PDT 24
Finished May 23 03:44:06 PM PDT 24
Peak memory 201764 kb
Host smart-2ce54d50-f928-47b9-a0b9-ca2ae5967acf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754727586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
adc_ctrl_filters_wakeup_fixed.754727586
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.226658668
Short name T778
Test name
Test status
Simulation time 22887887028 ps
CPU time 35.15 seconds
Started May 23 03:22:17 PM PDT 24
Finished May 23 03:22:54 PM PDT 24
Peak memory 201580 kb
Host smart-310921b7-ccf7-437a-9924-2271ac2badd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226658668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.226658668
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2970251669
Short name T411
Test name
Test status
Simulation time 4037963805 ps
CPU time 3.27 seconds
Started May 23 03:22:17 PM PDT 24
Finished May 23 03:22:22 PM PDT 24
Peak memory 201524 kb
Host smart-8ea0c0b8-dcb4-42c6-b18c-3c0fc8090e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970251669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2970251669
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2954770605
Short name T420
Test name
Test status
Simulation time 5935197790 ps
CPU time 13.25 seconds
Started May 23 03:22:17 PM PDT 24
Finished May 23 03:22:33 PM PDT 24
Peak memory 201628 kb
Host smart-36146dd0-1959-4ca0-89ee-0a59aed210ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954770605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2954770605
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1112519388
Short name T297
Test name
Test status
Simulation time 532187663090 ps
CPU time 186.38 seconds
Started May 23 03:22:17 PM PDT 24
Finished May 23 03:25:26 PM PDT 24
Peak memory 201752 kb
Host smart-eda18674-55ae-4fa5-b73c-e6de23aebd00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112519388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1112519388
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1216447982
Short name T601
Test name
Test status
Simulation time 477306747 ps
CPU time 0.88 seconds
Started May 23 03:22:37 PM PDT 24
Finished May 23 03:22:39 PM PDT 24
Peak memory 201600 kb
Host smart-adf5d484-91c3-4b69-b0c6-fc85cf94f5bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216447982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1216447982
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.258553778
Short name T255
Test name
Test status
Simulation time 334407061734 ps
CPU time 224.97 seconds
Started May 23 03:22:23 PM PDT 24
Finished May 23 03:26:09 PM PDT 24
Peak memory 201856 kb
Host smart-4a935e27-7800-4d2f-affc-198d7c9271f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258553778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.258553778
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1796753631
Short name T173
Test name
Test status
Simulation time 164267524039 ps
CPU time 142.36 seconds
Started May 23 03:22:25 PM PDT 24
Finished May 23 03:24:48 PM PDT 24
Peak memory 201860 kb
Host smart-3e0a9f64-6236-4139-b3ac-2a13a2865455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796753631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1796753631
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.921550366
Short name T507
Test name
Test status
Simulation time 167806476899 ps
CPU time 274.12 seconds
Started May 23 03:22:24 PM PDT 24
Finished May 23 03:26:59 PM PDT 24
Peak memory 201816 kb
Host smart-58c9c525-05ec-432c-856f-e99433f6702f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=921550366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrup
t_fixed.921550366
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1358414819
Short name T108
Test name
Test status
Simulation time 161463832754 ps
CPU time 385.57 seconds
Started May 23 03:22:24 PM PDT 24
Finished May 23 03:28:50 PM PDT 24
Peak memory 201808 kb
Host smart-6fd48db6-871b-4ef3-8f95-ba75076589d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358414819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1358414819
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1448249323
Short name T483
Test name
Test status
Simulation time 160082539500 ps
CPU time 375.68 seconds
Started May 23 03:22:25 PM PDT 24
Finished May 23 03:28:41 PM PDT 24
Peak memory 201828 kb
Host smart-13c1a872-3a16-4e1a-b28e-021a85a55e94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448249323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1448249323
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2889286457
Short name T292
Test name
Test status
Simulation time 363315236706 ps
CPU time 794.81 seconds
Started May 23 03:22:28 PM PDT 24
Finished May 23 03:35:44 PM PDT 24
Peak memory 201936 kb
Host smart-95838ea8-1997-460a-9d5d-e1b7c4f57530
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889286457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2889286457
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2047919953
Short name T673
Test name
Test status
Simulation time 206667339178 ps
CPU time 127.4 seconds
Started May 23 03:22:22 PM PDT 24
Finished May 23 03:24:31 PM PDT 24
Peak memory 201896 kb
Host smart-808cecac-33f7-495f-b7c3-ea223d90fa89
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047919953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.2047919953
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.364318279
Short name T55
Test name
Test status
Simulation time 120548264440 ps
CPU time 467.54 seconds
Started May 23 03:22:34 PM PDT 24
Finished May 23 03:30:22 PM PDT 24
Peak memory 202124 kb
Host smart-07b8325b-0ab3-4c9b-b683-0d99bc370249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364318279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.364318279
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3702696166
Short name T423
Test name
Test status
Simulation time 37148365576 ps
CPU time 22.81 seconds
Started May 23 03:22:18 PM PDT 24
Finished May 23 03:22:43 PM PDT 24
Peak memory 201672 kb
Host smart-96d01fcf-2b67-4dd0-bd4c-d662a9599c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702696166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3702696166
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1993723726
Short name T3
Test name
Test status
Simulation time 4862125277 ps
CPU time 6.59 seconds
Started May 23 03:22:18 PM PDT 24
Finished May 23 03:22:27 PM PDT 24
Peak memory 201668 kb
Host smart-797d0940-e96f-470e-8e50-f270b77289d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993723726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1993723726
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2325649932
Short name T694
Test name
Test status
Simulation time 5727411750 ps
CPU time 14.59 seconds
Started May 23 03:22:22 PM PDT 24
Finished May 23 03:22:38 PM PDT 24
Peak memory 201660 kb
Host smart-c215254a-9045-472a-b8e5-774305982c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325649932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2325649932
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3592966775
Short name T343
Test name
Test status
Simulation time 231510723914 ps
CPU time 417.26 seconds
Started May 23 03:22:37 PM PDT 24
Finished May 23 03:29:36 PM PDT 24
Peak memory 201828 kb
Host smart-eeac00a8-d83e-4d3a-a95b-a5307f02927d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592966775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3592966775
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3218698568
Short name T16
Test name
Test status
Simulation time 289062895527 ps
CPU time 198.74 seconds
Started May 23 03:22:37 PM PDT 24
Finished May 23 03:25:57 PM PDT 24
Peak memory 217828 kb
Host smart-e3da8798-c1c1-40eb-86fe-43b4ce45a0ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218698568 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3218698568
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2968373994
Short name T504
Test name
Test status
Simulation time 365199406 ps
CPU time 1.05 seconds
Started May 23 03:22:32 PM PDT 24
Finished May 23 03:22:34 PM PDT 24
Peak memory 201472 kb
Host smart-1adacded-7864-45f5-8524-928a635101b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968373994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2968373994
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.4141680295
Short name T348
Test name
Test status
Simulation time 508200248734 ps
CPU time 522.27 seconds
Started May 23 03:22:35 PM PDT 24
Finished May 23 03:31:19 PM PDT 24
Peak memory 201864 kb
Host smart-cd24b0b5-3a1b-4b1d-986c-1f6ea58d02c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141680295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.4141680295
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.2201803303
Short name T117
Test name
Test status
Simulation time 347357862034 ps
CPU time 788.25 seconds
Started May 23 03:22:38 PM PDT 24
Finished May 23 03:35:48 PM PDT 24
Peak memory 201732 kb
Host smart-113b5c5d-6565-4a76-8727-8273b82664c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201803303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.2201803303
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.4029469777
Short name T675
Test name
Test status
Simulation time 331186449872 ps
CPU time 346.11 seconds
Started May 23 03:22:37 PM PDT 24
Finished May 23 03:28:24 PM PDT 24
Peak memory 201836 kb
Host smart-3ef17fe5-69d6-4642-be21-501a42ebe560
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029469777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.4029469777
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3289492572
Short name T635
Test name
Test status
Simulation time 485499588701 ps
CPU time 598.03 seconds
Started May 23 03:22:35 PM PDT 24
Finished May 23 03:32:34 PM PDT 24
Peak memory 201788 kb
Host smart-24b6e193-009e-43ef-9a72-3cb962d2688d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289492572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3289492572
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1625714794
Short name T391
Test name
Test status
Simulation time 496960112149 ps
CPU time 605.82 seconds
Started May 23 03:22:40 PM PDT 24
Finished May 23 03:32:47 PM PDT 24
Peak memory 201868 kb
Host smart-3e5437b8-d528-4192-ad92-3d342e17ab59
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625714794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1625714794
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.911921020
Short name T259
Test name
Test status
Simulation time 522614953354 ps
CPU time 89.95 seconds
Started May 23 03:22:39 PM PDT 24
Finished May 23 03:24:10 PM PDT 24
Peak memory 201832 kb
Host smart-b8fe8414-30e9-45a1-82ab-43cff5599ca6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911921020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.911921020
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3898413112
Short name T641
Test name
Test status
Simulation time 212195535283 ps
CPU time 482.48 seconds
Started May 23 03:22:38 PM PDT 24
Finished May 23 03:30:42 PM PDT 24
Peak memory 201860 kb
Host smart-55150576-32d0-4cc7-9d4e-2e6ed3549d2d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898413112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3898413112
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.644232116
Short name T508
Test name
Test status
Simulation time 94046658045 ps
CPU time 317.22 seconds
Started May 23 03:22:39 PM PDT 24
Finished May 23 03:27:58 PM PDT 24
Peak memory 202120 kb
Host smart-25383727-3fbd-4c2b-9205-f4e7a91707a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644232116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.644232116
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.291154849
Short name T532
Test name
Test status
Simulation time 32638091429 ps
CPU time 71.5 seconds
Started May 23 03:22:38 PM PDT 24
Finished May 23 03:23:51 PM PDT 24
Peak memory 201688 kb
Host smart-fea00c93-4782-48db-aaa4-fb6ecf2c31a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291154849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.291154849
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.437829528
Short name T487
Test name
Test status
Simulation time 4585571238 ps
CPU time 1.68 seconds
Started May 23 03:22:35 PM PDT 24
Finished May 23 03:22:38 PM PDT 24
Peak memory 201640 kb
Host smart-653edd1e-0a5a-4e7e-86db-a22bb211e857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437829528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.437829528
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3097238681
Short name T100
Test name
Test status
Simulation time 5935342908 ps
CPU time 1.62 seconds
Started May 23 03:22:36 PM PDT 24
Finished May 23 03:22:39 PM PDT 24
Peak memory 201688 kb
Host smart-27e3be53-3d71-474b-b099-65b9cf460ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097238681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3097238681
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.4183880831
Short name T20
Test name
Test status
Simulation time 210311898473 ps
CPU time 128.82 seconds
Started May 23 03:22:39 PM PDT 24
Finished May 23 03:24:49 PM PDT 24
Peak memory 210048 kb
Host smart-4b77b56e-e4d3-489a-b352-ebca06c2f761
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183880831 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.4183880831
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1192327658
Short name T779
Test name
Test status
Simulation time 450463808 ps
CPU time 0.85 seconds
Started May 23 03:22:35 PM PDT 24
Finished May 23 03:22:37 PM PDT 24
Peak memory 201568 kb
Host smart-b6969c34-bb56-44cf-8997-aee99f431a4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192327658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1192327658
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1298641676
Short name T656
Test name
Test status
Simulation time 183846493564 ps
CPU time 68.85 seconds
Started May 23 03:22:36 PM PDT 24
Finished May 23 03:23:46 PM PDT 24
Peak memory 201828 kb
Host smart-60d66b0d-9032-46cb-a22d-4e3ee7c8e80c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298641676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1298641676
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.332229206
Short name T662
Test name
Test status
Simulation time 176943332019 ps
CPU time 209.6 seconds
Started May 23 03:22:42 PM PDT 24
Finished May 23 03:26:14 PM PDT 24
Peak memory 201848 kb
Host smart-117f7a24-dcf6-4025-8550-6105dfe0137b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332229206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.332229206
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1623409122
Short name T643
Test name
Test status
Simulation time 488636201903 ps
CPU time 494.75 seconds
Started May 23 03:22:37 PM PDT 24
Finished May 23 03:30:53 PM PDT 24
Peak memory 201860 kb
Host smart-84c76882-eac3-4d2b-8823-51f73b3e2653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623409122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1623409122
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.217130879
Short name T372
Test name
Test status
Simulation time 166247231403 ps
CPU time 385.24 seconds
Started May 23 03:22:35 PM PDT 24
Finished May 23 03:29:01 PM PDT 24
Peak memory 201804 kb
Host smart-78e1fef4-ed45-4d5b-80d5-ee736677ed52
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=217130879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.217130879
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1234066389
Short name T696
Test name
Test status
Simulation time 502820162559 ps
CPU time 260.27 seconds
Started May 23 03:22:38 PM PDT 24
Finished May 23 03:27:00 PM PDT 24
Peak memory 201832 kb
Host smart-ee65ef75-b9eb-4af7-a766-983fc38558ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234066389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1234066389
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.868808880
Short name T758
Test name
Test status
Simulation time 161217498436 ps
CPU time 178.35 seconds
Started May 23 03:22:35 PM PDT 24
Finished May 23 03:25:34 PM PDT 24
Peak memory 201820 kb
Host smart-82944b0a-9e49-43ec-8289-4df9c2a05adf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=868808880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.868808880
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1136173318
Short name T256
Test name
Test status
Simulation time 575218951467 ps
CPU time 714.22 seconds
Started May 23 03:22:39 PM PDT 24
Finished May 23 03:34:35 PM PDT 24
Peak memory 201908 kb
Host smart-f5d871f7-d839-4e39-968f-b7c7f5d7d183
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136173318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1136173318
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1743236150
Short name T621
Test name
Test status
Simulation time 191830261800 ps
CPU time 115.44 seconds
Started May 23 03:22:37 PM PDT 24
Finished May 23 03:24:33 PM PDT 24
Peak memory 201868 kb
Host smart-3ba00648-3225-4e31-8ff1-28158d43a323
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743236150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1743236150
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.4075140254
Short name T776
Test name
Test status
Simulation time 62126701203 ps
CPU time 217 seconds
Started May 23 03:22:39 PM PDT 24
Finished May 23 03:26:17 PM PDT 24
Peak memory 202196 kb
Host smart-0b7b2102-04b4-423b-9a55-55dad6c513a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075140254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.4075140254
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.993652649
Short name T666
Test name
Test status
Simulation time 28321952425 ps
CPU time 62.99 seconds
Started May 23 03:22:36 PM PDT 24
Finished May 23 03:23:41 PM PDT 24
Peak memory 201676 kb
Host smart-e4b8d4cc-6545-467c-9de1-c20bc2b1de3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993652649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.993652649
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.791851872
Short name T388
Test name
Test status
Simulation time 4227208297 ps
CPU time 3.2 seconds
Started May 23 03:22:35 PM PDT 24
Finished May 23 03:22:40 PM PDT 24
Peak memory 201580 kb
Host smart-b1c00b74-3c0a-4d28-ae27-87afd294d692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791851872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.791851872
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.678400930
Short name T381
Test name
Test status
Simulation time 5943866984 ps
CPU time 14.7 seconds
Started May 23 03:22:36 PM PDT 24
Finished May 23 03:22:52 PM PDT 24
Peak memory 201632 kb
Host smart-2bac3148-a94a-46b9-bab5-941df0797431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678400930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.678400930
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.13250424
Short name T158
Test name
Test status
Simulation time 172983188418 ps
CPU time 403.42 seconds
Started May 23 03:22:38 PM PDT 24
Finished May 23 03:29:23 PM PDT 24
Peak memory 201900 kb
Host smart-9c7312d8-09e5-466f-8e2d-e8f0498e9874
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13250424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.13250424
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.705690668
Short name T19
Test name
Test status
Simulation time 102590634998 ps
CPU time 50.72 seconds
Started May 23 03:22:38 PM PDT 24
Finished May 23 03:23:30 PM PDT 24
Peak memory 210120 kb
Host smart-11ba2f0f-437b-488a-a4ea-3d4cc6e91c6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705690668 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.705690668
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3910564183
Short name T676
Test name
Test status
Simulation time 327230747 ps
CPU time 1.4 seconds
Started May 23 03:22:39 PM PDT 24
Finished May 23 03:22:42 PM PDT 24
Peak memory 201520 kb
Host smart-6235f6ed-f0ed-4ab6-8d74-d8fee8efee47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910564183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3910564183
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2190950113
Short name T695
Test name
Test status
Simulation time 167567724240 ps
CPU time 110.19 seconds
Started May 23 03:22:40 PM PDT 24
Finished May 23 03:24:31 PM PDT 24
Peak memory 201812 kb
Host smart-982fe3ce-39a4-4cd7-95c5-064ffd2197af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190950113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2190950113
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.255543226
Short name T216
Test name
Test status
Simulation time 494493592997 ps
CPU time 288.32 seconds
Started May 23 03:22:38 PM PDT 24
Finished May 23 03:27:28 PM PDT 24
Peak memory 201864 kb
Host smart-a838a60d-41da-41c7-a291-089b459152cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255543226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.255543226
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.724735845
Short name T425
Test name
Test status
Simulation time 319515477025 ps
CPU time 189.17 seconds
Started May 23 03:22:35 PM PDT 24
Finished May 23 03:25:45 PM PDT 24
Peak memory 201848 kb
Host smart-3b27a5e2-9c1d-4e16-b217-2f13586f9dd7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=724735845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrup
t_fixed.724735845
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3422634416
Short name T590
Test name
Test status
Simulation time 490028708781 ps
CPU time 968.29 seconds
Started May 23 03:22:37 PM PDT 24
Finished May 23 03:38:47 PM PDT 24
Peak memory 201860 kb
Host smart-1d1124de-a1c0-41c6-bd83-06cfb0028309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422634416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3422634416
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.4018589617
Short name T724
Test name
Test status
Simulation time 163367972444 ps
CPU time 348.82 seconds
Started May 23 03:22:37 PM PDT 24
Finished May 23 03:28:27 PM PDT 24
Peak memory 201832 kb
Host smart-4f77b3cc-259d-4a5f-9b83-270a9cd90380
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018589617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.4018589617
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1800267945
Short name T767
Test name
Test status
Simulation time 579676876020 ps
CPU time 674.91 seconds
Started May 23 03:22:38 PM PDT 24
Finished May 23 03:33:56 PM PDT 24
Peak memory 201816 kb
Host smart-e7b12c3a-b9b6-4131-8654-4b1fb23c9a39
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800267945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1800267945
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1124734164
Short name T609
Test name
Test status
Simulation time 121767630591 ps
CPU time 408.59 seconds
Started May 23 03:22:41 PM PDT 24
Finished May 23 03:29:31 PM PDT 24
Peak memory 202156 kb
Host smart-ae00f854-27e6-4eef-a2d7-74e89e7e3501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124734164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1124734164
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1856374990
Short name T365
Test name
Test status
Simulation time 32490496893 ps
CPU time 78.47 seconds
Started May 23 03:22:40 PM PDT 24
Finished May 23 03:23:59 PM PDT 24
Peak memory 201572 kb
Host smart-586ff1a6-235f-47b3-9a74-2f5069197854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856374990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1856374990
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.553806125
Short name T546
Test name
Test status
Simulation time 3523438447 ps
CPU time 2.8 seconds
Started May 23 03:22:39 PM PDT 24
Finished May 23 03:22:44 PM PDT 24
Peak memory 201580 kb
Host smart-f465b82e-eaf1-4105-acb8-91d9dc21ac4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553806125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.553806125
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1036813601
Short name T582
Test name
Test status
Simulation time 5919841479 ps
CPU time 3.97 seconds
Started May 23 03:22:34 PM PDT 24
Finished May 23 03:22:38 PM PDT 24
Peak memory 201660 kb
Host smart-05f055a2-0d8e-4c91-9d6a-9eab38142b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036813601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1036813601
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1889487777
Short name T684
Test name
Test status
Simulation time 10580621213 ps
CPU time 7.06 seconds
Started May 23 03:22:42 PM PDT 24
Finished May 23 03:22:51 PM PDT 24
Peak memory 201672 kb
Host smart-2a6bf8be-8731-442d-9d86-2aaf494cf02c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889487777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1889487777
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1086661131
Short name T585
Test name
Test status
Simulation time 504699017 ps
CPU time 0.72 seconds
Started May 23 03:22:42 PM PDT 24
Finished May 23 03:22:44 PM PDT 24
Peak memory 201532 kb
Host smart-aa3b4b00-610a-403e-ad7c-a5746f59d8f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086661131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1086661131
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2362870425
Short name T32
Test name
Test status
Simulation time 181251588856 ps
CPU time 90.8 seconds
Started May 23 03:22:39 PM PDT 24
Finished May 23 03:24:11 PM PDT 24
Peak memory 201848 kb
Host smart-8b83e285-682f-414e-b2e3-f7b488a7d680
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362870425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2362870425
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.36898119
Short name T433
Test name
Test status
Simulation time 323229696865 ps
CPU time 387.98 seconds
Started May 23 03:22:42 PM PDT 24
Finished May 23 03:29:11 PM PDT 24
Peak memory 201848 kb
Host smart-fbc5ed8b-4a85-4db5-887c-965989f01d2f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=36898119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt
_fixed.36898119
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1002868721
Short name T221
Test name
Test status
Simulation time 326412171181 ps
CPU time 183.73 seconds
Started May 23 03:22:36 PM PDT 24
Finished May 23 03:25:41 PM PDT 24
Peak memory 201924 kb
Host smart-94dc5bbf-999d-449d-881f-edd1b542ecfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002868721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1002868721
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3980543539
Short name T494
Test name
Test status
Simulation time 166392220390 ps
CPU time 119.86 seconds
Started May 23 03:22:41 PM PDT 24
Finished May 23 03:24:43 PM PDT 24
Peak memory 201808 kb
Host smart-bad6b64c-83a7-443d-af55-d8a829cd211b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980543539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3980543539
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1073903645
Short name T258
Test name
Test status
Simulation time 172249296484 ps
CPU time 372.25 seconds
Started May 23 03:22:42 PM PDT 24
Finished May 23 03:28:56 PM PDT 24
Peak memory 201924 kb
Host smart-3be3bb18-474f-47bb-be9e-c11bc0813d5d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073903645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1073903645
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2512143798
Short name T498
Test name
Test status
Simulation time 196567404293 ps
CPU time 486.97 seconds
Started May 23 03:22:39 PM PDT 24
Finished May 23 03:30:47 PM PDT 24
Peak memory 201844 kb
Host smart-c1882e47-577f-4606-bf9e-d12af7f0c386
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512143798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2512143798
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.1986212895
Short name T789
Test name
Test status
Simulation time 128615831267 ps
CPU time 560.83 seconds
Started May 23 03:22:42 PM PDT 24
Finished May 23 03:32:04 PM PDT 24
Peak memory 202160 kb
Host smart-88b9746b-3404-4774-b381-8d3268461b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986212895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1986212895
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.730386918
Short name T121
Test name
Test status
Simulation time 29644601915 ps
CPU time 68.56 seconds
Started May 23 03:22:42 PM PDT 24
Finished May 23 03:23:52 PM PDT 24
Peak memory 201680 kb
Host smart-10dd0ac2-a10b-41d2-9b99-4dc462a8eebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730386918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.730386918
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2347291812
Short name T29
Test name
Test status
Simulation time 4444401823 ps
CPU time 11.14 seconds
Started May 23 03:22:42 PM PDT 24
Finished May 23 03:22:55 PM PDT 24
Peak memory 201648 kb
Host smart-30662e69-66e2-40d1-989b-360e8228ad2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347291812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2347291812
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1823544806
Short name T749
Test name
Test status
Simulation time 5975862594 ps
CPU time 4.53 seconds
Started May 23 03:22:42 PM PDT 24
Finished May 23 03:22:48 PM PDT 24
Peak memory 201668 kb
Host smart-fc3ec4f9-9c54-400c-98d2-ea69557d8816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823544806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1823544806
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.82971890
Short name T34
Test name
Test status
Simulation time 110183109777 ps
CPU time 386.63 seconds
Started May 23 03:22:42 PM PDT 24
Finished May 23 03:29:10 PM PDT 24
Peak memory 211848 kb
Host smart-e0a5dbb7-f141-48ba-814a-2db54776d94b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82971890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.82971890
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2534634338
Short name T551
Test name
Test status
Simulation time 428937611471 ps
CPU time 308.98 seconds
Started May 23 03:22:41 PM PDT 24
Finished May 23 03:27:51 PM PDT 24
Peak memory 210448 kb
Host smart-78d12af8-5e70-40b8-8536-891044972cd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534634338 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2534634338
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.874557659
Short name T691
Test name
Test status
Simulation time 429937361 ps
CPU time 0.89 seconds
Started May 23 03:22:58 PM PDT 24
Finished May 23 03:22:59 PM PDT 24
Peak memory 201568 kb
Host smart-db1ea32f-7032-4125-844d-a7f9970f2e91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874557659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.874557659
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3019372959
Short name T347
Test name
Test status
Simulation time 520611269477 ps
CPU time 1102.81 seconds
Started May 23 03:22:35 PM PDT 24
Finished May 23 03:40:59 PM PDT 24
Peak memory 201844 kb
Host smart-d32b0d73-f45c-4fd5-ba40-c9348b53a8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019372959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3019372959
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3482857749
Short name T350
Test name
Test status
Simulation time 330640685936 ps
CPU time 760.34 seconds
Started May 23 03:22:42 PM PDT 24
Finished May 23 03:35:24 PM PDT 24
Peak memory 201856 kb
Host smart-fed25da6-03fc-4025-8103-1e2cc5d4f9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482857749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3482857749
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2040317971
Short name T723
Test name
Test status
Simulation time 331876511620 ps
CPU time 210.93 seconds
Started May 23 03:22:40 PM PDT 24
Finished May 23 03:26:13 PM PDT 24
Peak memory 201832 kb
Host smart-7419b915-ce3b-4307-a36e-fad5ffbf94c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040317971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2040317971
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3332724622
Short name T610
Test name
Test status
Simulation time 168856491759 ps
CPU time 64.41 seconds
Started May 23 03:22:41 PM PDT 24
Finished May 23 03:23:46 PM PDT 24
Peak memory 201816 kb
Host smart-99c41444-f303-46e4-b3ff-42c801222713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332724622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3332724622
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.48629217
Short name T460
Test name
Test status
Simulation time 321363448691 ps
CPU time 46.96 seconds
Started May 23 03:22:41 PM PDT 24
Finished May 23 03:23:29 PM PDT 24
Peak memory 201832 kb
Host smart-21329662-99ab-4683-bbd4-21f332992464
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=48629217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixed
.48629217
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.4116391110
Short name T740
Test name
Test status
Simulation time 176935425401 ps
CPU time 388.29 seconds
Started May 23 03:22:42 PM PDT 24
Finished May 23 03:29:11 PM PDT 24
Peak memory 201844 kb
Host smart-d4b842d8-0b3e-4c8c-b8a3-f48957ac0b43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116391110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.4116391110
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1400097800
Short name T516
Test name
Test status
Simulation time 205966820383 ps
CPU time 216.5 seconds
Started May 23 03:22:38 PM PDT 24
Finished May 23 03:26:16 PM PDT 24
Peak memory 201860 kb
Host smart-6005fa6a-5117-4da5-89b8-4dee5abe9f5e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400097800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1400097800
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1094593502
Short name T364
Test name
Test status
Simulation time 132333146223 ps
CPU time 698.91 seconds
Started May 23 03:22:38 PM PDT 24
Finished May 23 03:34:20 PM PDT 24
Peak memory 202208 kb
Host smart-491df636-e729-48bb-9e6e-ac7c1deb7a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094593502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1094593502
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1932682378
Short name T599
Test name
Test status
Simulation time 27033634150 ps
CPU time 8.13 seconds
Started May 23 03:22:38 PM PDT 24
Finished May 23 03:22:49 PM PDT 24
Peak memory 201656 kb
Host smart-d17ce676-7ce0-4da0-bcc7-057fafa95091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932682378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1932682378
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2504233993
Short name T529
Test name
Test status
Simulation time 5116555708 ps
CPU time 2.14 seconds
Started May 23 03:22:38 PM PDT 24
Finished May 23 03:22:42 PM PDT 24
Peak memory 201688 kb
Host smart-38fd8793-42b4-4d3c-9d6c-7da46bbdc172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504233993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2504233993
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3089151194
Short name T386
Test name
Test status
Simulation time 6175958000 ps
CPU time 3.1 seconds
Started May 23 03:22:41 PM PDT 24
Finished May 23 03:22:46 PM PDT 24
Peak memory 201664 kb
Host smart-fa17fe09-698d-4ba4-996e-098919fa6426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089151194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3089151194
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1865201584
Short name T291
Test name
Test status
Simulation time 3904180818594 ps
CPU time 3910.77 seconds
Started May 23 03:22:57 PM PDT 24
Finished May 23 04:28:09 PM PDT 24
Peak memory 212936 kb
Host smart-b9e41e99-2150-48e4-96ff-88d5c3b2979f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865201584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1865201584
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1564544879
Short name T65
Test name
Test status
Simulation time 122395594173 ps
CPU time 216.92 seconds
Started May 23 03:22:59 PM PDT 24
Finished May 23 03:26:37 PM PDT 24
Peak memory 213308 kb
Host smart-ac34af00-4ea7-4dd5-8a6e-4413558a813b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564544879 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1564544879
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.151816991
Short name T375
Test name
Test status
Simulation time 516332948 ps
CPU time 1.28 seconds
Started May 23 03:23:02 PM PDT 24
Finished May 23 03:23:05 PM PDT 24
Peak memory 201556 kb
Host smart-c7605902-6735-4609-84ef-1e14e3e64b72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151816991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.151816991
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3893824808
Short name T672
Test name
Test status
Simulation time 187790253320 ps
CPU time 114.3 seconds
Started May 23 03:22:59 PM PDT 24
Finished May 23 03:24:54 PM PDT 24
Peak memory 201840 kb
Host smart-50e4aaa6-3e94-4feb-8011-4333c99b3700
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893824808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3893824808
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2034295009
Short name T525
Test name
Test status
Simulation time 165473962046 ps
CPU time 31.64 seconds
Started May 23 03:22:57 PM PDT 24
Finished May 23 03:23:29 PM PDT 24
Peak memory 201852 kb
Host smart-e97415f7-9e2f-4075-8966-276186a5d2e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034295009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2034295009
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1805877972
Short name T521
Test name
Test status
Simulation time 326542253561 ps
CPU time 773.4 seconds
Started May 23 03:22:59 PM PDT 24
Finished May 23 03:35:54 PM PDT 24
Peak memory 201824 kb
Host smart-0bd4c9e0-1562-4866-847c-8a69d284f050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805877972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1805877972
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2411019506
Short name T370
Test name
Test status
Simulation time 494068248988 ps
CPU time 464.54 seconds
Started May 23 03:22:57 PM PDT 24
Finished May 23 03:30:42 PM PDT 24
Peak memory 201800 kb
Host smart-9e58f503-5420-4bf9-88f8-ec5043c11242
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411019506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2411019506
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3366841382
Short name T752
Test name
Test status
Simulation time 93452248756 ps
CPU time 345.68 seconds
Started May 23 03:22:56 PM PDT 24
Finished May 23 03:28:42 PM PDT 24
Peak memory 202160 kb
Host smart-b1c9f345-2675-4cbd-9db5-67b2bd01c3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366841382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3366841382
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.4202292898
Short name T205
Test name
Test status
Simulation time 42195649082 ps
CPU time 25.79 seconds
Started May 23 03:22:57 PM PDT 24
Finished May 23 03:23:24 PM PDT 24
Peak memory 201660 kb
Host smart-23ab356e-0d6b-4323-9ae4-9e596c310419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202292898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.4202292898
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3104482529
Short name T190
Test name
Test status
Simulation time 4638418576 ps
CPU time 3.49 seconds
Started May 23 03:22:56 PM PDT 24
Finished May 23 03:23:00 PM PDT 24
Peak memory 201620 kb
Host smart-64b51bd2-7f92-4741-9915-d2a9a6751db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104482529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3104482529
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2624649582
Short name T395
Test name
Test status
Simulation time 5976280936 ps
CPU time 16.01 seconds
Started May 23 03:23:02 PM PDT 24
Finished May 23 03:23:19 PM PDT 24
Peak memory 201688 kb
Host smart-9a340a12-667f-486a-a820-6de0ca27cd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624649582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2624649582
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1042770023
Short name T304
Test name
Test status
Simulation time 671749702116 ps
CPU time 457.05 seconds
Started May 23 03:22:56 PM PDT 24
Finished May 23 03:30:34 PM PDT 24
Peak memory 201852 kb
Host smart-36db26e4-f53e-470a-b745-d1ac6f25b8cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042770023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1042770023
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3038619781
Short name T40
Test name
Test status
Simulation time 358100968446 ps
CPU time 205.27 seconds
Started May 23 03:22:56 PM PDT 24
Finished May 23 03:26:22 PM PDT 24
Peak memory 202020 kb
Host smart-4b5f00a8-53d7-4c9b-b741-f252670f9855
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038619781 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3038619781
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2087742442
Short name T689
Test name
Test status
Simulation time 473638887 ps
CPU time 1.68 seconds
Started May 23 03:23:13 PM PDT 24
Finished May 23 03:23:15 PM PDT 24
Peak memory 201556 kb
Host smart-cbc35ff1-bbe9-4a1e-9e18-c9997d4580a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087742442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2087742442
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3434098861
Short name T349
Test name
Test status
Simulation time 330749896814 ps
CPU time 351.14 seconds
Started May 23 03:23:11 PM PDT 24
Finished May 23 03:29:04 PM PDT 24
Peak memory 201832 kb
Host smart-c81fe2ab-9b3f-491f-8eb2-fd3c14c940fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434098861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3434098861
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3845055610
Short name T239
Test name
Test status
Simulation time 163684461871 ps
CPU time 392.23 seconds
Started May 23 03:23:19 PM PDT 24
Finished May 23 03:29:52 PM PDT 24
Peak memory 201932 kb
Host smart-31fbca0f-2f40-4d2c-9119-016adbf16189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845055610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3845055610
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.911783105
Short name T598
Test name
Test status
Simulation time 170269710551 ps
CPU time 212.76 seconds
Started May 23 03:23:11 PM PDT 24
Finished May 23 03:26:44 PM PDT 24
Peak memory 201852 kb
Host smart-825c4c8c-21dd-4e0c-b465-f09d3a26cb46
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=911783105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.911783105
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3188300537
Short name T577
Test name
Test status
Simulation time 325490937277 ps
CPU time 716.76 seconds
Started May 23 03:22:56 PM PDT 24
Finished May 23 03:34:54 PM PDT 24
Peak memory 201896 kb
Host smart-140dfb84-f4ca-48c8-a5c5-76946b484aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188300537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3188300537
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1760902937
Short name T189
Test name
Test status
Simulation time 331653065874 ps
CPU time 376.56 seconds
Started May 23 03:23:11 PM PDT 24
Finished May 23 03:29:28 PM PDT 24
Peak memory 201828 kb
Host smart-51ffddc8-d013-4584-aa1e-6473196c6dca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760902937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1760902937
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.997192649
Short name T331
Test name
Test status
Simulation time 370539836865 ps
CPU time 225.44 seconds
Started May 23 03:23:12 PM PDT 24
Finished May 23 03:26:59 PM PDT 24
Peak memory 201916 kb
Host smart-27162388-e160-4b43-8efd-2f7eb18c9f81
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997192649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.997192649
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3609359109
Short name T793
Test name
Test status
Simulation time 606497585731 ps
CPU time 338.93 seconds
Started May 23 03:23:13 PM PDT 24
Finished May 23 03:28:53 PM PDT 24
Peak memory 201820 kb
Host smart-12604842-fe13-459d-9aa4-ff735db7a09f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609359109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3609359109
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2225733977
Short name T648
Test name
Test status
Simulation time 73962836315 ps
CPU time 271.63 seconds
Started May 23 03:23:12 PM PDT 24
Finished May 23 03:27:44 PM PDT 24
Peak memory 202216 kb
Host smart-840bdc7b-4349-463b-945c-ac0e06b500b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225733977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2225733977
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3679325074
Short name T373
Test name
Test status
Simulation time 38385149181 ps
CPU time 91.12 seconds
Started May 23 03:23:12 PM PDT 24
Finished May 23 03:24:44 PM PDT 24
Peak memory 201688 kb
Host smart-352e5824-7dc4-4678-ad56-790e6c9d19b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679325074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3679325074
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2282024687
Short name T531
Test name
Test status
Simulation time 3119542260 ps
CPU time 2.47 seconds
Started May 23 03:23:17 PM PDT 24
Finished May 23 03:23:21 PM PDT 24
Peak memory 201620 kb
Host smart-32b22c2c-d52b-4b19-b90a-5a2a2f1d19e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282024687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2282024687
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2701543536
Short name T442
Test name
Test status
Simulation time 5755177664 ps
CPU time 14.44 seconds
Started May 23 03:22:54 PM PDT 24
Finished May 23 03:23:09 PM PDT 24
Peak memory 201656 kb
Host smart-8c7b2e3f-a509-43b2-bf79-2453f3332284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701543536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2701543536
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3640185213
Short name T699
Test name
Test status
Simulation time 602064304452 ps
CPU time 1504.7 seconds
Started May 23 03:23:10 PM PDT 24
Finished May 23 03:48:15 PM PDT 24
Peak memory 202232 kb
Host smart-fe6ccd83-c3d7-4f84-bea8-7acd7c872833
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640185213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3640185213
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2816131776
Short name T344
Test name
Test status
Simulation time 85618248388 ps
CPU time 157.66 seconds
Started May 23 03:23:17 PM PDT 24
Finished May 23 03:25:56 PM PDT 24
Peak memory 211504 kb
Host smart-20557a04-3ca9-4068-ad32-dab7e9e72598
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816131776 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.2816131776
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2176734943
Short name T766
Test name
Test status
Simulation time 524358396 ps
CPU time 0.89 seconds
Started May 23 03:21:28 PM PDT 24
Finished May 23 03:21:33 PM PDT 24
Peak memory 201540 kb
Host smart-6cff8f4e-f3d4-4f9a-9921-249aa0fd9326
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176734943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2176734943
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1300384367
Short name T111
Test name
Test status
Simulation time 332296073876 ps
CPU time 358.45 seconds
Started May 23 03:21:23 PM PDT 24
Finished May 23 03:27:27 PM PDT 24
Peak memory 201848 kb
Host smart-2f10a071-c206-4d24-8f81-f6b4835e3848
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300384367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1300384367
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1361487218
Short name T764
Test name
Test status
Simulation time 366571790507 ps
CPU time 226.96 seconds
Started May 23 03:21:28 PM PDT 24
Finished May 23 03:25:19 PM PDT 24
Peak memory 201856 kb
Host smart-85988382-d2bf-4f4f-8a9c-f38d85555271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361487218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1361487218
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.4179520642
Short name T792
Test name
Test status
Simulation time 323562723640 ps
CPU time 135.52 seconds
Started May 23 03:21:28 PM PDT 24
Finished May 23 03:23:47 PM PDT 24
Peak memory 201904 kb
Host smart-32202cbf-2d46-4d9d-a305-f346cf11e284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179520642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.4179520642
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.4103598561
Short name T616
Test name
Test status
Simulation time 327453760448 ps
CPU time 716.49 seconds
Started May 23 03:21:29 PM PDT 24
Finished May 23 03:33:30 PM PDT 24
Peak memory 201812 kb
Host smart-fadb2e00-32f4-49fb-9ace-530d01616716
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103598561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.4103598561
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3649340361
Short name T743
Test name
Test status
Simulation time 325022603232 ps
CPU time 806.59 seconds
Started May 23 03:21:30 PM PDT 24
Finished May 23 03:35:00 PM PDT 24
Peak memory 201868 kb
Host smart-32935299-f657-4c07-a384-e211f6f88af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649340361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3649340361
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3270536025
Short name T748
Test name
Test status
Simulation time 164319015323 ps
CPU time 47.15 seconds
Started May 23 03:21:27 PM PDT 24
Finished May 23 03:22:19 PM PDT 24
Peak memory 201824 kb
Host smart-5973f513-22cb-4300-86b0-7bd5c37cd021
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270536025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3270536025
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2705867690
Short name T124
Test name
Test status
Simulation time 194172006497 ps
CPU time 117.76 seconds
Started May 23 03:21:27 PM PDT 24
Finished May 23 03:23:29 PM PDT 24
Peak memory 201912 kb
Host smart-03544ffb-ef46-4dea-83ec-7cc72d083374
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705867690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2705867690
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3890875193
Short name T705
Test name
Test status
Simulation time 606680653390 ps
CPU time 1334.98 seconds
Started May 23 03:21:30 PM PDT 24
Finished May 23 03:43:49 PM PDT 24
Peak memory 201892 kb
Host smart-339a74a4-d53b-4a7f-9e31-0763141a5a81
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890875193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.3890875193
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.4214782573
Short name T513
Test name
Test status
Simulation time 126170828999 ps
CPU time 409.95 seconds
Started May 23 03:21:31 PM PDT 24
Finished May 23 03:28:24 PM PDT 24
Peak memory 202156 kb
Host smart-52145f23-fe9a-4ccf-8c04-9d651eb0565b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214782573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.4214782573
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3378893000
Short name T502
Test name
Test status
Simulation time 29308666634 ps
CPU time 18.54 seconds
Started May 23 03:21:31 PM PDT 24
Finished May 23 03:21:53 PM PDT 24
Peak memory 201672 kb
Host smart-d6253d65-d9df-4f6f-8168-5f6aafe5a053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378893000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3378893000
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2772796615
Short name T715
Test name
Test status
Simulation time 3793087407 ps
CPU time 1.68 seconds
Started May 23 03:21:31 PM PDT 24
Finished May 23 03:21:36 PM PDT 24
Peak memory 201604 kb
Host smart-6888a2eb-7d4c-4d85-8737-d394dbcd71c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772796615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2772796615
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3220748105
Short name T83
Test name
Test status
Simulation time 8024301670 ps
CPU time 6.65 seconds
Started May 23 03:21:23 PM PDT 24
Finished May 23 03:21:35 PM PDT 24
Peak memory 218476 kb
Host smart-97fd10d9-9f8a-4f04-b450-ac03240f926c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220748105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3220748105
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3588623097
Short name T406
Test name
Test status
Simulation time 5870663797 ps
CPU time 14.24 seconds
Started May 23 03:21:27 PM PDT 24
Finished May 23 03:21:46 PM PDT 24
Peak memory 201660 kb
Host smart-c4bd4e1b-dcf4-4aba-b4f0-83acb3625799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588623097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3588623097
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.639302534
Short name T553
Test name
Test status
Simulation time 321184882772 ps
CPU time 1112.18 seconds
Started May 23 03:21:28 PM PDT 24
Finished May 23 03:40:04 PM PDT 24
Peak memory 202188 kb
Host smart-70830c13-13d6-4911-acdb-bab7760fcd0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639302534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.639302534
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1638955409
Short name T750
Test name
Test status
Simulation time 61954649800 ps
CPU time 154.67 seconds
Started May 23 03:21:27 PM PDT 24
Finished May 23 03:24:06 PM PDT 24
Peak memory 218412 kb
Host smart-98797f07-2ef1-4db1-9441-a81daab5ea3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638955409 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1638955409
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.529654300
Short name T458
Test name
Test status
Simulation time 326207825 ps
CPU time 0.79 seconds
Started May 23 03:23:26 PM PDT 24
Finished May 23 03:23:28 PM PDT 24
Peak memory 201460 kb
Host smart-29c3142d-ddac-4fc1-8fc1-cd5ff70a2016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529654300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.529654300
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3244144176
Short name T270
Test name
Test status
Simulation time 496265493752 ps
CPU time 762.48 seconds
Started May 23 03:23:09 PM PDT 24
Finished May 23 03:35:52 PM PDT 24
Peak memory 201892 kb
Host smart-e6ea4ffb-d9a5-481b-ba9c-655ffa5047c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244144176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3244144176
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2114869218
Short name T690
Test name
Test status
Simulation time 163236041430 ps
CPU time 400.48 seconds
Started May 23 03:23:11 PM PDT 24
Finished May 23 03:29:52 PM PDT 24
Peak memory 201852 kb
Host smart-c321feb3-7841-46c0-9a8d-8cee4cf9c659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114869218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2114869218
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2074441454
Short name T318
Test name
Test status
Simulation time 491956565913 ps
CPU time 333.84 seconds
Started May 23 03:23:09 PM PDT 24
Finished May 23 03:28:44 PM PDT 24
Peak memory 201848 kb
Host smart-cc64940b-367d-48f2-a477-37f64e63379d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074441454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2074441454
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3206361079
Short name T374
Test name
Test status
Simulation time 165513707781 ps
CPU time 405.7 seconds
Started May 23 03:23:12 PM PDT 24
Finished May 23 03:29:59 PM PDT 24
Peak memory 201844 kb
Host smart-904b385a-5a79-4df6-89ed-2dcd24ce3b22
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206361079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3206361079
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.4081298671
Short name T728
Test name
Test status
Simulation time 489711133801 ps
CPU time 292.58 seconds
Started May 23 03:23:18 PM PDT 24
Finished May 23 03:28:11 PM PDT 24
Peak memory 201920 kb
Host smart-91641cf5-7766-429d-b0c8-63768f11c7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081298671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.4081298671
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1406522798
Short name T677
Test name
Test status
Simulation time 492459029687 ps
CPU time 1118.94 seconds
Started May 23 03:23:12 PM PDT 24
Finished May 23 03:41:52 PM PDT 24
Peak memory 201808 kb
Host smart-c67d4427-023b-46ac-a21b-5785b05f839d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406522798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1406522798
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.1989851718
Short name T164
Test name
Test status
Simulation time 354027887353 ps
CPU time 418.92 seconds
Started May 23 03:23:10 PM PDT 24
Finished May 23 03:30:09 PM PDT 24
Peak memory 201900 kb
Host smart-7e867f97-e155-48b2-b38e-b303a523569d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989851718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.1989851718
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2224096701
Short name T103
Test name
Test status
Simulation time 196476071546 ps
CPU time 108.56 seconds
Started May 23 03:23:12 PM PDT 24
Finished May 23 03:25:01 PM PDT 24
Peak memory 201820 kb
Host smart-187a6fa1-cbf9-48d7-b1a5-f34ded671bf1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224096701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2224096701
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3088580999
Short name T357
Test name
Test status
Simulation time 119545191490 ps
CPU time 637.31 seconds
Started May 23 03:23:11 PM PDT 24
Finished May 23 03:33:49 PM PDT 24
Peak memory 202076 kb
Host smart-17763c53-5ef2-46d0-94a9-9b61347ab55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088580999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3088580999
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1854899025
Short name T774
Test name
Test status
Simulation time 32563557508 ps
CPU time 19.48 seconds
Started May 23 03:23:11 PM PDT 24
Finished May 23 03:23:32 PM PDT 24
Peak memory 201644 kb
Host smart-ea264b75-f138-4500-9c00-f88528cffa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854899025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1854899025
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1574138018
Short name T681
Test name
Test status
Simulation time 5149113432 ps
CPU time 12.02 seconds
Started May 23 03:23:11 PM PDT 24
Finished May 23 03:23:24 PM PDT 24
Peak memory 201668 kb
Host smart-1c601435-3c8a-46a4-9c39-ed710086b389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574138018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1574138018
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3928912881
Short name T581
Test name
Test status
Simulation time 6115713477 ps
CPU time 5.21 seconds
Started May 23 03:23:11 PM PDT 24
Finished May 23 03:23:18 PM PDT 24
Peak memory 201680 kb
Host smart-e0899f4d-d974-4420-a39e-ab801be98033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928912881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3928912881
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1915940257
Short name T286
Test name
Test status
Simulation time 575788869563 ps
CPU time 1313.23 seconds
Started May 23 03:23:29 PM PDT 24
Finished May 23 03:45:25 PM PDT 24
Peak memory 201764 kb
Host smart-946af8eb-4dba-48ec-bd4c-b34df3c5ac15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915940257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1915940257
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.823430252
Short name T301
Test name
Test status
Simulation time 114644191077 ps
CPU time 141.18 seconds
Started May 23 03:23:10 PM PDT 24
Finished May 23 03:25:32 PM PDT 24
Peak memory 201988 kb
Host smart-d6a5803a-f869-4a96-badc-f3cd2fcc4e1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823430252 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.823430252
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1332521136
Short name T775
Test name
Test status
Simulation time 477702541 ps
CPU time 1.2 seconds
Started May 23 03:23:29 PM PDT 24
Finished May 23 03:23:32 PM PDT 24
Peak memory 201468 kb
Host smart-38cd9540-9b01-419b-a666-c772bc405e1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332521136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1332521136
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2761060456
Short name T193
Test name
Test status
Simulation time 173966980398 ps
CPU time 38.99 seconds
Started May 23 03:23:30 PM PDT 24
Finished May 23 03:24:11 PM PDT 24
Peak memory 201932 kb
Host smart-65393c41-c0a9-4b5b-ba07-89081a690ab5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761060456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2761060456
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2520875665
Short name T319
Test name
Test status
Simulation time 352638032337 ps
CPU time 881.37 seconds
Started May 23 03:23:25 PM PDT 24
Finished May 23 03:38:08 PM PDT 24
Peak memory 201832 kb
Host smart-87c77e03-6c5f-46c1-8780-739d987769e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520875665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2520875665
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2650438977
Short name T558
Test name
Test status
Simulation time 161968014788 ps
CPU time 109.79 seconds
Started May 23 03:23:31 PM PDT 24
Finished May 23 03:25:23 PM PDT 24
Peak memory 201848 kb
Host smart-8eefa425-e405-4160-8315-e94b333ace0a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650438977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2650438977
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.890777044
Short name T110
Test name
Test status
Simulation time 167008615264 ps
CPU time 201.27 seconds
Started May 23 03:23:28 PM PDT 24
Finished May 23 03:26:51 PM PDT 24
Peak memory 201904 kb
Host smart-9e5f0d84-edbc-4914-9da9-4ee3c12f6bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890777044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.890777044
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.853785696
Short name T475
Test name
Test status
Simulation time 483033931167 ps
CPU time 564.89 seconds
Started May 23 03:23:27 PM PDT 24
Finished May 23 03:32:54 PM PDT 24
Peak memory 201852 kb
Host smart-0296b222-1baa-4c8a-8fec-ee1a2ba2152f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=853785696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixe
d.853785696
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1470395554
Short name T625
Test name
Test status
Simulation time 348464380650 ps
CPU time 134.95 seconds
Started May 23 03:23:26 PM PDT 24
Finished May 23 03:25:43 PM PDT 24
Peak memory 201840 kb
Host smart-965cfafe-bd62-4219-929c-4a8fcafcae76
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470395554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1470395554
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.229365346
Short name T446
Test name
Test status
Simulation time 394879955354 ps
CPU time 192.15 seconds
Started May 23 03:23:28 PM PDT 24
Finished May 23 03:26:41 PM PDT 24
Peak memory 201844 kb
Host smart-0cecf1c9-a1c4-4ddb-b057-9903592c70eb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229365346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.229365346
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2137008853
Short name T548
Test name
Test status
Simulation time 106022617250 ps
CPU time 351.2 seconds
Started May 23 03:23:26 PM PDT 24
Finished May 23 03:29:19 PM PDT 24
Peak memory 202180 kb
Host smart-6e66bc59-3e5a-48f2-ab81-92933a1a4fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137008853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2137008853
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.24998749
Short name T431
Test name
Test status
Simulation time 31138737853 ps
CPU time 16.77 seconds
Started May 23 03:23:27 PM PDT 24
Finished May 23 03:23:46 PM PDT 24
Peak memory 201616 kb
Host smart-09df469c-ebc0-46ae-98ab-2bcfc752a328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24998749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.24998749
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1278177312
Short name T459
Test name
Test status
Simulation time 4005178592 ps
CPU time 10.66 seconds
Started May 23 03:23:26 PM PDT 24
Finished May 23 03:23:38 PM PDT 24
Peak memory 201592 kb
Host smart-9f3ea53c-714b-4ac8-b958-afef3e6f4294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278177312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1278177312
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3899742300
Short name T495
Test name
Test status
Simulation time 5626190014 ps
CPU time 9.13 seconds
Started May 23 03:23:27 PM PDT 24
Finished May 23 03:23:37 PM PDT 24
Peak memory 201724 kb
Host smart-d38312d0-dda5-4852-86c8-6286af76d7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899742300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3899742300
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1358071030
Short name T242
Test name
Test status
Simulation time 443316638319 ps
CPU time 585.18 seconds
Started May 23 03:23:29 PM PDT 24
Finished May 23 03:33:16 PM PDT 24
Peak memory 202200 kb
Host smart-21cde91b-b697-4f0d-884f-9b47a887e89f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358071030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1358071030
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2256155243
Short name T98
Test name
Test status
Simulation time 150008917082 ps
CPU time 130.07 seconds
Started May 23 03:23:28 PM PDT 24
Finished May 23 03:25:40 PM PDT 24
Peak memory 210468 kb
Host smart-d7c97186-4294-4750-b84e-e73f45829abb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256155243 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2256155243
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.331211567
Short name T506
Test name
Test status
Simulation time 462963332 ps
CPU time 1.69 seconds
Started May 23 03:23:42 PM PDT 24
Finished May 23 03:23:45 PM PDT 24
Peak memory 201524 kb
Host smart-b106488d-6784-43ff-9c99-056f2b22dbbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331211567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.331211567
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2809920912
Short name T637
Test name
Test status
Simulation time 326223813854 ps
CPU time 84.96 seconds
Started May 23 03:23:26 PM PDT 24
Finished May 23 03:24:53 PM PDT 24
Peak memory 201848 kb
Host smart-98e2e64e-1df8-4472-9d93-94c6e9947c08
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809920912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2809920912
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1762007626
Short name T119
Test name
Test status
Simulation time 553598753695 ps
CPU time 378.14 seconds
Started May 23 03:23:28 PM PDT 24
Finished May 23 03:29:47 PM PDT 24
Peak memory 201844 kb
Host smart-0e44d928-7aff-4b45-801f-95a1b408204b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762007626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1762007626
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2920321403
Short name T152
Test name
Test status
Simulation time 493179104942 ps
CPU time 1225 seconds
Started May 23 03:23:28 PM PDT 24
Finished May 23 03:43:55 PM PDT 24
Peak memory 201904 kb
Host smart-72fa9332-9475-4444-b1a6-e04c4da1d2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920321403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2920321403
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2959132433
Short name T202
Test name
Test status
Simulation time 324135689085 ps
CPU time 133.1 seconds
Started May 23 03:23:30 PM PDT 24
Finished May 23 03:25:45 PM PDT 24
Peak memory 201864 kb
Host smart-6cd9e524-5b11-4817-bbcf-fb0c8a4f6a84
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959132433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2959132433
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1140832905
Short name T195
Test name
Test status
Simulation time 491054901001 ps
CPU time 290.37 seconds
Started May 23 03:23:32 PM PDT 24
Finished May 23 03:28:24 PM PDT 24
Peak memory 201840 kb
Host smart-1b21346c-9629-4a5b-9533-8ac4818f1ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140832905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1140832905
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1799794554
Short name T561
Test name
Test status
Simulation time 492359552432 ps
CPU time 532.29 seconds
Started May 23 03:23:26 PM PDT 24
Finished May 23 03:32:20 PM PDT 24
Peak memory 201800 kb
Host smart-87d1e066-c663-42fc-9452-7ef376dbad72
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799794554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1799794554
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1804896128
Short name T658
Test name
Test status
Simulation time 408590427533 ps
CPU time 450.03 seconds
Started May 23 03:23:28 PM PDT 24
Finished May 23 03:30:59 PM PDT 24
Peak memory 201840 kb
Host smart-fc97c13e-d000-4f62-b8e5-ba92c10d9c9a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804896128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1804896128
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.2505871986
Short name T763
Test name
Test status
Simulation time 35282174226 ps
CPU time 21.66 seconds
Started May 23 03:23:29 PM PDT 24
Finished May 23 03:23:52 PM PDT 24
Peak memory 201644 kb
Host smart-eb26e135-5cc1-4633-bcb1-a164d8658a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505871986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.2505871986
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.4104592010
Short name T781
Test name
Test status
Simulation time 3005169234 ps
CPU time 2.44 seconds
Started May 23 03:23:26 PM PDT 24
Finished May 23 03:23:29 PM PDT 24
Peak memory 201604 kb
Host smart-1d5e52e2-8a72-4096-a3f3-b1c624f6ee4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104592010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.4104592010
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3592970864
Short name T613
Test name
Test status
Simulation time 6134330382 ps
CPU time 15.6 seconds
Started May 23 03:23:27 PM PDT 24
Finished May 23 03:23:45 PM PDT 24
Peak memory 201676 kb
Host smart-a43273f0-7ad4-414b-b73d-9366ccd5de66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592970864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3592970864
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1902432202
Short name T721
Test name
Test status
Simulation time 168339535732 ps
CPU time 141.19 seconds
Started May 23 03:23:45 PM PDT 24
Finished May 23 03:26:08 PM PDT 24
Peak memory 201836 kb
Host smart-f080e405-d9b3-48e9-8b8e-6d8852302782
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902432202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1902432202
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2959895398
Short name T434
Test name
Test status
Simulation time 14779249838 ps
CPU time 37.26 seconds
Started May 23 03:23:43 PM PDT 24
Finished May 23 03:24:22 PM PDT 24
Peak memory 210472 kb
Host smart-c72f4ce5-3cff-4ae6-9884-ccd653444e80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959895398 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2959895398
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.626520836
Short name T206
Test name
Test status
Simulation time 532221695 ps
CPU time 1.8 seconds
Started May 23 03:23:42 PM PDT 24
Finished May 23 03:23:46 PM PDT 24
Peak memory 201472 kb
Host smart-791a37b3-ad3f-4d5f-8264-9a6591ce6374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626520836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.626520836
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1922269185
Short name T114
Test name
Test status
Simulation time 342908803204 ps
CPU time 381.3 seconds
Started May 23 03:23:46 PM PDT 24
Finished May 23 03:30:09 PM PDT 24
Peak memory 201880 kb
Host smart-13294093-5b3b-456e-bfa3-e935bb6cb07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922269185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1922269185
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1979833890
Short name T777
Test name
Test status
Simulation time 325283363510 ps
CPU time 93.26 seconds
Started May 23 03:23:43 PM PDT 24
Finished May 23 03:25:19 PM PDT 24
Peak memory 201796 kb
Host smart-04783bc0-0835-42ce-9596-1ab4ef402584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979833890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1979833890
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3977478498
Short name T384
Test name
Test status
Simulation time 330643066571 ps
CPU time 791.27 seconds
Started May 23 03:23:42 PM PDT 24
Finished May 23 03:36:55 PM PDT 24
Peak memory 201852 kb
Host smart-d8ab145e-e7bd-44ff-9967-2f6aead421bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977478498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3977478498
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.11635634
Short name T165
Test name
Test status
Simulation time 322653951142 ps
CPU time 754.97 seconds
Started May 23 03:23:44 PM PDT 24
Finished May 23 03:36:21 PM PDT 24
Peak memory 201816 kb
Host smart-dd10f360-14b8-40e2-b527-b684da6701cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11635634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.11635634
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2043667696
Short name T101
Test name
Test status
Simulation time 500098590637 ps
CPU time 176.67 seconds
Started May 23 03:23:47 PM PDT 24
Finished May 23 03:26:45 PM PDT 24
Peak memory 201812 kb
Host smart-28ee7b14-3e66-4b23-9b42-e130ab094ee1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043667696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2043667696
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1041252654
Short name T770
Test name
Test status
Simulation time 601760559312 ps
CPU time 722.11 seconds
Started May 23 03:23:42 PM PDT 24
Finished May 23 03:35:46 PM PDT 24
Peak memory 201884 kb
Host smart-6faa55aa-1368-40af-9e11-c3936b81ec76
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041252654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1041252654
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3498382102
Short name T102
Test name
Test status
Simulation time 600828497574 ps
CPU time 1479.67 seconds
Started May 23 03:23:45 PM PDT 24
Finished May 23 03:48:27 PM PDT 24
Peak memory 201832 kb
Host smart-16690018-13a4-4e3d-a3c1-077af6caa63b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498382102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3498382102
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2531052026
Short name T415
Test name
Test status
Simulation time 76452160152 ps
CPU time 428.83 seconds
Started May 23 03:23:45 PM PDT 24
Finished May 23 03:30:56 PM PDT 24
Peak memory 202164 kb
Host smart-5e76bd9f-83fc-4797-ba5a-00753882dc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531052026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2531052026
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1378339525
Short name T597
Test name
Test status
Simulation time 34429386102 ps
CPU time 12.92 seconds
Started May 23 03:23:43 PM PDT 24
Finished May 23 03:23:58 PM PDT 24
Peak memory 201632 kb
Host smart-0a4d7b7a-4ced-4867-8e1a-61c32f8356e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378339525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1378339525
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.4253290590
Short name T523
Test name
Test status
Simulation time 4578217919 ps
CPU time 9.64 seconds
Started May 23 03:23:46 PM PDT 24
Finished May 23 03:23:58 PM PDT 24
Peak memory 201644 kb
Host smart-3ab25e36-632c-4415-a27b-9f8c79c48054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253290590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.4253290590
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.4229610333
Short name T396
Test name
Test status
Simulation time 5569890850 ps
CPU time 13.36 seconds
Started May 23 03:23:43 PM PDT 24
Finished May 23 03:23:59 PM PDT 24
Peak memory 201652 kb
Host smart-b131da61-8ca1-4844-930a-f0bfd73f8231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229610333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.4229610333
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3136889707
Short name T738
Test name
Test status
Simulation time 75819071563 ps
CPU time 386.79 seconds
Started May 23 03:23:46 PM PDT 24
Finished May 23 03:30:14 PM PDT 24
Peak memory 202156 kb
Host smart-8fc2e6cf-8dae-4ef8-acd0-c7e990e8fc0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136889707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3136889707
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.84372233
Short name T753
Test name
Test status
Simulation time 427374219 ps
CPU time 0.9 seconds
Started May 23 03:24:01 PM PDT 24
Finished May 23 03:24:04 PM PDT 24
Peak memory 201556 kb
Host smart-57119fc7-1132-416b-bbd8-7c7a8730ecb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84372233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.84372233
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.273928952
Short name T289
Test name
Test status
Simulation time 332524424923 ps
CPU time 99.08 seconds
Started May 23 03:23:44 PM PDT 24
Finished May 23 03:25:25 PM PDT 24
Peak memory 201932 kb
Host smart-f5a15ef1-70df-48e1-b3e7-eb0e6dba633d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273928952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.273928952
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1348454749
Short name T95
Test name
Test status
Simulation time 328787967052 ps
CPU time 373.76 seconds
Started May 23 03:23:58 PM PDT 24
Finished May 23 03:30:14 PM PDT 24
Peak memory 201824 kb
Host smart-3a595bae-f9d4-489d-96f0-55b09c17a301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348454749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1348454749
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3797119133
Short name T455
Test name
Test status
Simulation time 163704632557 ps
CPU time 213.06 seconds
Started May 23 03:23:46 PM PDT 24
Finished May 23 03:27:21 PM PDT 24
Peak memory 201960 kb
Host smart-a9a177ff-0f70-4bf2-94fd-6ef987ca1ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797119133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3797119133
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2888420543
Short name T622
Test name
Test status
Simulation time 322927966783 ps
CPU time 173.43 seconds
Started May 23 03:23:41 PM PDT 24
Finished May 23 03:26:36 PM PDT 24
Peak memory 201820 kb
Host smart-56043e5b-8d1c-4e3a-916a-cd5bca2c3ca0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888420543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2888420543
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3982888149
Short name T464
Test name
Test status
Simulation time 169580858588 ps
CPU time 102.98 seconds
Started May 23 03:23:43 PM PDT 24
Finished May 23 03:25:28 PM PDT 24
Peak memory 201820 kb
Host smart-d58d1f02-a794-457f-bc90-3e2ed21ddd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982888149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3982888149
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3697179171
Short name T638
Test name
Test status
Simulation time 162643268468 ps
CPU time 97.43 seconds
Started May 23 03:23:42 PM PDT 24
Finished May 23 03:25:21 PM PDT 24
Peak memory 201800 kb
Host smart-4c8bc42f-bcc7-42e6-9a96-f2e13fadcced
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697179171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3697179171
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.587406503
Short name T469
Test name
Test status
Simulation time 172032328078 ps
CPU time 395.78 seconds
Started May 23 03:23:48 PM PDT 24
Finished May 23 03:30:25 PM PDT 24
Peak memory 201860 kb
Host smart-79c8ba12-56de-47be-86cd-75460408457b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587406503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.587406503
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3772331357
Short name T490
Test name
Test status
Simulation time 203293936851 ps
CPU time 440.25 seconds
Started May 23 03:23:47 PM PDT 24
Finished May 23 03:31:09 PM PDT 24
Peak memory 201844 kb
Host smart-cd0c190b-e4e6-426f-840d-dc16cc0786f8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772331357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3772331357
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.4065654912
Short name T227
Test name
Test status
Simulation time 88531603745 ps
CPU time 299.13 seconds
Started May 23 03:23:59 PM PDT 24
Finished May 23 03:29:01 PM PDT 24
Peak memory 202236 kb
Host smart-dc6b6ac9-d295-4334-b25d-c2c3667fcedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065654912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.4065654912
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3134281599
Short name T786
Test name
Test status
Simulation time 22360098302 ps
CPU time 3.84 seconds
Started May 23 03:23:59 PM PDT 24
Finished May 23 03:24:05 PM PDT 24
Peak memory 201668 kb
Host smart-2d3c7992-0c48-47f1-b03c-d36c46797dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134281599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3134281599
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1792652730
Short name T512
Test name
Test status
Simulation time 5190701132 ps
CPU time 12.53 seconds
Started May 23 03:23:58 PM PDT 24
Finished May 23 03:24:12 PM PDT 24
Peak memory 201676 kb
Host smart-13529f60-6281-4908-be5b-d50f12a9db37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792652730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1792652730
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.4281267876
Short name T120
Test name
Test status
Simulation time 5671417925 ps
CPU time 14.36 seconds
Started May 23 03:23:47 PM PDT 24
Finished May 23 03:24:03 PM PDT 24
Peak memory 201696 kb
Host smart-3064d1a5-dbfe-4125-8e2c-58319f302cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281267876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.4281267876
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1640298001
Short name T333
Test name
Test status
Simulation time 799013833855 ps
CPU time 2328.4 seconds
Started May 23 03:23:59 PM PDT 24
Finished May 23 04:02:50 PM PDT 24
Peak memory 211908 kb
Host smart-b8f73dc9-3437-4b8c-89be-6e3bc094eba7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640298001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1640298001
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3425183493
Short name T436
Test name
Test status
Simulation time 312608396 ps
CPU time 0.79 seconds
Started May 23 03:24:15 PM PDT 24
Finished May 23 03:24:18 PM PDT 24
Peak memory 201560 kb
Host smart-3eaf4d15-0131-474d-90e9-001a173f70d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425183493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3425183493
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.766056378
Short name T247
Test name
Test status
Simulation time 334806507858 ps
CPU time 94.15 seconds
Started May 23 03:24:14 PM PDT 24
Finished May 23 03:25:51 PM PDT 24
Peak memory 201820 kb
Host smart-1680c986-3ab4-48c7-8023-d47d64f9295d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766056378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.766056378
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.68902029
Short name T278
Test name
Test status
Simulation time 163648338166 ps
CPU time 190.78 seconds
Started May 23 03:23:59 PM PDT 24
Finished May 23 03:27:12 PM PDT 24
Peak memory 201948 kb
Host smart-cb78ef83-a253-4af4-ae2e-0c864d5e458a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68902029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.68902029
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1672332734
Short name T403
Test name
Test status
Simulation time 163971841953 ps
CPU time 403.28 seconds
Started May 23 03:24:18 PM PDT 24
Finished May 23 03:31:04 PM PDT 24
Peak memory 201840 kb
Host smart-1e6feb65-f154-4856-a1a4-1d390d778461
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672332734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1672332734
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1925116955
Short name T413
Test name
Test status
Simulation time 494520143785 ps
CPU time 590.78 seconds
Started May 23 03:24:00 PM PDT 24
Finished May 23 03:33:53 PM PDT 24
Peak memory 201880 kb
Host smart-948c16de-8488-4e02-a505-dfaa05962686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925116955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1925116955
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2536815908
Short name T402
Test name
Test status
Simulation time 499502377171 ps
CPU time 307.14 seconds
Started May 23 03:23:58 PM PDT 24
Finished May 23 03:29:08 PM PDT 24
Peak memory 201824 kb
Host smart-9fe49d21-ebf2-46a1-833f-5e3cf06b8ec5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536815908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2536815908
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3348829380
Short name T324
Test name
Test status
Simulation time 350359985185 ps
CPU time 760.65 seconds
Started May 23 03:24:15 PM PDT 24
Finished May 23 03:36:59 PM PDT 24
Peak memory 201868 kb
Host smart-5f943463-ff8c-41f1-928a-5a5ea1d265db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348829380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3348829380
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1554293785
Short name T687
Test name
Test status
Simulation time 394033757253 ps
CPU time 932.31 seconds
Started May 23 03:24:14 PM PDT 24
Finished May 23 03:39:49 PM PDT 24
Peak memory 201848 kb
Host smart-9bd55395-c446-4d54-9374-b7ec8bd3805d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554293785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1554293785
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.46939910
Short name T611
Test name
Test status
Simulation time 109701266538 ps
CPU time 510.59 seconds
Started May 23 03:24:14 PM PDT 24
Finished May 23 03:32:47 PM PDT 24
Peak memory 202068 kb
Host smart-42576996-6b9c-44b4-907a-9b5c4315647f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46939910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.46939910
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1032848195
Short name T539
Test name
Test status
Simulation time 23255498480 ps
CPU time 12.74 seconds
Started May 23 03:24:14 PM PDT 24
Finished May 23 03:24:29 PM PDT 24
Peak memory 201660 kb
Host smart-74c6f95a-4390-4729-aaed-05823b93ac2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032848195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1032848195
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3846214008
Short name T645
Test name
Test status
Simulation time 4925715947 ps
CPU time 3.14 seconds
Started May 23 03:24:19 PM PDT 24
Finished May 23 03:24:24 PM PDT 24
Peak memory 201672 kb
Host smart-42e20384-ed63-412a-8efb-3b0508d98761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846214008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3846214008
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3779906993
Short name T737
Test name
Test status
Simulation time 5723926741 ps
CPU time 4.3 seconds
Started May 23 03:23:58 PM PDT 24
Finished May 23 03:24:04 PM PDT 24
Peak memory 201640 kb
Host smart-1d785251-e93e-400f-a73b-1e34128305f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779906993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3779906993
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.265752696
Short name T294
Test name
Test status
Simulation time 201767365421 ps
CPU time 481.56 seconds
Started May 23 03:24:19 PM PDT 24
Finished May 23 03:32:23 PM PDT 24
Peak memory 201852 kb
Host smart-b5f9106b-18d2-448e-98e3-f49283d4011c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265752696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
265752696
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1713026997
Short name T21
Test name
Test status
Simulation time 596588861419 ps
CPU time 414.75 seconds
Started May 23 03:24:15 PM PDT 24
Finished May 23 03:31:12 PM PDT 24
Peak memory 210508 kb
Host smart-51483165-e589-4f80-a9c8-eaffa67c9d8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713026997 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1713026997
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.112774734
Short name T569
Test name
Test status
Simulation time 538618721 ps
CPU time 0.66 seconds
Started May 23 03:24:30 PM PDT 24
Finished May 23 03:24:33 PM PDT 24
Peak memory 201516 kb
Host smart-9b312113-a81f-4981-8c0b-042dbf1f8c8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112774734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.112774734
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3102041523
Short name T351
Test name
Test status
Simulation time 497129055550 ps
CPU time 390.42 seconds
Started May 23 03:24:16 PM PDT 24
Finished May 23 03:30:49 PM PDT 24
Peak memory 201840 kb
Host smart-549fbfa1-07de-48b1-ad81-2de6fb8b68e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102041523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3102041523
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.315055067
Short name T317
Test name
Test status
Simulation time 322520285577 ps
CPU time 711 seconds
Started May 23 03:24:14 PM PDT 24
Finished May 23 03:36:07 PM PDT 24
Peak memory 201872 kb
Host smart-744b92f6-dad7-4554-90a5-376d99049ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315055067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.315055067
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2866071674
Short name T614
Test name
Test status
Simulation time 492586725862 ps
CPU time 266.19 seconds
Started May 23 03:24:15 PM PDT 24
Finished May 23 03:28:43 PM PDT 24
Peak memory 201896 kb
Host smart-223e7b8a-70d1-44de-8049-124d534b00ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866071674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2866071674
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1771822220
Short name T438
Test name
Test status
Simulation time 165682761239 ps
CPU time 59.35 seconds
Started May 23 03:24:15 PM PDT 24
Finished May 23 03:25:17 PM PDT 24
Peak memory 201816 kb
Host smart-8eca2f42-eca8-4d47-a337-7d86440d9bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771822220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1771822220
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2378583443
Short name T481
Test name
Test status
Simulation time 167300975814 ps
CPU time 380.43 seconds
Started May 23 03:24:14 PM PDT 24
Finished May 23 03:30:36 PM PDT 24
Peak memory 201836 kb
Host smart-85b25430-3bf3-47c2-9403-625a2b5e90cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378583443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2378583443
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2762853462
Short name T584
Test name
Test status
Simulation time 407069267116 ps
CPU time 168.38 seconds
Started May 23 03:24:15 PM PDT 24
Finished May 23 03:27:06 PM PDT 24
Peak memory 201852 kb
Host smart-28ab74d4-5369-451e-9788-a9379e8f34da
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762853462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2762853462
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1651517330
Short name T646
Test name
Test status
Simulation time 123032687939 ps
CPU time 633.82 seconds
Started May 23 03:24:29 PM PDT 24
Finished May 23 03:35:05 PM PDT 24
Peak memory 202188 kb
Host smart-0e3f044c-36d6-493f-9217-a9868326fe43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651517330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1651517330
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.4104004089
Short name T447
Test name
Test status
Simulation time 28503077017 ps
CPU time 25.46 seconds
Started May 23 03:24:30 PM PDT 24
Finished May 23 03:24:58 PM PDT 24
Peak memory 201720 kb
Host smart-9fee3f47-f91a-4d0b-9777-840f92c98d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104004089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.4104004089
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2371717655
Short name T7
Test name
Test status
Simulation time 3638385520 ps
CPU time 8.5 seconds
Started May 23 03:24:19 PM PDT 24
Finished May 23 03:24:30 PM PDT 24
Peak memory 201608 kb
Host smart-175bf99f-7ffc-4082-b593-20cdd9725043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371717655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2371717655
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3541779683
Short name T592
Test name
Test status
Simulation time 5894940081 ps
CPU time 6.12 seconds
Started May 23 03:24:16 PM PDT 24
Finished May 23 03:24:25 PM PDT 24
Peak memory 201664 kb
Host smart-c4403e40-f89e-4630-82ff-dbc24cd8acba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541779683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3541779683
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2101046095
Short name T46
Test name
Test status
Simulation time 1188363669729 ps
CPU time 551.32 seconds
Started May 23 03:24:30 PM PDT 24
Finished May 23 03:33:44 PM PDT 24
Peak memory 210548 kb
Host smart-6eb9f678-5919-43e0-b9af-d63e0051bdb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101046095 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2101046095
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.945782454
Short name T419
Test name
Test status
Simulation time 484596142 ps
CPU time 0.85 seconds
Started May 23 03:24:30 PM PDT 24
Finished May 23 03:24:34 PM PDT 24
Peak memory 201556 kb
Host smart-021abb5d-db5d-4f36-9077-5811bac9db11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945782454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.945782454
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1010081039
Short name T160
Test name
Test status
Simulation time 336938013495 ps
CPU time 803.49 seconds
Started May 23 03:24:30 PM PDT 24
Finished May 23 03:37:56 PM PDT 24
Peak memory 201840 kb
Host smart-a066ceb2-d7e0-45a3-9306-989614c3e832
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010081039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1010081039
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1139137687
Short name T224
Test name
Test status
Simulation time 357712642635 ps
CPU time 228.59 seconds
Started May 23 03:24:31 PM PDT 24
Finished May 23 03:28:23 PM PDT 24
Peak memory 201908 kb
Host smart-1ea9e946-7de7-4bdc-8009-d336187a0360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139137687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1139137687
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2684675861
Short name T154
Test name
Test status
Simulation time 328830344631 ps
CPU time 49.6 seconds
Started May 23 03:24:30 PM PDT 24
Finished May 23 03:25:22 PM PDT 24
Peak memory 201888 kb
Host smart-66f0b52b-59a5-4f5d-9909-f11b12ae1f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684675861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2684675861
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2872609045
Short name T623
Test name
Test status
Simulation time 486557615897 ps
CPU time 278.66 seconds
Started May 23 03:24:30 PM PDT 24
Finished May 23 03:29:12 PM PDT 24
Peak memory 201900 kb
Host smart-694eabe6-0955-49e6-a5fe-5ed9462be80d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872609045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2872609045
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3128287454
Short name T84
Test name
Test status
Simulation time 491989099838 ps
CPU time 605.17 seconds
Started May 23 03:24:30 PM PDT 24
Finished May 23 03:34:38 PM PDT 24
Peak memory 201896 kb
Host smart-34382fbe-1a66-45c2-aeec-be7d05569394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128287454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3128287454
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3746589891
Short name T484
Test name
Test status
Simulation time 161987492285 ps
CPU time 370.02 seconds
Started May 23 03:24:34 PM PDT 24
Finished May 23 03:30:46 PM PDT 24
Peak memory 201800 kb
Host smart-aae252da-f018-470f-803f-7e9252ebad68
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746589891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3746589891
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3447907419
Short name T339
Test name
Test status
Simulation time 630973390302 ps
CPU time 381.83 seconds
Started May 23 03:24:31 PM PDT 24
Finished May 23 03:30:56 PM PDT 24
Peak memory 201936 kb
Host smart-63269b7b-d160-4515-89b1-2e47963fcdcf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447907419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3447907419
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3641129443
Short name T624
Test name
Test status
Simulation time 404076380151 ps
CPU time 452.21 seconds
Started May 23 03:24:30 PM PDT 24
Finished May 23 03:32:06 PM PDT 24
Peak memory 201828 kb
Host smart-c94bc56a-0e74-4e62-acbc-fef39b9518fb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641129443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.3641129443
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.331722981
Short name T392
Test name
Test status
Simulation time 65480116368 ps
CPU time 391.51 seconds
Started May 23 03:24:30 PM PDT 24
Finished May 23 03:31:04 PM PDT 24
Peak memory 202192 kb
Host smart-34f77467-ea14-4671-98d4-e1b6e8423301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331722981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.331722981
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.4218809467
Short name T727
Test name
Test status
Simulation time 40219423145 ps
CPU time 23.37 seconds
Started May 23 03:24:31 PM PDT 24
Finished May 23 03:24:57 PM PDT 24
Peak memory 201688 kb
Host smart-753c5723-8f4b-4416-a1a8-3f3c711980b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218809467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.4218809467
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3869406533
Short name T401
Test name
Test status
Simulation time 3860057649 ps
CPU time 10.12 seconds
Started May 23 03:24:31 PM PDT 24
Finished May 23 03:24:44 PM PDT 24
Peak memory 201524 kb
Host smart-3bed02ab-688b-4c18-a67d-78ca9ed6796c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869406533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3869406533
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.491091670
Short name T188
Test name
Test status
Simulation time 5861487455 ps
CPU time 4.68 seconds
Started May 23 03:24:33 PM PDT 24
Finished May 23 03:24:40 PM PDT 24
Peak memory 201660 kb
Host smart-4406532c-ef97-455b-b87d-e6ebe647cbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491091670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.491091670
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.302674660
Short name T306
Test name
Test status
Simulation time 15112205611 ps
CPU time 43.37 seconds
Started May 23 03:24:31 PM PDT 24
Finished May 23 03:25:17 PM PDT 24
Peak memory 210500 kb
Host smart-c2380716-682d-49bc-853b-c1418e7102b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302674660 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.302674660
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3850705814
Short name T468
Test name
Test status
Simulation time 534348624 ps
CPU time 0.85 seconds
Started May 23 03:24:55 PM PDT 24
Finished May 23 03:24:57 PM PDT 24
Peak memory 201512 kb
Host smart-41b991a4-087f-4fee-8c31-94fd22823da8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850705814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3850705814
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3888841505
Short name T534
Test name
Test status
Simulation time 347745597127 ps
CPU time 804.34 seconds
Started May 23 03:24:54 PM PDT 24
Finished May 23 03:38:20 PM PDT 24
Peak memory 201832 kb
Host smart-386493af-46a5-460d-b9c7-dfe4721861f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888841505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3888841505
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1350485509
Short name T747
Test name
Test status
Simulation time 489988048130 ps
CPU time 319.68 seconds
Started May 23 03:24:30 PM PDT 24
Finished May 23 03:29:53 PM PDT 24
Peak memory 201844 kb
Host smart-7f578125-1a76-467b-b034-5f1ef3b7c8ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350485509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1350485509
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2729797602
Short name T566
Test name
Test status
Simulation time 161822885127 ps
CPU time 357.05 seconds
Started May 23 03:24:31 PM PDT 24
Finished May 23 03:30:31 PM PDT 24
Peak memory 201820 kb
Host smart-3bb3d6f3-b232-4006-8651-ffd3735c9423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729797602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2729797602
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3185903833
Short name T732
Test name
Test status
Simulation time 500231438107 ps
CPU time 1063.18 seconds
Started May 23 03:24:31 PM PDT 24
Finished May 23 03:42:17 PM PDT 24
Peak memory 201840 kb
Host smart-c480d389-cfeb-4a41-bca4-03f8137813ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185903833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3185903833
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.4151068711
Short name T24
Test name
Test status
Simulation time 540778724777 ps
CPU time 1123.88 seconds
Started May 23 03:24:32 PM PDT 24
Finished May 23 03:43:18 PM PDT 24
Peak memory 201872 kb
Host smart-89c6aab9-1ca5-4bf3-9b32-a24a1dbd33d7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151068711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.4151068711
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3858005416
Short name T382
Test name
Test status
Simulation time 404422645261 ps
CPU time 244.38 seconds
Started May 23 03:24:54 PM PDT 24
Finished May 23 03:29:00 PM PDT 24
Peak memory 201848 kb
Host smart-fab9096f-eeb1-4fb5-a0e6-3358779102a9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858005416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3858005416
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.836341361
Short name T619
Test name
Test status
Simulation time 94605564972 ps
CPU time 402.37 seconds
Started May 23 03:24:51 PM PDT 24
Finished May 23 03:31:35 PM PDT 24
Peak memory 202216 kb
Host smart-665b2336-fbda-44fb-a00c-d77be4c4ccf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836341361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.836341361
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3022248793
Short name T772
Test name
Test status
Simulation time 42172388516 ps
CPU time 88.46 seconds
Started May 23 03:24:52 PM PDT 24
Finished May 23 03:26:22 PM PDT 24
Peak memory 201648 kb
Host smart-e95d78f5-e3ac-4120-a4a2-cdd4861ed98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022248793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3022248793
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3871117881
Short name T565
Test name
Test status
Simulation time 3050320994 ps
CPU time 5.93 seconds
Started May 23 03:24:51 PM PDT 24
Finished May 23 03:24:59 PM PDT 24
Peak memory 201524 kb
Host smart-9e2e0e0a-f6d1-4851-9dc6-a0c42455275e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871117881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3871117881
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2183952343
Short name T409
Test name
Test status
Simulation time 5747367327 ps
CPU time 2.91 seconds
Started May 23 03:24:33 PM PDT 24
Finished May 23 03:24:38 PM PDT 24
Peak memory 201660 kb
Host smart-3d37cb50-b35f-4be6-b912-9baeff0c25d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183952343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2183952343
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1826912088
Short name T89
Test name
Test status
Simulation time 208829490966 ps
CPU time 510.19 seconds
Started May 23 03:24:53 PM PDT 24
Finished May 23 03:33:25 PM PDT 24
Peak memory 201896 kb
Host smart-d664c6a3-aacb-459a-a925-734221139137
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826912088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1826912088
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1190508640
Short name T280
Test name
Test status
Simulation time 136523660537 ps
CPU time 50.71 seconds
Started May 23 03:24:52 PM PDT 24
Finished May 23 03:25:44 PM PDT 24
Peak memory 210236 kb
Host smart-d274f8c2-c3d0-4f14-ae38-905b74d37cff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190508640 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1190508640
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.183589906
Short name T640
Test name
Test status
Simulation time 392898271 ps
CPU time 1.53 seconds
Started May 23 03:24:55 PM PDT 24
Finished May 23 03:24:58 PM PDT 24
Peak memory 201540 kb
Host smart-da86dabb-66f8-4db2-acb3-c7ba492d46c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183589906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.183589906
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1091409734
Short name T341
Test name
Test status
Simulation time 492191262221 ps
CPU time 1159.54 seconds
Started May 23 03:24:52 PM PDT 24
Finished May 23 03:44:13 PM PDT 24
Peak memory 201948 kb
Host smart-bca06fe4-60a9-4459-8c50-7da1b76a171d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091409734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1091409734
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1139470793
Short name T798
Test name
Test status
Simulation time 499719056050 ps
CPU time 1240.24 seconds
Started May 23 03:24:50 PM PDT 24
Finished May 23 03:45:31 PM PDT 24
Peak memory 201832 kb
Host smart-8332b0f2-6fcf-4a98-982e-e8d45af8b79b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139470793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1139470793
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.334639896
Short name T429
Test name
Test status
Simulation time 497658096193 ps
CPU time 1066.28 seconds
Started May 23 03:24:53 PM PDT 24
Finished May 23 03:42:41 PM PDT 24
Peak memory 201824 kb
Host smart-dcfb1454-a437-450f-a583-4c111cc9625f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334639896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.334639896
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.4182780193
Short name T389
Test name
Test status
Simulation time 162749296051 ps
CPU time 346.41 seconds
Started May 23 03:24:53 PM PDT 24
Finished May 23 03:30:41 PM PDT 24
Peak memory 201704 kb
Host smart-cb1ec4de-30f5-48ef-8259-a51640062c82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182780193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.4182780193
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3015788010
Short name T254
Test name
Test status
Simulation time 567089180672 ps
CPU time 624.64 seconds
Started May 23 03:24:52 PM PDT 24
Finished May 23 03:35:19 PM PDT 24
Peak memory 201936 kb
Host smart-51fe468e-0e45-4972-8bc5-9544c68ab576
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015788010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3015788010
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3125047102
Short name T651
Test name
Test status
Simulation time 394288298968 ps
CPU time 939.42 seconds
Started May 23 03:24:52 PM PDT 24
Finished May 23 03:40:33 PM PDT 24
Peak memory 201848 kb
Host smart-c97281c4-7d34-47e1-be81-32d8ea26b48e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125047102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3125047102
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2702649972
Short name T769
Test name
Test status
Simulation time 38825579711 ps
CPU time 68.04 seconds
Started May 23 03:24:54 PM PDT 24
Finished May 23 03:26:04 PM PDT 24
Peak memory 201628 kb
Host smart-3d2e93a1-fb1c-487d-b7be-080dd9d9639a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702649972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2702649972
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3155128569
Short name T554
Test name
Test status
Simulation time 4184298035 ps
CPU time 11.25 seconds
Started May 23 03:24:51 PM PDT 24
Finished May 23 03:25:04 PM PDT 24
Peak memory 201576 kb
Host smart-9034c88f-2135-40e0-ad3c-fb7e088551a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155128569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3155128569
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1191635389
Short name T704
Test name
Test status
Simulation time 5934578784 ps
CPU time 4.36 seconds
Started May 23 03:24:52 PM PDT 24
Finished May 23 03:24:58 PM PDT 24
Peak memory 201676 kb
Host smart-522fe9ff-6294-4c48-9df7-e1350a765119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191635389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1191635389
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3953116898
Short name T674
Test name
Test status
Simulation time 25614239182 ps
CPU time 53.06 seconds
Started May 23 03:24:52 PM PDT 24
Finished May 23 03:25:47 PM PDT 24
Peak memory 201652 kb
Host smart-84ac198f-47b8-422f-a515-2fa82e84ec51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953116898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3953116898
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1543392259
Short name T794
Test name
Test status
Simulation time 44205305804 ps
CPU time 91.75 seconds
Started May 23 03:24:52 PM PDT 24
Finished May 23 03:26:25 PM PDT 24
Peak memory 212008 kb
Host smart-e72e6c92-ad6f-4827-a87a-1561fec779bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543392259 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1543392259
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1900121068
Short name T670
Test name
Test status
Simulation time 398718231 ps
CPU time 0.85 seconds
Started May 23 03:21:41 PM PDT 24
Finished May 23 03:21:44 PM PDT 24
Peak memory 201516 kb
Host smart-934cf441-e848-4f19-b823-a05b1f2999f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900121068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1900121068
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1156017532
Short name T663
Test name
Test status
Simulation time 350166217048 ps
CPU time 458.77 seconds
Started May 23 03:21:42 PM PDT 24
Finished May 23 03:29:23 PM PDT 24
Peak memory 201844 kb
Host smart-1ad5f1f0-0e7f-405d-892d-d1a04565e41a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156017532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1156017532
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1669131206
Short name T733
Test name
Test status
Simulation time 165801904568 ps
CPU time 395.61 seconds
Started May 23 03:21:41 PM PDT 24
Finished May 23 03:28:19 PM PDT 24
Peak memory 201840 kb
Host smart-d3745b33-217f-4ffc-8a9b-b4d37270c407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669131206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1669131206
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.349122770
Short name T178
Test name
Test status
Simulation time 322288946928 ps
CPU time 201.36 seconds
Started May 23 03:21:41 PM PDT 24
Finished May 23 03:25:04 PM PDT 24
Peak memory 201928 kb
Host smart-a34000c4-9ea4-4621-9b13-14ad3af5794b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349122770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.349122770
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.1896751581
Short name T567
Test name
Test status
Simulation time 485213558107 ps
CPU time 612.18 seconds
Started May 23 03:21:40 PM PDT 24
Finished May 23 03:31:54 PM PDT 24
Peak memory 201832 kb
Host smart-d6254b7f-021c-4b07-8b7f-8c1e7c6feddc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896751581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.1896751581
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3800558412
Short name T196
Test name
Test status
Simulation time 490737846802 ps
CPU time 69.03 seconds
Started May 23 03:21:24 PM PDT 24
Finished May 23 03:22:38 PM PDT 24
Peak memory 201836 kb
Host smart-f7f539f0-c180-4370-8c3d-493cb913d8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800558412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3800558412
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3292092021
Short name T430
Test name
Test status
Simulation time 496417636386 ps
CPU time 598.52 seconds
Started May 23 03:21:31 PM PDT 24
Finished May 23 03:31:33 PM PDT 24
Peak memory 201844 kb
Host smart-3eb7c7a5-b0f4-4ee6-9fff-41f96e71a948
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292092021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3292092021
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3183357450
Short name T338
Test name
Test status
Simulation time 186031723387 ps
CPU time 91.08 seconds
Started May 23 03:21:40 PM PDT 24
Finished May 23 03:23:13 PM PDT 24
Peak memory 201828 kb
Host smart-537aba80-9315-492e-a960-a9847629bf96
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183357450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3183357450
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1715764677
Short name T418
Test name
Test status
Simulation time 195475123775 ps
CPU time 445.85 seconds
Started May 23 03:21:49 PM PDT 24
Finished May 23 03:29:16 PM PDT 24
Peak memory 201812 kb
Host smart-9691405e-e7e0-4f0e-8b78-f0a7c09ea2e5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715764677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1715764677
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.516037070
Short name T185
Test name
Test status
Simulation time 98165070333 ps
CPU time 379.41 seconds
Started May 23 03:21:50 PM PDT 24
Finished May 23 03:28:10 PM PDT 24
Peak memory 202192 kb
Host smart-5b49a4ea-d7b4-42ea-b699-046ca1dd89c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516037070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.516037070
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.1602852856
Short name T639
Test name
Test status
Simulation time 23395172712 ps
CPU time 57.3 seconds
Started May 23 03:21:42 PM PDT 24
Finished May 23 03:22:41 PM PDT 24
Peak memory 201612 kb
Host smart-a16ae063-6358-4398-b81c-0fcce6166daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602852856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1602852856
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1533228395
Short name T636
Test name
Test status
Simulation time 3722199984 ps
CPU time 1.8 seconds
Started May 23 03:21:39 PM PDT 24
Finished May 23 03:21:42 PM PDT 24
Peak memory 201600 kb
Host smart-0e1fc23a-c2d3-40c6-b256-c80d1c000bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533228395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1533228395
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3253905988
Short name T72
Test name
Test status
Simulation time 8877498167 ps
CPU time 2.77 seconds
Started May 23 03:21:41 PM PDT 24
Finished May 23 03:21:46 PM PDT 24
Peak memory 218404 kb
Host smart-6e6d5b2b-ac56-4bfd-b5ac-d0fc7ef4e8c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253905988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3253905988
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.672364618
Short name T212
Test name
Test status
Simulation time 5857460646 ps
CPU time 3.94 seconds
Started May 23 03:21:31 PM PDT 24
Finished May 23 03:21:38 PM PDT 24
Peak memory 201676 kb
Host smart-10dc4254-bfee-4270-8707-ee5cf200776e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672364618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.672364618
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2243932575
Short name T453
Test name
Test status
Simulation time 196741612128 ps
CPU time 229.76 seconds
Started May 23 03:21:45 PM PDT 24
Finished May 23 03:25:36 PM PDT 24
Peak memory 201832 kb
Host smart-fea2ff26-54da-4ca3-84fe-3bdf537e7509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243932575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2243932575
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3678833210
Short name T33
Test name
Test status
Simulation time 141884639460 ps
CPU time 80.52 seconds
Started May 23 03:21:44 PM PDT 24
Finished May 23 03:23:06 PM PDT 24
Peak memory 210160 kb
Host smart-d9beed07-8adf-4763-a814-d4edff739dcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678833210 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3678833210
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.4233611713
Short name T593
Test name
Test status
Simulation time 385261223 ps
CPU time 1.51 seconds
Started May 23 03:25:09 PM PDT 24
Finished May 23 03:25:12 PM PDT 24
Peak memory 201544 kb
Host smart-077efab8-6e74-4ce5-bf16-38a7ea525436
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233611713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.4233611713
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.297036124
Short name T654
Test name
Test status
Simulation time 595201327702 ps
CPU time 87.19 seconds
Started May 23 03:25:08 PM PDT 24
Finished May 23 03:26:38 PM PDT 24
Peak memory 201864 kb
Host smart-dc2e6412-38fd-4519-a02e-5196b45f1a84
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297036124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gati
ng.297036124
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2372562423
Short name T26
Test name
Test status
Simulation time 325686265375 ps
CPU time 804.16 seconds
Started May 23 03:24:52 PM PDT 24
Finished May 23 03:38:17 PM PDT 24
Peak memory 201884 kb
Host smart-afc28381-fd14-42b5-b693-f3f199a0b4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372562423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2372562423
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.353638455
Short name T461
Test name
Test status
Simulation time 495210926422 ps
CPU time 576.86 seconds
Started May 23 03:25:10 PM PDT 24
Finished May 23 03:34:49 PM PDT 24
Peak memory 201844 kb
Host smart-2516f6af-8b7f-48d7-9a99-4adbcfa67dfe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=353638455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrup
t_fixed.353638455
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3350115215
Short name T180
Test name
Test status
Simulation time 490242406559 ps
CPU time 956.9 seconds
Started May 23 03:24:51 PM PDT 24
Finished May 23 03:40:49 PM PDT 24
Peak memory 201848 kb
Host smart-41c41da9-2f99-4fcc-9f32-3455b39be4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350115215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3350115215
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2951119363
Short name T528
Test name
Test status
Simulation time 159604756320 ps
CPU time 72.81 seconds
Started May 23 03:24:51 PM PDT 24
Finished May 23 03:26:05 PM PDT 24
Peak memory 201800 kb
Host smart-5a4b1662-b11f-4ad0-b196-b2c764cdb7e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951119363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2951119363
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1828715106
Short name T549
Test name
Test status
Simulation time 607792240297 ps
CPU time 1497.54 seconds
Started May 23 03:25:09 PM PDT 24
Finished May 23 03:50:09 PM PDT 24
Peak memory 201828 kb
Host smart-75c39cc0-ad64-4ad6-9afa-345f53d4abcf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828715106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1828715106
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3463459097
Short name T230
Test name
Test status
Simulation time 77523866893 ps
CPU time 291.29 seconds
Started May 23 03:25:10 PM PDT 24
Finished May 23 03:30:03 PM PDT 24
Peak memory 202112 kb
Host smart-6c0eadc0-064c-4884-82f7-ab81cb740d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463459097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3463459097
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1270411714
Short name T520
Test name
Test status
Simulation time 24857350978 ps
CPU time 27.54 seconds
Started May 23 03:25:09 PM PDT 24
Finished May 23 03:25:39 PM PDT 24
Peak memory 201688 kb
Host smart-18535806-35a6-4ba9-9547-2472480fbb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270411714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1270411714
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1618968099
Short name T187
Test name
Test status
Simulation time 3824920778 ps
CPU time 1.44 seconds
Started May 23 03:25:10 PM PDT 24
Finished May 23 03:25:14 PM PDT 24
Peak memory 201572 kb
Host smart-f62e9caf-273f-4e61-90a5-8d21d61707b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618968099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1618968099
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.214033565
Short name T517
Test name
Test status
Simulation time 5832851140 ps
CPU time 14.34 seconds
Started May 23 03:24:52 PM PDT 24
Finished May 23 03:25:08 PM PDT 24
Peak memory 201636 kb
Host smart-cebd8e03-06ca-4beb-a8f7-be734b8dca2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214033565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.214033565
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.4084025574
Short name T741
Test name
Test status
Simulation time 365235620679 ps
CPU time 741.21 seconds
Started May 23 03:25:10 PM PDT 24
Finished May 23 03:37:33 PM PDT 24
Peak memory 201828 kb
Host smart-b4ae76c9-133d-430f-aaf5-05b5449280e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084025574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.4084025574
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3785060281
Short name T22
Test name
Test status
Simulation time 213742570646 ps
CPU time 131.96 seconds
Started May 23 03:25:12 PM PDT 24
Finished May 23 03:27:26 PM PDT 24
Peak memory 210136 kb
Host smart-0d578275-9db2-4a05-abb5-82fb37f8d073
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785060281 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3785060281
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2980198348
Short name T106
Test name
Test status
Simulation time 348048376 ps
CPU time 1.38 seconds
Started May 23 03:25:25 PM PDT 24
Finished May 23 03:25:29 PM PDT 24
Peak memory 201556 kb
Host smart-43c111b3-3e33-45b1-b51d-8ab3195b61a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980198348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2980198348
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.397056994
Short name T281
Test name
Test status
Simulation time 531186842012 ps
CPU time 309.92 seconds
Started May 23 03:25:11 PM PDT 24
Finished May 23 03:30:24 PM PDT 24
Peak memory 201828 kb
Host smart-a538582f-80e7-437a-8650-4f4fd1225a15
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397056994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.397056994
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2066784501
Short name T788
Test name
Test status
Simulation time 346048949137 ps
CPU time 214.98 seconds
Started May 23 03:25:12 PM PDT 24
Finished May 23 03:28:50 PM PDT 24
Peak memory 201920 kb
Host smart-c6d4ba69-8e30-4b2a-b407-f814e70929dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066784501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2066784501
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1544912307
Short name T491
Test name
Test status
Simulation time 484568474983 ps
CPU time 563.63 seconds
Started May 23 03:25:09 PM PDT 24
Finished May 23 03:34:35 PM PDT 24
Peak memory 201864 kb
Host smart-b362d761-78a8-4011-8aad-42479fc5a1ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544912307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1544912307
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1408126584
Short name T572
Test name
Test status
Simulation time 488332728914 ps
CPU time 1142.06 seconds
Started May 23 03:25:13 PM PDT 24
Finished May 23 03:44:17 PM PDT 24
Peak memory 201828 kb
Host smart-402be52b-71f6-4b3f-9eca-b6b5f691f38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408126584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1408126584
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1283667780
Short name T478
Test name
Test status
Simulation time 326530319879 ps
CPU time 697.51 seconds
Started May 23 03:25:11 PM PDT 24
Finished May 23 03:36:52 PM PDT 24
Peak memory 201880 kb
Host smart-bb86c665-1107-45de-aad1-0ba57e8ffabc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283667780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1283667780
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2969584669
Short name T191
Test name
Test status
Simulation time 176043559945 ps
CPU time 52.71 seconds
Started May 23 03:25:10 PM PDT 24
Finished May 23 03:26:06 PM PDT 24
Peak memory 201884 kb
Host smart-d842ef8b-54ab-46a7-9179-a770e12187fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969584669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2969584669
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1837341138
Short name T526
Test name
Test status
Simulation time 393717349570 ps
CPU time 378.7 seconds
Started May 23 03:25:12 PM PDT 24
Finished May 23 03:31:33 PM PDT 24
Peak memory 201848 kb
Host smart-bb56c8b0-f9fe-4c22-9a2f-b17e3c9fdb53
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837341138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1837341138
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.166889975
Short name T522
Test name
Test status
Simulation time 102468863567 ps
CPU time 374.69 seconds
Started May 23 03:25:11 PM PDT 24
Finished May 23 03:31:28 PM PDT 24
Peak memory 202156 kb
Host smart-5b612f70-e99b-4800-8897-2c01392a2776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166889975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.166889975
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.207393906
Short name T796
Test name
Test status
Simulation time 27433123117 ps
CPU time 15.69 seconds
Started May 23 03:25:13 PM PDT 24
Finished May 23 03:25:31 PM PDT 24
Peak memory 201672 kb
Host smart-52db512e-3c5e-45aa-a889-2bbbdb532014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207393906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.207393906
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2394231653
Short name T746
Test name
Test status
Simulation time 4414861862 ps
CPU time 3.65 seconds
Started May 23 03:25:13 PM PDT 24
Finished May 23 03:25:19 PM PDT 24
Peak memory 201664 kb
Host smart-0dbccfcd-193f-4f0f-9c38-63ffad0d9ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394231653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2394231653
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2047123368
Short name T422
Test name
Test status
Simulation time 5564656177 ps
CPU time 4.27 seconds
Started May 23 03:25:11 PM PDT 24
Finished May 23 03:25:17 PM PDT 24
Peak memory 201684 kb
Host smart-a59ebca4-2c80-4000-8e48-b73bbb774337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047123368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2047123368
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3235442614
Short name T797
Test name
Test status
Simulation time 178843126251 ps
CPU time 200.23 seconds
Started May 23 03:25:27 PM PDT 24
Finished May 23 03:28:50 PM PDT 24
Peak memory 217804 kb
Host smart-715be19c-6b97-4d7c-b757-ec9523ed613c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235442614 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3235442614
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2904516885
Short name T500
Test name
Test status
Simulation time 328790523 ps
CPU time 0.98 seconds
Started May 23 03:25:27 PM PDT 24
Finished May 23 03:25:31 PM PDT 24
Peak memory 201524 kb
Host smart-a0232e74-7222-40c8-94e7-782f745b05ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904516885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2904516885
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3027752347
Short name T346
Test name
Test status
Simulation time 350534438470 ps
CPU time 804.84 seconds
Started May 23 03:25:28 PM PDT 24
Finished May 23 03:38:56 PM PDT 24
Peak memory 201864 kb
Host smart-2f24b6c7-a014-4b07-9d22-b19b393425e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027752347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3027752347
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3296357728
Short name T342
Test name
Test status
Simulation time 349124068550 ps
CPU time 752.94 seconds
Started May 23 03:25:24 PM PDT 24
Finished May 23 03:38:00 PM PDT 24
Peak memory 201756 kb
Host smart-ad5ac108-6d95-4c07-a5b6-4574ab6b55dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296357728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3296357728
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3795699185
Short name T467
Test name
Test status
Simulation time 484605743050 ps
CPU time 293.48 seconds
Started May 23 03:25:27 PM PDT 24
Finished May 23 03:30:23 PM PDT 24
Peak memory 201912 kb
Host smart-f0a0bc87-2dd9-430a-a77b-4a025aed5123
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795699185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3795699185
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.824681354
Short name T799
Test name
Test status
Simulation time 169442123765 ps
CPU time 104.86 seconds
Started May 23 03:25:25 PM PDT 24
Finished May 23 03:27:13 PM PDT 24
Peak memory 201724 kb
Host smart-417f16e7-600a-4ab2-96c8-61fbd3d3380b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824681354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.824681354
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3646917148
Short name T768
Test name
Test status
Simulation time 331661058702 ps
CPU time 819.35 seconds
Started May 23 03:25:27 PM PDT 24
Finished May 23 03:39:09 PM PDT 24
Peak memory 201828 kb
Host smart-fb877c40-1d72-4fb6-b0ff-d12bad8f314c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646917148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3646917148
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.2365864430
Short name T345
Test name
Test status
Simulation time 354340413521 ps
CPU time 815.79 seconds
Started May 23 03:25:28 PM PDT 24
Finished May 23 03:39:07 PM PDT 24
Peak memory 201932 kb
Host smart-ca9b5e03-6284-46df-8c3d-e74eca0b2aa5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365864430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.2365864430
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2907539490
Short name T414
Test name
Test status
Simulation time 202239649460 ps
CPU time 47.6 seconds
Started May 23 03:25:26 PM PDT 24
Finished May 23 03:26:16 PM PDT 24
Peak memory 201856 kb
Host smart-1009fb9d-9d2b-4dfd-99d6-eaaef4593100
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907539490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2907539490
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.1694379546
Short name T709
Test name
Test status
Simulation time 111079003208 ps
CPU time 364.72 seconds
Started May 23 03:25:25 PM PDT 24
Finished May 23 03:31:33 PM PDT 24
Peak memory 202168 kb
Host smart-2c0a70ec-0504-4e8e-9a50-21a8cbee8516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694379546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1694379546
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.885697260
Short name T371
Test name
Test status
Simulation time 25806950434 ps
CPU time 61.02 seconds
Started May 23 03:25:26 PM PDT 24
Finished May 23 03:26:30 PM PDT 24
Peak memory 201672 kb
Host smart-9a778361-d4de-4acd-b6f4-5c246b8c65be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885697260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.885697260
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1868987189
Short name T669
Test name
Test status
Simulation time 3994388061 ps
CPU time 7.4 seconds
Started May 23 03:25:28 PM PDT 24
Finished May 23 03:25:38 PM PDT 24
Peak memory 201620 kb
Host smart-67ec1bdb-681a-4be3-ad10-65f3bac81263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868987189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1868987189
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3777300152
Short name T145
Test name
Test status
Simulation time 5680472157 ps
CPU time 2.23 seconds
Started May 23 03:25:26 PM PDT 24
Finished May 23 03:25:31 PM PDT 24
Peak memory 201660 kb
Host smart-d7d48845-afab-4c4a-9b31-02b3bbfdcb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777300152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3777300152
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2054328304
Short name T536
Test name
Test status
Simulation time 200517534186 ps
CPU time 208.82 seconds
Started May 23 03:25:29 PM PDT 24
Finished May 23 03:29:00 PM PDT 24
Peak memory 201856 kb
Host smart-3cc00cee-67a7-44e5-819b-ac7f10d4509a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054328304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2054328304
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1505559261
Short name T692
Test name
Test status
Simulation time 20616449822 ps
CPU time 39.88 seconds
Started May 23 03:25:27 PM PDT 24
Finished May 23 03:26:10 PM PDT 24
Peak memory 210240 kb
Host smart-2cb03734-b5d1-48be-bd26-666491d76b5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505559261 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1505559261
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1747332976
Short name T394
Test name
Test status
Simulation time 466446622 ps
CPU time 0.91 seconds
Started May 23 03:25:43 PM PDT 24
Finished May 23 03:25:45 PM PDT 24
Peak memory 201540 kb
Host smart-b2242616-b867-4d30-85dd-056ed227d2ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747332976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1747332976
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1503968811
Short name T576
Test name
Test status
Simulation time 172336300128 ps
CPU time 178.45 seconds
Started May 23 03:25:44 PM PDT 24
Finished May 23 03:28:44 PM PDT 24
Peak memory 201852 kb
Host smart-e455701c-a093-40a2-9b80-94686f3c1c88
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503968811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1503968811
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1274874741
Short name T321
Test name
Test status
Simulation time 524354283764 ps
CPU time 1295.42 seconds
Started May 23 03:25:43 PM PDT 24
Finished May 23 03:47:21 PM PDT 24
Peak memory 201844 kb
Host smart-83a58a2c-ef8c-4bbb-900b-8dd702a320f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274874741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1274874741
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1786935732
Short name T685
Test name
Test status
Simulation time 502298509528 ps
CPU time 625.65 seconds
Started May 23 03:25:28 PM PDT 24
Finished May 23 03:35:56 PM PDT 24
Peak memory 201836 kb
Host smart-63561b8a-e3e2-4097-af6a-3b74e8c7d533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786935732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1786935732
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3836777628
Short name T505
Test name
Test status
Simulation time 168676461755 ps
CPU time 224.83 seconds
Started May 23 03:25:41 PM PDT 24
Finished May 23 03:29:27 PM PDT 24
Peak memory 201832 kb
Host smart-b95b4a3f-53b3-4ed1-ac34-0575412239ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836777628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3836777628
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.545754987
Short name T159
Test name
Test status
Simulation time 164461301660 ps
CPU time 85.3 seconds
Started May 23 03:25:25 PM PDT 24
Finished May 23 03:26:53 PM PDT 24
Peak memory 201972 kb
Host smart-8206adb6-3566-4d1b-8d23-b3b93d403020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545754987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.545754987
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1592082795
Short name T380
Test name
Test status
Simulation time 494260865762 ps
CPU time 296.55 seconds
Started May 23 03:25:28 PM PDT 24
Finished May 23 03:30:28 PM PDT 24
Peak memory 201832 kb
Host smart-d9ca3c84-7af1-4514-bdaf-96a5f03f7500
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592082795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1592082795
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3812951304
Short name T279
Test name
Test status
Simulation time 563840848104 ps
CPU time 316.19 seconds
Started May 23 03:25:43 PM PDT 24
Finished May 23 03:31:00 PM PDT 24
Peak memory 201860 kb
Host smart-f60105e1-28fe-426a-8f73-8fa7f28b4efe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812951304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3812951304
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3106226224
Short name T210
Test name
Test status
Simulation time 402104609136 ps
CPU time 922.69 seconds
Started May 23 03:25:42 PM PDT 24
Finished May 23 03:41:06 PM PDT 24
Peak memory 201832 kb
Host smart-89fbf354-e54d-4978-9fc6-8e5e6625da7b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106226224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3106226224
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1335840894
Short name T462
Test name
Test status
Simulation time 110767028107 ps
CPU time 636.74 seconds
Started May 23 03:25:41 PM PDT 24
Finished May 23 03:36:20 PM PDT 24
Peak memory 202208 kb
Host smart-f07e3ad8-0d3a-4d23-a76a-87b3dba248e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335840894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1335840894
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.21286964
Short name T655
Test name
Test status
Simulation time 27168336933 ps
CPU time 16.59 seconds
Started May 23 03:25:42 PM PDT 24
Finished May 23 03:26:00 PM PDT 24
Peak memory 201636 kb
Host smart-25783f62-0aaf-4933-ba37-5c373fec08ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21286964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.21286964
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.4213893114
Short name T427
Test name
Test status
Simulation time 4561772907 ps
CPU time 8.82 seconds
Started May 23 03:25:42 PM PDT 24
Finished May 23 03:25:52 PM PDT 24
Peak memory 201592 kb
Host smart-0b423f53-6087-4129-96a0-e4a03e17b225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213893114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.4213893114
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1472769553
Short name T742
Test name
Test status
Simulation time 6039724542 ps
CPU time 15.16 seconds
Started May 23 03:25:30 PM PDT 24
Finished May 23 03:25:48 PM PDT 24
Peak memory 201676 kb
Host smart-da7d759e-a0dc-415f-94fa-19e06432cc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472769553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1472769553
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3596855106
Short name T535
Test name
Test status
Simulation time 181316955334 ps
CPU time 179.95 seconds
Started May 23 03:25:41 PM PDT 24
Finished May 23 03:28:43 PM PDT 24
Peak memory 201860 kb
Host smart-6b251de7-d193-401b-a947-c37bf1301782
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596855106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3596855106
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.4267533724
Short name T773
Test name
Test status
Simulation time 102476091032 ps
CPU time 71.78 seconds
Started May 23 03:25:42 PM PDT 24
Finished May 23 03:26:56 PM PDT 24
Peak memory 210436 kb
Host smart-d21a9b5d-f596-4cc1-9724-39a02fe4aa6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267533724 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.4267533724
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.806820777
Short name T515
Test name
Test status
Simulation time 327696697 ps
CPU time 1.28 seconds
Started May 23 03:25:57 PM PDT 24
Finished May 23 03:26:00 PM PDT 24
Peak memory 201544 kb
Host smart-e5863007-e25c-4f8a-a48a-0be60ac04bc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806820777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.806820777
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.968610635
Short name T693
Test name
Test status
Simulation time 341373631587 ps
CPU time 185.77 seconds
Started May 23 03:25:56 PM PDT 24
Finished May 23 03:29:04 PM PDT 24
Peak memory 201848 kb
Host smart-c57fe2ee-8c1e-43da-8122-471fdca5ded5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968610635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gati
ng.968610635
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1187569273
Short name T266
Test name
Test status
Simulation time 556045290449 ps
CPU time 322.41 seconds
Started May 23 03:25:57 PM PDT 24
Finished May 23 03:31:21 PM PDT 24
Peak memory 201756 kb
Host smart-fe14d8d5-b2d8-4169-9afc-2ace84ea5cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187569273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1187569273
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.246323759
Short name T626
Test name
Test status
Simulation time 321948464562 ps
CPU time 158.09 seconds
Started May 23 03:25:57 PM PDT 24
Finished May 23 03:28:37 PM PDT 24
Peak memory 201944 kb
Host smart-f4d56e69-eefc-4abc-a712-fe362e0f99af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246323759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.246323759
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2314784295
Short name T476
Test name
Test status
Simulation time 492986289557 ps
CPU time 790.53 seconds
Started May 23 03:25:42 PM PDT 24
Finished May 23 03:38:54 PM PDT 24
Peak memory 201816 kb
Host smart-6101dd47-42fc-4b37-b1fb-3e09a2a0420a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314784295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2314784295
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3407741197
Short name T657
Test name
Test status
Simulation time 329622706130 ps
CPU time 681.11 seconds
Started May 23 03:25:55 PM PDT 24
Finished May 23 03:37:19 PM PDT 24
Peak memory 201840 kb
Host smart-2b2641a6-1df1-4958-88aa-d73eca18abc3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407741197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3407741197
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3409151022
Short name T225
Test name
Test status
Simulation time 353447189202 ps
CPU time 204.7 seconds
Started May 23 03:25:58 PM PDT 24
Finished May 23 03:29:25 PM PDT 24
Peak memory 201880 kb
Host smart-99262ef0-8304-40e7-9b91-101832c7525e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409151022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3409151022
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3865877684
Short name T488
Test name
Test status
Simulation time 606441364187 ps
CPU time 350.49 seconds
Started May 23 03:25:58 PM PDT 24
Finished May 23 03:31:51 PM PDT 24
Peak memory 201920 kb
Host smart-cf7cebdd-7c30-4d1c-bfd8-3ddf7cc38cbe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865877684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3865877684
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.515551640
Short name T497
Test name
Test status
Simulation time 87858565116 ps
CPU time 454.9 seconds
Started May 23 03:25:57 PM PDT 24
Finished May 23 03:33:34 PM PDT 24
Peak memory 202136 kb
Host smart-e6a2f4df-28dc-42be-88e4-4b5516fb9f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515551640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.515551640
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1868160712
Short name T524
Test name
Test status
Simulation time 42456560828 ps
CPU time 42.55 seconds
Started May 23 03:25:58 PM PDT 24
Finished May 23 03:26:42 PM PDT 24
Peak memory 201668 kb
Host smart-73ff6fd3-b0b0-4ea2-be15-b037e30d9b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868160712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1868160712
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3077860065
Short name T726
Test name
Test status
Simulation time 5147748749 ps
CPU time 5.02 seconds
Started May 23 03:25:59 PM PDT 24
Finished May 23 03:26:06 PM PDT 24
Peak memory 201616 kb
Host smart-bcd24603-4cf3-45ef-95d7-bf0a96c21049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077860065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3077860065
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1562081538
Short name T783
Test name
Test status
Simulation time 6193508083 ps
CPU time 4.53 seconds
Started May 23 03:25:42 PM PDT 24
Finished May 23 03:25:48 PM PDT 24
Peak memory 201656 kb
Host smart-3b12da15-4540-4e96-ad74-50c93f4f32c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562081538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1562081538
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3674545608
Short name T482
Test name
Test status
Simulation time 62154773177 ps
CPU time 39.38 seconds
Started May 23 03:25:57 PM PDT 24
Finished May 23 03:26:39 PM PDT 24
Peak memory 201672 kb
Host smart-8e85319f-f179-458d-a911-000a431cdc01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674545608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3674545608
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.298813973
Short name T45
Test name
Test status
Simulation time 205778105555 ps
CPU time 88.72 seconds
Started May 23 03:25:55 PM PDT 24
Finished May 23 03:27:26 PM PDT 24
Peak memory 210532 kb
Host smart-3c1383c0-ae6e-47e1-a3ac-a670b9a195a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298813973 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.298813973
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2468527581
Short name T719
Test name
Test status
Simulation time 486729463 ps
CPU time 0.8 seconds
Started May 23 03:26:14 PM PDT 24
Finished May 23 03:26:17 PM PDT 24
Peak memory 201548 kb
Host smart-eca52472-d9c3-4d2a-856f-f65fdf440e31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468527581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2468527581
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3105424531
Short name T168
Test name
Test status
Simulation time 509172675408 ps
CPU time 139.63 seconds
Started May 23 03:26:12 PM PDT 24
Finished May 23 03:28:33 PM PDT 24
Peak memory 201828 kb
Host smart-166a3b6a-6abd-4184-8e15-8ba7d925b29e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105424531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3105424531
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3085106670
Short name T96
Test name
Test status
Simulation time 345187163915 ps
CPU time 745.05 seconds
Started May 23 03:26:14 PM PDT 24
Finished May 23 03:38:42 PM PDT 24
Peak memory 201784 kb
Host smart-fdc869c2-ed7b-4e5d-ba98-012c138a86ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085106670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3085106670
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1454475879
Short name T486
Test name
Test status
Simulation time 490427458807 ps
CPU time 309.85 seconds
Started May 23 03:25:58 PM PDT 24
Finished May 23 03:31:10 PM PDT 24
Peak memory 201848 kb
Host smart-75605e32-149c-4156-8c15-bc0ac279fe5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454475879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1454475879
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.750733805
Short name T157
Test name
Test status
Simulation time 328327102349 ps
CPU time 201.13 seconds
Started May 23 03:25:56 PM PDT 24
Finished May 23 03:29:19 PM PDT 24
Peak memory 201884 kb
Host smart-480ad7cc-05ae-4d9d-9631-ed656a86eb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750733805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.750733805
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1250072441
Short name T629
Test name
Test status
Simulation time 478485469468 ps
CPU time 283.82 seconds
Started May 23 03:25:56 PM PDT 24
Finished May 23 03:30:42 PM PDT 24
Peak memory 201888 kb
Host smart-4974983e-20ee-42ab-bd9a-f1cece19311f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250072441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1250072441
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.4114070055
Short name T605
Test name
Test status
Simulation time 338298727760 ps
CPU time 833.52 seconds
Started May 23 03:25:56 PM PDT 24
Finished May 23 03:39:52 PM PDT 24
Peak memory 201908 kb
Host smart-7eb09bc7-12f0-4b59-8642-61bd69e9ea23
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114070055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.4114070055
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1879272804
Short name T485
Test name
Test status
Simulation time 189902456734 ps
CPU time 441.68 seconds
Started May 23 03:26:13 PM PDT 24
Finished May 23 03:33:37 PM PDT 24
Peak memory 201844 kb
Host smart-a60b4a48-b1e2-476c-8343-b96c2b296821
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879272804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1879272804
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3099116030
Short name T92
Test name
Test status
Simulation time 82218489160 ps
CPU time 438.67 seconds
Started May 23 03:26:12 PM PDT 24
Finished May 23 03:33:34 PM PDT 24
Peak memory 202136 kb
Host smart-6a1d87e2-ba09-44d2-8c2e-a06485c0bdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099116030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3099116030
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3662448359
Short name T471
Test name
Test status
Simulation time 45704953515 ps
CPU time 105.91 seconds
Started May 23 03:26:14 PM PDT 24
Finished May 23 03:28:03 PM PDT 24
Peak memory 201628 kb
Host smart-acb79927-f572-42c0-a767-c27cfd7d948c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662448359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3662448359
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3625084684
Short name T545
Test name
Test status
Simulation time 3068194871 ps
CPU time 2.66 seconds
Started May 23 03:26:12 PM PDT 24
Finished May 23 03:26:17 PM PDT 24
Peak memory 201620 kb
Host smart-0d31b56a-3635-43c9-be2b-d066521eb27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625084684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3625084684
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2253861348
Short name T400
Test name
Test status
Simulation time 6011906981 ps
CPU time 8.43 seconds
Started May 23 03:25:58 PM PDT 24
Finished May 23 03:26:08 PM PDT 24
Peak memory 201672 kb
Host smart-4d393178-da67-4e67-937c-31b06b9cf4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253861348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2253861348
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.290545489
Short name T573
Test name
Test status
Simulation time 376929825358 ps
CPU time 253.78 seconds
Started May 23 03:26:12 PM PDT 24
Finished May 23 03:30:27 PM PDT 24
Peak memory 201804 kb
Host smart-93f45c86-babd-405e-9cf2-876fe44c2ed2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290545489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
290545489
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.4031097066
Short name T260
Test name
Test status
Simulation time 104492394997 ps
CPU time 138.89 seconds
Started May 23 03:26:14 PM PDT 24
Finished May 23 03:28:35 PM PDT 24
Peak memory 210496 kb
Host smart-f29f380d-dc6f-4e1b-a50a-31c212e2841e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031097066 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.4031097066
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2334672374
Short name T426
Test name
Test status
Simulation time 378078510 ps
CPU time 1.03 seconds
Started May 23 03:26:15 PM PDT 24
Finished May 23 03:26:19 PM PDT 24
Peak memory 201564 kb
Host smart-3c66f00d-c3b4-42cb-8c07-e7a5b5a2788b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334672374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2334672374
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3137070770
Short name T560
Test name
Test status
Simulation time 178121863875 ps
CPU time 98.62 seconds
Started May 23 03:26:12 PM PDT 24
Finished May 23 03:27:53 PM PDT 24
Peak memory 201856 kb
Host smart-80d4dc13-c4a8-4a4e-86ad-fe7adf33fcc6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137070770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3137070770
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3822200169
Short name T163
Test name
Test status
Simulation time 166769111870 ps
CPU time 69.08 seconds
Started May 23 03:26:12 PM PDT 24
Finished May 23 03:27:23 PM PDT 24
Peak memory 201844 kb
Host smart-7ccd0ae5-7168-435a-aeb8-ba5f9ae21512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822200169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3822200169
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2598171481
Short name T276
Test name
Test status
Simulation time 162899875713 ps
CPU time 86.59 seconds
Started May 23 03:26:14 PM PDT 24
Finished May 23 03:27:44 PM PDT 24
Peak memory 201840 kb
Host smart-c4bcfd06-d358-4314-8a53-431484200715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598171481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2598171481
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.884887612
Short name T787
Test name
Test status
Simulation time 171099923362 ps
CPU time 363.45 seconds
Started May 23 03:26:13 PM PDT 24
Finished May 23 03:32:19 PM PDT 24
Peak memory 201840 kb
Host smart-82a0a908-93d0-46de-bfbe-ee13513c26c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=884887612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.884887612
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2922320426
Short name T112
Test name
Test status
Simulation time 331863127620 ps
CPU time 141.81 seconds
Started May 23 03:26:16 PM PDT 24
Finished May 23 03:28:41 PM PDT 24
Peak memory 201932 kb
Host smart-d4231a99-72af-4212-80a4-7e3135ea4233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922320426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2922320426
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3384848638
Short name T368
Test name
Test status
Simulation time 495989896765 ps
CPU time 301.83 seconds
Started May 23 03:26:13 PM PDT 24
Finished May 23 03:31:18 PM PDT 24
Peak memory 201884 kb
Host smart-970db60e-d434-450f-9495-5951be703fad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384848638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3384848638
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2271406140
Short name T480
Test name
Test status
Simulation time 544306555626 ps
CPU time 1259.42 seconds
Started May 23 03:26:12 PM PDT 24
Finished May 23 03:47:14 PM PDT 24
Peak memory 201936 kb
Host smart-fca166ff-8d90-432a-9f28-4b0243b85abf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271406140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2271406140
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2707573223
Short name T688
Test name
Test status
Simulation time 596939291502 ps
CPU time 1386.9 seconds
Started May 23 03:26:14 PM PDT 24
Finished May 23 03:49:24 PM PDT 24
Peak memory 201832 kb
Host smart-3d3c08db-988d-4e03-956f-1e3fc7cd0ff9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707573223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2707573223
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3849546578
Short name T41
Test name
Test status
Simulation time 109138518278 ps
CPU time 365.01 seconds
Started May 23 03:26:11 PM PDT 24
Finished May 23 03:32:18 PM PDT 24
Peak memory 202152 kb
Host smart-fc110712-7636-4b1a-be15-9b7a1db01853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849546578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3849546578
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1940018625
Short name T612
Test name
Test status
Simulation time 36743568732 ps
CPU time 44.31 seconds
Started May 23 03:26:15 PM PDT 24
Finished May 23 03:27:02 PM PDT 24
Peak memory 201524 kb
Host smart-8b643e6c-a910-4c4e-af71-4045b4978b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940018625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1940018625
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2013865799
Short name T213
Test name
Test status
Simulation time 5101356924 ps
CPU time 3.7 seconds
Started May 23 03:26:13 PM PDT 24
Finished May 23 03:26:19 PM PDT 24
Peak memory 201660 kb
Host smart-069d1b7f-8fa2-482d-990b-2263ac952783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013865799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2013865799
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.14767780
Short name T416
Test name
Test status
Simulation time 5584695208 ps
CPU time 12.42 seconds
Started May 23 03:26:15 PM PDT 24
Finished May 23 03:26:30 PM PDT 24
Peak memory 201552 kb
Host smart-2d9145f3-ce8c-47b8-974c-98598d99b3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14767780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.14767780
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2909822731
Short name T707
Test name
Test status
Simulation time 174916080537 ps
CPU time 100.29 seconds
Started May 23 03:26:12 PM PDT 24
Finished May 23 03:27:55 PM PDT 24
Peak memory 201836 kb
Host smart-ae68a5f1-38ff-4b8b-b638-ed61f152b802
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909822731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2909822731
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3111162468
Short name T78
Test name
Test status
Simulation time 478914940 ps
CPU time 0.95 seconds
Started May 23 03:26:33 PM PDT 24
Finished May 23 03:26:36 PM PDT 24
Peak memory 201592 kb
Host smart-49b9b8b7-f4e4-4a3c-a5b6-09d598def314
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111162468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3111162468
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.4259021882
Short name T182
Test name
Test status
Simulation time 492138007048 ps
CPU time 157.93 seconds
Started May 23 03:26:33 PM PDT 24
Finished May 23 03:29:13 PM PDT 24
Peak memory 201860 kb
Host smart-9ff7f7c0-ae7a-4711-a7c7-ee188b181247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259021882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.4259021882
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.395066401
Short name T267
Test name
Test status
Simulation time 326364973155 ps
CPU time 365.27 seconds
Started May 23 03:26:33 PM PDT 24
Finished May 23 03:32:40 PM PDT 24
Peak memory 201844 kb
Host smart-e732c153-d7de-46ae-840d-31dc1a0ce83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395066401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.395066401
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2398297793
Short name T204
Test name
Test status
Simulation time 318301764379 ps
CPU time 712.2 seconds
Started May 23 03:26:33 PM PDT 24
Finished May 23 03:38:27 PM PDT 24
Peak memory 201828 kb
Host smart-475fc524-53b4-40c1-838d-2e1cde82d4d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398297793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2398297793
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.208942231
Short name T308
Test name
Test status
Simulation time 163646125160 ps
CPU time 376.18 seconds
Started May 23 03:26:12 PM PDT 24
Finished May 23 03:32:30 PM PDT 24
Peak memory 201844 kb
Host smart-176db809-1b23-4f27-80c9-50782eb46e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208942231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.208942231
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.386344516
Short name T13
Test name
Test status
Simulation time 494076085803 ps
CPU time 1099.6 seconds
Started May 23 03:26:32 PM PDT 24
Finished May 23 03:44:54 PM PDT 24
Peak memory 201848 kb
Host smart-f2898aea-bb86-4c4a-bdb2-0aa0cba3afde
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=386344516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.386344516
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.4167467955
Short name T580
Test name
Test status
Simulation time 183569689087 ps
CPU time 89.77 seconds
Started May 23 03:26:31 PM PDT 24
Finished May 23 03:28:03 PM PDT 24
Peak memory 201964 kb
Host smart-45d365bc-4958-453b-8b43-ab127e3835c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167467955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.4167467955
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.404578786
Short name T489
Test name
Test status
Simulation time 211611040306 ps
CPU time 139.4 seconds
Started May 23 03:26:32 PM PDT 24
Finished May 23 03:28:53 PM PDT 24
Peak memory 201840 kb
Host smart-3b38ea07-68e4-4553-a571-029f37cdfb0a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404578786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.404578786
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2448571951
Short name T754
Test name
Test status
Simulation time 101104616192 ps
CPU time 514.65 seconds
Started May 23 03:26:32 PM PDT 24
Finished May 23 03:35:09 PM PDT 24
Peak memory 202148 kb
Host smart-6ce38fd7-6dc0-4058-989f-5881e020ec22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448571951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2448571951
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.4250096598
Short name T410
Test name
Test status
Simulation time 36047789733 ps
CPU time 39.87 seconds
Started May 23 03:26:31 PM PDT 24
Finished May 23 03:27:12 PM PDT 24
Peak memory 201688 kb
Host smart-d3915aab-acc4-4511-98ae-d7c770f90a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250096598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.4250096598
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1335549820
Short name T90
Test name
Test status
Simulation time 5692378308 ps
CPU time 13.72 seconds
Started May 23 03:26:31 PM PDT 24
Finished May 23 03:26:46 PM PDT 24
Peak memory 201672 kb
Host smart-f3955f47-5231-4251-b839-15fef6e165cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335549820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1335549820
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.529856689
Short name T439
Test name
Test status
Simulation time 6113716462 ps
CPU time 2.37 seconds
Started May 23 03:26:15 PM PDT 24
Finished May 23 03:26:20 PM PDT 24
Peak memory 201648 kb
Host smart-90621aa2-3bd9-4321-b7a4-cb9ccaaed25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529856689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.529856689
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.4294883652
Short name T511
Test name
Test status
Simulation time 260665026476 ps
CPU time 419.12 seconds
Started May 23 03:26:32 PM PDT 24
Finished May 23 03:33:32 PM PDT 24
Peak memory 218584 kb
Host smart-685272dd-b30a-4735-86bc-afb5074a79c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294883652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.4294883652
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.616328222
Short name T595
Test name
Test status
Simulation time 123943201098 ps
CPU time 253.2 seconds
Started May 23 03:26:33 PM PDT 24
Finished May 23 03:30:48 PM PDT 24
Peak memory 210476 kb
Host smart-3182d5b4-6b87-4100-8617-648c9a01579b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616328222 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.616328222
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3029487934
Short name T510
Test name
Test status
Simulation time 490259054 ps
CPU time 0.89 seconds
Started May 23 03:26:59 PM PDT 24
Finished May 23 03:27:03 PM PDT 24
Peak memory 201460 kb
Host smart-3e16b5c7-d28c-426a-a9d1-fabde9fae89a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029487934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3029487934
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.886442844
Short name T311
Test name
Test status
Simulation time 352425626432 ps
CPU time 73.96 seconds
Started May 23 03:27:00 PM PDT 24
Finished May 23 03:28:18 PM PDT 24
Peak memory 201840 kb
Host smart-5153e5c1-40d0-405a-b64e-48ec44d10fac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886442844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.886442844
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3143461398
Short name T285
Test name
Test status
Simulation time 534157983930 ps
CPU time 1276.03 seconds
Started May 23 03:27:00 PM PDT 24
Finished May 23 03:48:20 PM PDT 24
Peak memory 201836 kb
Host smart-155f0baf-d3d5-4984-b274-8537f17a868b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143461398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3143461398
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1726786150
Short name T668
Test name
Test status
Simulation time 330188455833 ps
CPU time 179.17 seconds
Started May 23 03:26:32 PM PDT 24
Finished May 23 03:29:33 PM PDT 24
Peak memory 201788 kb
Host smart-f323f4a1-ce9a-4027-9a2e-70aa803cb482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726786150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1726786150
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.688710681
Short name T428
Test name
Test status
Simulation time 332079766325 ps
CPU time 211.8 seconds
Started May 23 03:26:31 PM PDT 24
Finished May 23 03:30:04 PM PDT 24
Peak memory 201820 kb
Host smart-7da3447e-cde3-48f9-9a2b-78d530d9c42e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=688710681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.688710681
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3070854723
Short name T771
Test name
Test status
Simulation time 166015362601 ps
CPU time 188.26 seconds
Started May 23 03:26:34 PM PDT 24
Finished May 23 03:29:44 PM PDT 24
Peak memory 201776 kb
Host smart-54aa6413-0417-4f88-b6eb-5ad8502dcb51
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070854723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3070854723
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.783573020
Short name T175
Test name
Test status
Simulation time 438849803400 ps
CPU time 364.89 seconds
Started May 23 03:26:30 PM PDT 24
Finished May 23 03:32:36 PM PDT 24
Peak memory 201848 kb
Host smart-206da462-b77a-450a-b22c-802a3bee75c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783573020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.783573020
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2873542839
Short name T405
Test name
Test status
Simulation time 604891131554 ps
CPU time 1412.25 seconds
Started May 23 03:26:32 PM PDT 24
Finished May 23 03:50:07 PM PDT 24
Peak memory 201860 kb
Host smart-1b2b4cff-612d-4d01-87ff-1eb165f75688
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873542839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2873542839
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.435452555
Short name T424
Test name
Test status
Simulation time 73289825795 ps
CPU time 420.74 seconds
Started May 23 03:27:01 PM PDT 24
Finished May 23 03:34:06 PM PDT 24
Peak memory 202140 kb
Host smart-e047f76d-097a-47df-89b6-fa28a31ee4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435452555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.435452555
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1797386366
Short name T499
Test name
Test status
Simulation time 30046106667 ps
CPU time 72.32 seconds
Started May 23 03:27:00 PM PDT 24
Finished May 23 03:28:16 PM PDT 24
Peak memory 201684 kb
Host smart-8f96f3b0-082b-463e-a39f-fc40a6142281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797386366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1797386366
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3997628407
Short name T617
Test name
Test status
Simulation time 4061043286 ps
CPU time 3.03 seconds
Started May 23 03:27:01 PM PDT 24
Finished May 23 03:27:08 PM PDT 24
Peak memory 201576 kb
Host smart-a9ec320b-3db5-42f1-ad34-8ce6943253b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997628407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3997628407
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2825305844
Short name T575
Test name
Test status
Simulation time 6124012242 ps
CPU time 3.68 seconds
Started May 23 03:26:33 PM PDT 24
Finished May 23 03:26:38 PM PDT 24
Peak memory 201660 kb
Host smart-1d97ff6f-7f4c-45c0-854d-9ef55f2f15a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825305844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2825305844
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1568614954
Short name T36
Test name
Test status
Simulation time 177220358940 ps
CPU time 640.36 seconds
Started May 23 03:26:59 PM PDT 24
Finished May 23 03:37:41 PM PDT 24
Peak memory 202168 kb
Host smart-81cda0ff-9254-47ae-b854-3ec57329354e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568614954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1568614954
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3792810918
Short name T18
Test name
Test status
Simulation time 152050386621 ps
CPU time 434.1 seconds
Started May 23 03:26:59 PM PDT 24
Finished May 23 03:34:16 PM PDT 24
Peak memory 210464 kb
Host smart-eca417ba-fae0-4c03-a16e-851ca5ea9bda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792810918 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3792810918
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3154000231
Short name T496
Test name
Test status
Simulation time 400635135 ps
CPU time 0.88 seconds
Started May 23 03:27:00 PM PDT 24
Finished May 23 03:27:05 PM PDT 24
Peak memory 201524 kb
Host smart-2b26a740-c167-4a5b-99f2-113d1abfe7b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154000231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3154000231
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.261772279
Short name T9
Test name
Test status
Simulation time 330117370664 ps
CPU time 363.28 seconds
Started May 23 03:27:01 PM PDT 24
Finished May 23 03:33:07 PM PDT 24
Peak memory 201864 kb
Host smart-669804c9-0fc7-44f7-8f67-0d2bc0d2cda9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261772279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.261772279
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3170540938
Short name T320
Test name
Test status
Simulation time 322110105776 ps
CPU time 185.26 seconds
Started May 23 03:27:05 PM PDT 24
Finished May 23 03:30:14 PM PDT 24
Peak memory 201680 kb
Host smart-b3513281-52e2-493d-98cb-50b203bd307a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170540938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3170540938
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.291816128
Short name T785
Test name
Test status
Simulation time 325194823360 ps
CPU time 818.14 seconds
Started May 23 03:27:05 PM PDT 24
Finished May 23 03:40:47 PM PDT 24
Peak memory 201704 kb
Host smart-35db7d1d-32f4-45ad-b220-a2ce0983793f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291816128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.291816128
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.614076440
Short name T630
Test name
Test status
Simulation time 498391527593 ps
CPU time 1169.31 seconds
Started May 23 03:27:01 PM PDT 24
Finished May 23 03:46:34 PM PDT 24
Peak memory 201828 kb
Host smart-9011ebc0-a4f5-4463-9ad2-ef8a5e0a7109
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=614076440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.614076440
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.669343292
Short name T603
Test name
Test status
Simulation time 325834772119 ps
CPU time 689.41 seconds
Started May 23 03:26:59 PM PDT 24
Finished May 23 03:38:32 PM PDT 24
Peak memory 201876 kb
Host smart-d98ef623-f9ea-4206-893b-e26e8fe0a291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669343292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.669343292
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1534209015
Short name T30
Test name
Test status
Simulation time 482541407121 ps
CPU time 91.69 seconds
Started May 23 03:27:01 PM PDT 24
Finished May 23 03:28:36 PM PDT 24
Peak memory 201772 kb
Host smart-9fdad823-a8d7-4cf4-9350-dddf1ee521aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534209015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1534209015
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1545925422
Short name T316
Test name
Test status
Simulation time 208497332624 ps
CPU time 210.47 seconds
Started May 23 03:26:59 PM PDT 24
Finished May 23 03:30:32 PM PDT 24
Peak memory 201920 kb
Host smart-8071bdaa-e110-4bc0-a9eb-3b2a2c403cf8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545925422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1545925422
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1561682753
Short name T176
Test name
Test status
Simulation time 601412275911 ps
CPU time 139.52 seconds
Started May 23 03:27:00 PM PDT 24
Finished May 23 03:29:24 PM PDT 24
Peak memory 201860 kb
Host smart-056d8aab-ca01-416a-b7ef-abf3814c531d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561682753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1561682753
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3138316458
Short name T682
Test name
Test status
Simulation time 124884932787 ps
CPU time 624.09 seconds
Started May 23 03:27:00 PM PDT 24
Finished May 23 03:37:27 PM PDT 24
Peak memory 202224 kb
Host smart-45978a89-f587-4055-b445-0eea540c2a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138316458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3138316458
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2702680222
Short name T671
Test name
Test status
Simulation time 33877794147 ps
CPU time 82.04 seconds
Started May 23 03:27:01 PM PDT 24
Finished May 23 03:28:27 PM PDT 24
Peak memory 201676 kb
Host smart-86e640e4-5001-46e4-a683-c9b42c9f113d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702680222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2702680222
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1033706940
Short name T449
Test name
Test status
Simulation time 4871404352 ps
CPU time 12.36 seconds
Started May 23 03:27:00 PM PDT 24
Finished May 23 03:27:15 PM PDT 24
Peak memory 201636 kb
Host smart-41422b21-7089-4531-ad63-460a0ba7978c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033706940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1033706940
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.550945839
Short name T678
Test name
Test status
Simulation time 5987799569 ps
CPU time 4.19 seconds
Started May 23 03:27:00 PM PDT 24
Finished May 23 03:27:08 PM PDT 24
Peak memory 201668 kb
Host smart-56df4b2c-6f86-49ce-89a2-54b9aa906c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550945839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.550945839
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.734919281
Short name T556
Test name
Test status
Simulation time 6365988700 ps
CPU time 12.28 seconds
Started May 23 03:27:04 PM PDT 24
Finished May 23 03:27:21 PM PDT 24
Peak memory 201664 kb
Host smart-aeb50e5f-f595-45b3-b008-631c0f592f31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734919281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
734919281
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2173360677
Short name T653
Test name
Test status
Simulation time 120829455616 ps
CPU time 124.97 seconds
Started May 23 03:27:00 PM PDT 24
Finished May 23 03:29:08 PM PDT 24
Peak memory 217780 kb
Host smart-4920a7e8-6fce-498b-838f-790ed1898db3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173360677 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2173360677
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.3279905527
Short name T543
Test name
Test status
Simulation time 484406347 ps
CPU time 0.94 seconds
Started May 23 03:21:49 PM PDT 24
Finished May 23 03:21:51 PM PDT 24
Peak memory 201500 kb
Host smart-b23e7e28-92cb-4cbf-ac09-3951fa7b652a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279905527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.3279905527
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.425946309
Short name T589
Test name
Test status
Simulation time 162325834897 ps
CPU time 129.38 seconds
Started May 23 03:21:41 PM PDT 24
Finished May 23 03:23:52 PM PDT 24
Peak memory 201864 kb
Host smart-75c8c22b-da6d-493b-b2e8-192b3e323fe9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425946309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.425946309
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3074007370
Short name T272
Test name
Test status
Simulation time 165009252296 ps
CPU time 103.31 seconds
Started May 23 03:21:49 PM PDT 24
Finished May 23 03:23:34 PM PDT 24
Peak memory 201924 kb
Host smart-5010c654-b6b1-4ade-8852-7a3e9a5f0dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074007370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3074007370
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2612487019
Short name T631
Test name
Test status
Simulation time 330550604031 ps
CPU time 133.99 seconds
Started May 23 03:21:39 PM PDT 24
Finished May 23 03:23:54 PM PDT 24
Peak memory 201820 kb
Host smart-3e844a9f-3154-4c61-8b8b-6a55836efed1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612487019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2612487019
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1988032378
Short name T148
Test name
Test status
Simulation time 489210010659 ps
CPU time 1151.07 seconds
Started May 23 03:21:40 PM PDT 24
Finished May 23 03:40:53 PM PDT 24
Peak memory 201788 kb
Host smart-67a484f0-48f9-4d78-9f5f-1e2a1afd2339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988032378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1988032378
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3655801962
Short name T379
Test name
Test status
Simulation time 326286540039 ps
CPU time 101.49 seconds
Started May 23 03:21:50 PM PDT 24
Finished May 23 03:23:32 PM PDT 24
Peak memory 201780 kb
Host smart-370c537a-f697-48dc-89ca-f876067e8d19
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655801962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3655801962
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.548689251
Short name T261
Test name
Test status
Simulation time 226830820245 ps
CPU time 523.31 seconds
Started May 23 03:21:51 PM PDT 24
Finished May 23 03:30:36 PM PDT 24
Peak memory 201908 kb
Host smart-56094729-1c88-4b0b-bd7e-71ca738cfac6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548689251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.548689251
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2438537044
Short name T538
Test name
Test status
Simulation time 599802053953 ps
CPU time 699.15 seconds
Started May 23 03:21:50 PM PDT 24
Finished May 23 03:33:30 PM PDT 24
Peak memory 201844 kb
Host smart-ed1ece99-bbac-4c57-b6ec-197654ee47c1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438537044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2438537044
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2373986865
Short name T660
Test name
Test status
Simulation time 119490617571 ps
CPU time 501.58 seconds
Started May 23 03:21:43 PM PDT 24
Finished May 23 03:30:06 PM PDT 24
Peak memory 202276 kb
Host smart-2cb8cb78-6e99-429d-8744-58686be3eb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373986865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2373986865
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.3993316089
Short name T706
Test name
Test status
Simulation time 29247637607 ps
CPU time 23.14 seconds
Started May 23 03:21:41 PM PDT 24
Finished May 23 03:22:06 PM PDT 24
Peak memory 201624 kb
Host smart-3229d117-1cef-4fd3-a60e-65e112b1a084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993316089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3993316089
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3280908250
Short name T588
Test name
Test status
Simulation time 4641626153 ps
CPU time 3.59 seconds
Started May 23 03:21:39 PM PDT 24
Finished May 23 03:21:44 PM PDT 24
Peak memory 201656 kb
Host smart-d15a1aae-3a6a-4075-adb5-16a772192723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280908250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3280908250
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.65029577
Short name T82
Test name
Test status
Simulation time 7636870502 ps
CPU time 9.65 seconds
Started May 23 03:21:50 PM PDT 24
Finished May 23 03:22:00 PM PDT 24
Peak memory 217400 kb
Host smart-5d31bd33-b403-4b70-b452-658d4da782fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65029577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.65029577
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2118123907
Short name T88
Test name
Test status
Simulation time 5834272566 ps
CPU time 6.51 seconds
Started May 23 03:21:49 PM PDT 24
Finished May 23 03:21:57 PM PDT 24
Peak memory 201648 kb
Host smart-87b89251-c21f-466c-b4f4-c864ee50a75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118123907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2118123907
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3339554781
Short name T37
Test name
Test status
Simulation time 318837640303 ps
CPU time 582.43 seconds
Started May 23 03:21:44 PM PDT 24
Finished May 23 03:31:28 PM PDT 24
Peak memory 202184 kb
Host smart-08a8e1c8-8d9a-4869-bfc7-51e04437046c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339554781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3339554781
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3040085125
Short name T265
Test name
Test status
Simulation time 219365031884 ps
CPU time 405.98 seconds
Started May 23 03:21:40 PM PDT 24
Finished May 23 03:28:27 PM PDT 24
Peak memory 210448 kb
Host smart-c4f609ab-ed72-448c-9e64-aefa95e587cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040085125 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3040085125
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2958674208
Short name T465
Test name
Test status
Simulation time 334637540 ps
CPU time 0.81 seconds
Started May 23 03:27:14 PM PDT 24
Finished May 23 03:27:19 PM PDT 24
Peak memory 201516 kb
Host smart-4a72076c-83dd-4ac3-825a-3f6e4cd33c6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958674208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2958674208
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3802605139
Short name T183
Test name
Test status
Simulation time 491700859190 ps
CPU time 203.11 seconds
Started May 23 03:27:17 PM PDT 24
Finished May 23 03:30:45 PM PDT 24
Peak memory 201888 kb
Host smart-2adb20ee-c833-4f42-b194-b12d96898e88
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802605139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3802605139
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1048466406
Short name T330
Test name
Test status
Simulation time 569117334928 ps
CPU time 1379.64 seconds
Started May 23 03:27:12 PM PDT 24
Finished May 23 03:50:17 PM PDT 24
Peak memory 201816 kb
Host smart-672e3c38-87ef-4e9f-a1f5-5b964b3c41de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048466406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1048466406
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3911029630
Short name T649
Test name
Test status
Simulation time 330524789591 ps
CPU time 481.4 seconds
Started May 23 03:27:13 PM PDT 24
Finished May 23 03:35:19 PM PDT 24
Peak memory 201856 kb
Host smart-d9ee361b-36ac-484b-bf1a-a447660813e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911029630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3911029630
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.737625229
Short name T730
Test name
Test status
Simulation time 492114900675 ps
CPU time 1100.38 seconds
Started May 23 03:27:13 PM PDT 24
Finished May 23 03:45:38 PM PDT 24
Peak memory 201844 kb
Host smart-e8196c45-a9d8-4518-a4b2-84af13a6c4fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=737625229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.737625229
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3522971113
Short name T644
Test name
Test status
Simulation time 500667025887 ps
CPU time 317.05 seconds
Started May 23 03:27:00 PM PDT 24
Finished May 23 03:32:21 PM PDT 24
Peak memory 201772 kb
Host smart-d98645e1-3096-47b1-bd95-58237591fc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522971113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3522971113
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.1138621335
Short name T473
Test name
Test status
Simulation time 161689311443 ps
CPU time 63.36 seconds
Started May 23 03:27:12 PM PDT 24
Finished May 23 03:28:20 PM PDT 24
Peak memory 201812 kb
Host smart-a6e49f9c-b1c0-4ce6-90b9-d1afe33c2c1a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138621335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.1138621335
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.4173426025
Short name T398
Test name
Test status
Simulation time 393929932430 ps
CPU time 932.58 seconds
Started May 23 03:27:11 PM PDT 24
Finished May 23 03:42:49 PM PDT 24
Peak memory 201828 kb
Host smart-e3f64094-538e-4421-88b2-fc8b1ff39485
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173426025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.4173426025
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1024821995
Short name T633
Test name
Test status
Simulation time 105151155768 ps
CPU time 591.48 seconds
Started May 23 03:27:12 PM PDT 24
Finished May 23 03:37:09 PM PDT 24
Peak memory 202120 kb
Host smart-f2631be6-6c45-468f-9faa-e38839f46fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024821995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1024821995
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1796526014
Short name T470
Test name
Test status
Simulation time 41777159045 ps
CPU time 27.08 seconds
Started May 23 03:27:15 PM PDT 24
Finished May 23 03:27:47 PM PDT 24
Peak memory 201636 kb
Host smart-cd1b4a11-6ad8-4727-9150-5d6de3c45ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796526014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1796526014
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2815839527
Short name T725
Test name
Test status
Simulation time 2976509811 ps
CPU time 2.25 seconds
Started May 23 03:27:14 PM PDT 24
Finished May 23 03:27:21 PM PDT 24
Peak memory 201620 kb
Host smart-d905eec3-83e0-4683-85b7-695ac587354d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815839527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2815839527
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1924572678
Short name T587
Test name
Test status
Simulation time 5906708974 ps
CPU time 4.1 seconds
Started May 23 03:27:00 PM PDT 24
Finished May 23 03:27:07 PM PDT 24
Peak memory 201688 kb
Host smart-6d294499-fec1-472b-bc3f-5267ef039a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924572678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1924572678
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1130271540
Short name T363
Test name
Test status
Simulation time 351338228781 ps
CPU time 849.5 seconds
Started May 23 03:27:17 PM PDT 24
Finished May 23 03:41:31 PM PDT 24
Peak memory 202196 kb
Host smart-5039b406-b386-46c5-9aa5-ae8ad109142c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130271540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1130271540
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.81783419
Short name T48
Test name
Test status
Simulation time 128326405536 ps
CPU time 85.66 seconds
Started May 23 03:27:17 PM PDT 24
Finished May 23 03:28:47 PM PDT 24
Peak memory 210580 kb
Host smart-e04103d4-61ea-4697-9cef-31d0862393fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81783419 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.81783419
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.799704313
Short name T714
Test name
Test status
Simulation time 535947261 ps
CPU time 1.24 seconds
Started May 23 03:27:13 PM PDT 24
Finished May 23 03:27:18 PM PDT 24
Peak memory 201496 kb
Host smart-99755b23-d176-4129-9cea-8646ceb5502b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799704313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.799704313
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.536012912
Short name T700
Test name
Test status
Simulation time 420792016406 ps
CPU time 176.13 seconds
Started May 23 03:27:16 PM PDT 24
Finished May 23 03:30:17 PM PDT 24
Peak memory 201844 kb
Host smart-18470d2f-430c-4510-8b80-1d374b7a690f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536012912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati
ng.536012912
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.823224641
Short name T248
Test name
Test status
Simulation time 354306950021 ps
CPU time 69.15 seconds
Started May 23 03:27:14 PM PDT 24
Finished May 23 03:28:27 PM PDT 24
Peak memory 201828 kb
Host smart-0f12a7b5-119d-430b-9cfb-5d0a40d768e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823224641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.823224641
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.915846042
Short name T334
Test name
Test status
Simulation time 323102345031 ps
CPU time 784.84 seconds
Started May 23 03:27:15 PM PDT 24
Finished May 23 03:40:25 PM PDT 24
Peak memory 201764 kb
Host smart-2cb75606-a73e-4c8e-9806-2679eb860f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915846042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.915846042
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.13663274
Short name T542
Test name
Test status
Simulation time 159891551888 ps
CPU time 96.75 seconds
Started May 23 03:27:17 PM PDT 24
Finished May 23 03:28:58 PM PDT 24
Peak memory 201840 kb
Host smart-a0f74e15-b03a-4e7d-b867-8473e252fbc0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=13663274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt
_fixed.13663274
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2047856763
Short name T744
Test name
Test status
Simulation time 494352073345 ps
CPU time 568.03 seconds
Started May 23 03:27:15 PM PDT 24
Finished May 23 03:36:48 PM PDT 24
Peak memory 201748 kb
Host smart-ead574d1-f914-495b-941f-b8617f4ddc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047856763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2047856763
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.523288077
Short name T530
Test name
Test status
Simulation time 488528424480 ps
CPU time 1230.64 seconds
Started May 23 03:27:14 PM PDT 24
Finished May 23 03:47:50 PM PDT 24
Peak memory 201808 kb
Host smart-00bae578-28b4-4744-b7b7-a1242f86de33
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=523288077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixe
d.523288077
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.603401479
Short name T716
Test name
Test status
Simulation time 168893005172 ps
CPU time 407.24 seconds
Started May 23 03:27:17 PM PDT 24
Finished May 23 03:34:09 PM PDT 24
Peak memory 201864 kb
Host smart-ae0c1a4f-09b5-4930-bd59-72f3025dd99e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603401479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.603401479
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.587055325
Short name T756
Test name
Test status
Simulation time 198857978075 ps
CPU time 476.78 seconds
Started May 23 03:27:18 PM PDT 24
Finished May 23 03:35:19 PM PDT 24
Peak memory 201848 kb
Host smart-b8e5b180-5b9b-438e-9d08-40713096ec83
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587055325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.587055325
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.396629156
Short name T116
Test name
Test status
Simulation time 72112907029 ps
CPU time 296.96 seconds
Started May 23 03:27:18 PM PDT 24
Finished May 23 03:32:19 PM PDT 24
Peak memory 202160 kb
Host smart-05988f7d-16d7-40c3-b3c7-e8b3eaa05ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396629156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.396629156
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2812702055
Short name T454
Test name
Test status
Simulation time 41601936491 ps
CPU time 33.06 seconds
Started May 23 03:27:17 PM PDT 24
Finished May 23 03:27:55 PM PDT 24
Peak memory 201668 kb
Host smart-2fccf9cf-f899-4dca-a036-845679174fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812702055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2812702055
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1644788270
Short name T562
Test name
Test status
Simulation time 4073972896 ps
CPU time 9.82 seconds
Started May 23 03:27:16 PM PDT 24
Finished May 23 03:27:31 PM PDT 24
Peak memory 201604 kb
Host smart-13168a30-e074-44f7-9222-531326042d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644788270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1644788270
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3822887191
Short name T600
Test name
Test status
Simulation time 6098126374 ps
CPU time 8.37 seconds
Started May 23 03:27:17 PM PDT 24
Finished May 23 03:27:30 PM PDT 24
Peak memory 201676 kb
Host smart-33c44af0-0f93-46b9-8aae-874abdac14ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822887191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3822887191
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.3291452550
Short name T38
Test name
Test status
Simulation time 316478000427 ps
CPU time 1088.76 seconds
Started May 23 03:27:14 PM PDT 24
Finished May 23 03:45:27 PM PDT 24
Peak memory 213512 kb
Host smart-50acb5aa-8369-4aef-a1f1-975e6edc3318
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291452550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.3291452550
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1416947261
Short name T479
Test name
Test status
Simulation time 378573991 ps
CPU time 0.8 seconds
Started May 23 03:27:29 PM PDT 24
Finished May 23 03:27:32 PM PDT 24
Peak memory 201528 kb
Host smart-8f316dd0-7d3b-465d-ae1a-332d19eb0880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416947261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1416947261
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1377175719
Short name T209
Test name
Test status
Simulation time 365263188603 ps
CPU time 31.85 seconds
Started May 23 03:27:28 PM PDT 24
Finished May 23 03:28:01 PM PDT 24
Peak memory 201916 kb
Host smart-cdff26dc-4b74-48eb-aefa-18c948f23290
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377175719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1377175719
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3231401381
Short name T323
Test name
Test status
Simulation time 351916995433 ps
CPU time 814.03 seconds
Started May 23 03:27:28 PM PDT 24
Finished May 23 03:41:05 PM PDT 24
Peak memory 201852 kb
Host smart-5162c347-f136-4511-ae30-c50682b00d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231401381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3231401381
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1388361483
Short name T268
Test name
Test status
Simulation time 162765704065 ps
CPU time 375.69 seconds
Started May 23 03:27:29 PM PDT 24
Finished May 23 03:33:47 PM PDT 24
Peak memory 201832 kb
Host smart-9c1852cd-3b05-4b58-bee9-4c4d2b9220c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388361483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1388361483
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3431762128
Short name T11
Test name
Test status
Simulation time 170747113078 ps
CPU time 418.08 seconds
Started May 23 03:27:29 PM PDT 24
Finished May 23 03:34:29 PM PDT 24
Peak memory 201832 kb
Host smart-82b41064-6ea9-4e58-acdd-f601d2bf0bf5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431762128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3431762128
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.86903330
Short name T219
Test name
Test status
Simulation time 330607049198 ps
CPU time 166 seconds
Started May 23 03:27:31 PM PDT 24
Finished May 23 03:30:19 PM PDT 24
Peak memory 201884 kb
Host smart-2c4d36b0-7687-4a3e-af73-407508715177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86903330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.86903330
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2251687244
Short name T628
Test name
Test status
Simulation time 164150785308 ps
CPU time 202.56 seconds
Started May 23 03:27:28 PM PDT 24
Finished May 23 03:30:52 PM PDT 24
Peak memory 201820 kb
Host smart-76b7ed10-27f5-433a-93b1-9e093247fe92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251687244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2251687244
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1845611040
Short name T550
Test name
Test status
Simulation time 196715166683 ps
CPU time 469.32 seconds
Started May 23 03:27:28 PM PDT 24
Finished May 23 03:35:20 PM PDT 24
Peak memory 201856 kb
Host smart-e0f4406e-4dd4-47e4-99c4-5f3148c74cc1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845611040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1845611040
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1258003938
Short name T85
Test name
Test status
Simulation time 83173853964 ps
CPU time 481.4 seconds
Started May 23 03:27:28 PM PDT 24
Finished May 23 03:35:31 PM PDT 24
Peak memory 202132 kb
Host smart-a924cce9-b7f0-4c12-b4d1-aa20b7172893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258003938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1258003938
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.945122690
Short name T541
Test name
Test status
Simulation time 40840972446 ps
CPU time 94.69 seconds
Started May 23 03:27:28 PM PDT 24
Finished May 23 03:29:05 PM PDT 24
Peak memory 201648 kb
Host smart-84532825-5f1c-45e9-bd23-621249449539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945122690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.945122690
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2422216767
Short name T606
Test name
Test status
Simulation time 4150485955 ps
CPU time 3.64 seconds
Started May 23 03:27:31 PM PDT 24
Finished May 23 03:27:37 PM PDT 24
Peak memory 201588 kb
Host smart-9dcf81b0-2ff1-42ec-a6f9-1674a078633e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422216767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2422216767
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3879644010
Short name T6
Test name
Test status
Simulation time 5693644529 ps
CPU time 13.08 seconds
Started May 23 03:27:17 PM PDT 24
Finished May 23 03:27:34 PM PDT 24
Peak memory 201688 kb
Host smart-a50d8f1d-1121-423e-8614-83410882e884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879644010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3879644010
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2374807961
Short name T583
Test name
Test status
Simulation time 489342771149 ps
CPU time 138.93 seconds
Started May 23 03:27:28 PM PDT 24
Finished May 23 03:29:48 PM PDT 24
Peak memory 201840 kb
Host smart-cfe938a7-8c3d-419d-bf40-0d3e0bc691b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374807961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2374807961
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2960611904
Short name T44
Test name
Test status
Simulation time 33273990864 ps
CPU time 70 seconds
Started May 23 03:27:30 PM PDT 24
Finished May 23 03:28:42 PM PDT 24
Peak memory 210156 kb
Host smart-7ce8c0ab-6d7f-4e80-ba61-768acd0efb66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960611904 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2960611904
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.216880528
Short name T665
Test name
Test status
Simulation time 515992407 ps
CPU time 1.16 seconds
Started May 23 03:28:11 PM PDT 24
Finished May 23 03:28:15 PM PDT 24
Peak memory 201552 kb
Host smart-977546e4-d54c-40f7-8046-0325ffd69759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216880528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.216880528
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1836828128
Short name T243
Test name
Test status
Simulation time 163713158506 ps
CPU time 154.83 seconds
Started May 23 03:28:11 PM PDT 24
Finished May 23 03:30:50 PM PDT 24
Peak memory 201868 kb
Host smart-2e0445e3-8cd8-4666-98eb-91d3e271f34d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836828128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1836828128
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2561779848
Short name T257
Test name
Test status
Simulation time 162076059205 ps
CPU time 94.34 seconds
Started May 23 03:28:11 PM PDT 24
Finished May 23 03:29:49 PM PDT 24
Peak memory 201900 kb
Host smart-de141bab-a8eb-4eed-908a-b845fdd2437f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561779848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2561779848
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2756275265
Short name T153
Test name
Test status
Simulation time 169589667518 ps
CPU time 26.26 seconds
Started May 23 03:28:11 PM PDT 24
Finished May 23 03:28:40 PM PDT 24
Peak memory 201832 kb
Host smart-5fc3f4b9-72da-41c3-b9d5-36fae4a2d286
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756275265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2756275265
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1673926890
Short name T443
Test name
Test status
Simulation time 164305488645 ps
CPU time 368.95 seconds
Started May 23 03:27:31 PM PDT 24
Finished May 23 03:33:42 PM PDT 24
Peak memory 201888 kb
Host smart-a02d15be-bc00-498e-be34-db9354161cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673926890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1673926890
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3404387051
Short name T527
Test name
Test status
Simulation time 491300862647 ps
CPU time 122 seconds
Started May 23 03:28:09 PM PDT 24
Finished May 23 03:30:12 PM PDT 24
Peak memory 201800 kb
Host smart-1e05f3c8-59c4-462d-ac8c-a5f42890cd87
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404387051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3404387051
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1131961794
Short name T283
Test name
Test status
Simulation time 564490380998 ps
CPU time 636.94 seconds
Started May 23 03:28:10 PM PDT 24
Finished May 23 03:38:50 PM PDT 24
Peak memory 201868 kb
Host smart-4b53ad38-e5fd-4ad6-9642-269443ac8c72
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131961794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1131961794
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.28746674
Short name T435
Test name
Test status
Simulation time 404669341832 ps
CPU time 914.68 seconds
Started May 23 03:28:10 PM PDT 24
Finished May 23 03:43:28 PM PDT 24
Peak memory 201836 kb
Host smart-20acc7d2-4e21-420b-b245-15d21e33abbc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28746674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.a
dc_ctrl_filters_wakeup_fixed.28746674
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.651166511
Short name T233
Test name
Test status
Simulation time 108472617520 ps
CPU time 554.72 seconds
Started May 23 03:28:11 PM PDT 24
Finished May 23 03:37:29 PM PDT 24
Peak memory 202236 kb
Host smart-010d17bd-fc98-4750-9a03-3d94fc4f4723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651166511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.651166511
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1399509461
Short name T667
Test name
Test status
Simulation time 38412965426 ps
CPU time 92.59 seconds
Started May 23 03:28:11 PM PDT 24
Finished May 23 03:29:47 PM PDT 24
Peak memory 201688 kb
Host smart-8d6c5a32-04a1-4d3c-85bb-896dd59267f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399509461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1399509461
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.4100677447
Short name T712
Test name
Test status
Simulation time 4427276060 ps
CPU time 5.75 seconds
Started May 23 03:28:10 PM PDT 24
Finished May 23 03:28:19 PM PDT 24
Peak memory 201652 kb
Host smart-65782fda-03cc-46d2-ac50-f6dc335e0f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100677447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.4100677447
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3730058745
Short name T659
Test name
Test status
Simulation time 6081524152 ps
CPU time 13.56 seconds
Started May 23 03:27:29 PM PDT 24
Finished May 23 03:27:44 PM PDT 24
Peak memory 201668 kb
Host smart-ad51a655-e90f-4580-acef-1962028b8d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730058745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3730058745
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2941528887
Short name T109
Test name
Test status
Simulation time 131584140002 ps
CPU time 638.41 seconds
Started May 23 03:28:10 PM PDT 24
Finished May 23 03:38:52 PM PDT 24
Peak memory 210264 kb
Host smart-d9ce133e-de8c-4626-8558-988e041e2ce9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941528887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2941528887
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.194733957
Short name T23
Test name
Test status
Simulation time 1361763390058 ps
CPU time 91.26 seconds
Started May 23 03:28:10 PM PDT 24
Finished May 23 03:29:45 PM PDT 24
Peak memory 210460 kb
Host smart-11b9fbc1-1162-4b44-87e9-27682b3ff65a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194733957 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.194733957
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3347942927
Short name T407
Test name
Test status
Simulation time 358445173 ps
CPU time 0.86 seconds
Started May 23 03:28:11 PM PDT 24
Finished May 23 03:28:16 PM PDT 24
Peak memory 201524 kb
Host smart-fe3cfb22-6765-4e12-8fa1-935aa962a482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347942927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3347942927
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1340354203
Short name T547
Test name
Test status
Simulation time 190011314584 ps
CPU time 466.04 seconds
Started May 23 03:28:11 PM PDT 24
Finished May 23 03:36:00 PM PDT 24
Peak memory 201904 kb
Host smart-075263fa-3d02-47ee-a1d6-9b4b1e037e1c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340354203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1340354203
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3534126434
Short name T686
Test name
Test status
Simulation time 325510512578 ps
CPU time 804.13 seconds
Started May 23 03:28:10 PM PDT 24
Finished May 23 03:41:36 PM PDT 24
Peak memory 201908 kb
Host smart-3bc023d0-4aad-4063-bea5-daf2a30c27d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534126434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3534126434
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3568477569
Short name T596
Test name
Test status
Simulation time 161112529616 ps
CPU time 26.52 seconds
Started May 23 03:28:10 PM PDT 24
Finished May 23 03:28:39 PM PDT 24
Peak memory 201920 kb
Host smart-cf952fa7-efb6-4a08-9d4e-d9e1ea5243a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568477569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3568477569
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3908969810
Short name T399
Test name
Test status
Simulation time 483429711244 ps
CPU time 183.05 seconds
Started May 23 03:28:11 PM PDT 24
Finished May 23 03:31:17 PM PDT 24
Peak memory 201808 kb
Host smart-b54cc4e7-ea37-4253-9fbd-1d73e3e51d91
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908969810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3908969810
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2567983649
Short name T571
Test name
Test status
Simulation time 162697884583 ps
CPU time 395.5 seconds
Started May 23 03:28:10 PM PDT 24
Finished May 23 03:34:49 PM PDT 24
Peak memory 201816 kb
Host smart-281498c4-99b0-4b51-8473-89d041360013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567983649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2567983649
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.4032658823
Short name T383
Test name
Test status
Simulation time 164007636411 ps
CPU time 205.57 seconds
Started May 23 03:28:11 PM PDT 24
Finished May 23 03:31:40 PM PDT 24
Peak memory 201788 kb
Host smart-e6840042-836d-41e5-9ff8-5ab5c83d2e1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032658823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.4032658823
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2288119349
Short name T300
Test name
Test status
Simulation time 358503157460 ps
CPU time 762.62 seconds
Started May 23 03:28:09 PM PDT 24
Finished May 23 03:40:54 PM PDT 24
Peak memory 201864 kb
Host smart-3c6e65e9-e045-4859-8d9f-ad9dee49585d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288119349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2288119349
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1210223751
Short name T555
Test name
Test status
Simulation time 619639686504 ps
CPU time 330.66 seconds
Started May 23 03:28:11 PM PDT 24
Finished May 23 03:33:46 PM PDT 24
Peak memory 201880 kb
Host smart-a83b5d9f-1f37-415a-858a-78707d9cc20b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210223751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1210223751
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2089181354
Short name T564
Test name
Test status
Simulation time 84023021707 ps
CPU time 380.24 seconds
Started May 23 03:28:11 PM PDT 24
Finished May 23 03:34:34 PM PDT 24
Peak memory 202164 kb
Host smart-b0a3b44a-3162-4bda-a4fb-df796b333e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089181354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2089181354
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3884776158
Short name T762
Test name
Test status
Simulation time 28359679503 ps
CPU time 65.73 seconds
Started May 23 03:28:11 PM PDT 24
Finished May 23 03:29:20 PM PDT 24
Peak memory 201668 kb
Host smart-b50829a2-360e-46df-9b19-997bcdf3c4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884776158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3884776158
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.741536447
Short name T627
Test name
Test status
Simulation time 3419090551 ps
CPU time 2.71 seconds
Started May 23 03:28:10 PM PDT 24
Finished May 23 03:28:16 PM PDT 24
Peak memory 201604 kb
Host smart-499566a2-32b0-455d-84d3-93a5b7e750b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741536447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.741536447
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.594265891
Short name T170
Test name
Test status
Simulation time 6174286658 ps
CPU time 4.69 seconds
Started May 23 03:28:12 PM PDT 24
Finished May 23 03:28:21 PM PDT 24
Peak memory 201660 kb
Host smart-537ce0f8-a0cf-43f6-9152-ac0c16317fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594265891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.594265891
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.339004236
Short name T751
Test name
Test status
Simulation time 90427333739 ps
CPU time 359.13 seconds
Started May 23 03:28:10 PM PDT 24
Finished May 23 03:34:13 PM PDT 24
Peak memory 210352 kb
Host smart-becf4d4c-40fd-406f-9646-892591ca7ea5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339004236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
339004236
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3591030940
Short name T199
Test name
Test status
Simulation time 40441190910 ps
CPU time 90.92 seconds
Started May 23 03:28:10 PM PDT 24
Finished May 23 03:29:45 PM PDT 24
Peak memory 210220 kb
Host smart-462edf4b-42cc-4de2-9ef8-d4da5f498655
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591030940 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3591030940
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2813193098
Short name T452
Test name
Test status
Simulation time 456561015 ps
CPU time 1.69 seconds
Started May 23 03:28:28 PM PDT 24
Finished May 23 03:28:32 PM PDT 24
Peak memory 201528 kb
Host smart-3946a65b-febb-4ac3-aadf-af3a6b3d0465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813193098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2813193098
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1169752835
Short name T739
Test name
Test status
Simulation time 204457772073 ps
CPU time 135.46 seconds
Started May 23 03:28:29 PM PDT 24
Finished May 23 03:30:46 PM PDT 24
Peak memory 201840 kb
Host smart-e98248f0-2094-449a-8b97-4e2fa09058d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169752835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1169752835
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.4151469392
Short name T540
Test name
Test status
Simulation time 327261154207 ps
CPU time 840.1 seconds
Started May 23 03:28:29 PM PDT 24
Finished May 23 03:42:30 PM PDT 24
Peak memory 201852 kb
Host smart-0584e1c6-de41-4246-b802-38c58eb10371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151469392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.4151469392
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3555023031
Short name T503
Test name
Test status
Simulation time 325253321707 ps
CPU time 321.59 seconds
Started May 23 03:28:29 PM PDT 24
Finished May 23 03:33:53 PM PDT 24
Peak memory 201844 kb
Host smart-e9e75593-a57c-47e6-873c-431e126aaa9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555023031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3555023031
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2089106252
Short name T208
Test name
Test status
Simulation time 326885323764 ps
CPU time 249.25 seconds
Started May 23 03:28:28 PM PDT 24
Finished May 23 03:32:39 PM PDT 24
Peak memory 201848 kb
Host smart-04d3b427-5d9e-4a70-94d3-dcf681440b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089106252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2089106252
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.470436418
Short name T492
Test name
Test status
Simulation time 167888039093 ps
CPU time 102.96 seconds
Started May 23 03:28:27 PM PDT 24
Finished May 23 03:30:11 PM PDT 24
Peak memory 201860 kb
Host smart-0f303300-25f3-445e-8c37-94fdd39d13ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=470436418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.470436418
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.323545209
Short name T50
Test name
Test status
Simulation time 187741785675 ps
CPU time 445.6 seconds
Started May 23 03:28:30 PM PDT 24
Finished May 23 03:35:57 PM PDT 24
Peak memory 201852 kb
Host smart-3b9b29d5-5797-46ad-b92e-61a3b168f8bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323545209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.323545209
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2511089093
Short name T680
Test name
Test status
Simulation time 615807820784 ps
CPU time 372.08 seconds
Started May 23 03:28:29 PM PDT 24
Finished May 23 03:34:43 PM PDT 24
Peak memory 201832 kb
Host smart-e8dbae1e-cddc-413c-8819-8f23874bd181
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511089093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2511089093
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.579861391
Short name T229
Test name
Test status
Simulation time 110900318605 ps
CPU time 543.8 seconds
Started May 23 03:28:29 PM PDT 24
Finished May 23 03:37:34 PM PDT 24
Peak memory 202240 kb
Host smart-466b232a-1107-4a3b-adcc-549a2d2a8cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579861391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.579861391
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.742005124
Short name T456
Test name
Test status
Simulation time 45239788180 ps
CPU time 38.66 seconds
Started May 23 03:28:28 PM PDT 24
Finished May 23 03:29:08 PM PDT 24
Peak memory 201676 kb
Host smart-7eecc7bf-53f8-49ad-aeaa-c36303d9ecf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742005124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.742005124
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2839119920
Short name T518
Test name
Test status
Simulation time 3757601992 ps
CPU time 3.21 seconds
Started May 23 03:28:29 PM PDT 24
Finished May 23 03:28:34 PM PDT 24
Peak memory 201584 kb
Host smart-32b5ae91-9b7f-47dd-a711-ce755f5b99c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839119920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2839119920
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1879116311
Short name T451
Test name
Test status
Simulation time 6066444700 ps
CPU time 7.91 seconds
Started May 23 03:28:12 PM PDT 24
Finished May 23 03:28:24 PM PDT 24
Peak memory 201656 kb
Host smart-3f63d0e8-eecc-484c-9f9f-efc12ecee661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879116311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1879116311
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.4245874343
Short name T150
Test name
Test status
Simulation time 501606029178 ps
CPU time 139.89 seconds
Started May 23 03:28:31 PM PDT 24
Finished May 23 03:30:52 PM PDT 24
Peak memory 201888 kb
Host smart-88aedbc2-2a61-4512-9ef8-e63d8cddad4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245874343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.4245874343
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1725378435
Short name T15
Test name
Test status
Simulation time 697169993392 ps
CPU time 316.92 seconds
Started May 23 03:28:30 PM PDT 24
Finished May 23 03:33:49 PM PDT 24
Peak memory 218012 kb
Host smart-e8fe4c8b-ceba-428e-9e5e-11501f4d1eaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725378435 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1725378435
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3027064284
Short name T77
Test name
Test status
Simulation time 478103162 ps
CPU time 1.71 seconds
Started May 23 03:28:45 PM PDT 24
Finished May 23 03:28:48 PM PDT 24
Peak memory 201536 kb
Host smart-cb72e03f-73f3-4d11-a557-c10d9585dd82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027064284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3027064284
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3994165261
Short name T760
Test name
Test status
Simulation time 351410734022 ps
CPU time 416.08 seconds
Started May 23 03:28:30 PM PDT 24
Finished May 23 03:35:28 PM PDT 24
Peak memory 201848 kb
Host smart-eedb6839-bb52-4cfa-8431-b292c4ca0074
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994165261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3994165261
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3548003534
Short name T287
Test name
Test status
Simulation time 497463796788 ps
CPU time 597.39 seconds
Started May 23 03:28:31 PM PDT 24
Finished May 23 03:38:30 PM PDT 24
Peak memory 201788 kb
Host smart-ce554bba-6c9a-4055-ac10-1e799d69f2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548003534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3548003534
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.4023203074
Short name T608
Test name
Test status
Simulation time 165394961085 ps
CPU time 89.2 seconds
Started May 23 03:28:29 PM PDT 24
Finished May 23 03:30:00 PM PDT 24
Peak memory 201884 kb
Host smart-b4d7c8b6-5444-430f-a2ce-7dda1348f5d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023203074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.4023203074
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3684117770
Short name T167
Test name
Test status
Simulation time 331947696780 ps
CPU time 806.9 seconds
Started May 23 03:28:29 PM PDT 24
Finished May 23 03:41:57 PM PDT 24
Peak memory 201844 kb
Host smart-591803e0-b459-4f79-a0db-93ed6349ad1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684117770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3684117770
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3773982983
Short name T445
Test name
Test status
Simulation time 330942587270 ps
CPU time 738.75 seconds
Started May 23 03:28:28 PM PDT 24
Finished May 23 03:40:48 PM PDT 24
Peak memory 201828 kb
Host smart-1d7089f8-400c-4d66-9ed8-3d70604a7acc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773982983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3773982983
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.477256546
Short name T237
Test name
Test status
Simulation time 365169727470 ps
CPU time 241.74 seconds
Started May 23 03:28:28 PM PDT 24
Finished May 23 03:32:31 PM PDT 24
Peak memory 201984 kb
Host smart-380c80b8-4564-4395-93cf-be5471b21693
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477256546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.477256546
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1619659078
Short name T113
Test name
Test status
Simulation time 616890243306 ps
CPU time 512.48 seconds
Started May 23 03:28:29 PM PDT 24
Finished May 23 03:37:03 PM PDT 24
Peak memory 201820 kb
Host smart-ff02cbcc-d1d6-44cc-b0cb-e1586355e2b1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619659078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1619659078
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3044407942
Short name T679
Test name
Test status
Simulation time 70914818946 ps
CPU time 289.14 seconds
Started May 23 03:28:28 PM PDT 24
Finished May 23 03:33:19 PM PDT 24
Peak memory 202148 kb
Host smart-062f3483-d77d-4fdf-9476-63d4700f7174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044407942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3044407942
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3728929838
Short name T552
Test name
Test status
Simulation time 37881848949 ps
CPU time 24.24 seconds
Started May 23 03:28:30 PM PDT 24
Finished May 23 03:28:56 PM PDT 24
Peak memory 201656 kb
Host smart-227a0fc8-534f-42ac-b7c3-907d1956f7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728929838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3728929838
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3996461980
Short name T647
Test name
Test status
Simulation time 2986609194 ps
CPU time 1.19 seconds
Started May 23 03:28:30 PM PDT 24
Finished May 23 03:28:32 PM PDT 24
Peak memory 201604 kb
Host smart-dbacae2f-3bf5-4ce6-b442-ca2c5d418696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996461980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3996461980
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1552166591
Short name T172
Test name
Test status
Simulation time 5880689072 ps
CPU time 3.51 seconds
Started May 23 03:28:29 PM PDT 24
Finished May 23 03:28:35 PM PDT 24
Peak memory 201644 kb
Host smart-f7daf881-9381-4608-a3a2-c5f3508f9576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552166591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1552166591
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1805901302
Short name T710
Test name
Test status
Simulation time 329889482654 ps
CPU time 796.12 seconds
Started May 23 03:28:42 PM PDT 24
Finished May 23 03:42:01 PM PDT 24
Peak memory 201840 kb
Host smart-95e34d96-2854-47d8-a9bc-a47b813e1402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805901302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1805901302
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1596342646
Short name T360
Test name
Test status
Simulation time 30859215841 ps
CPU time 76.9 seconds
Started May 23 03:28:43 PM PDT 24
Finished May 23 03:30:02 PM PDT 24
Peak memory 217744 kb
Host smart-4850fb8b-2190-45c6-a981-4c1a35e5f4d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596342646 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1596342646
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2205125956
Short name T537
Test name
Test status
Simulation time 404348702 ps
CPU time 0.79 seconds
Started May 23 03:28:43 PM PDT 24
Finished May 23 03:28:46 PM PDT 24
Peak memory 201536 kb
Host smart-14aee748-d30f-4e6e-b791-93b735a61ac3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205125956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2205125956
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2446986559
Short name T759
Test name
Test status
Simulation time 329414048785 ps
CPU time 199.29 seconds
Started May 23 03:28:43 PM PDT 24
Finished May 23 03:32:04 PM PDT 24
Peak memory 201844 kb
Host smart-a1f61fc1-f958-4bb8-b267-4fbf09198c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446986559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2446986559
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.4195533201
Short name T174
Test name
Test status
Simulation time 333894205982 ps
CPU time 189.9 seconds
Started May 23 03:28:43 PM PDT 24
Finished May 23 03:31:55 PM PDT 24
Peak memory 201836 kb
Host smart-817f08ae-faf5-4ae3-853d-c4bb3c1aa5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195533201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.4195533201
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.381976913
Short name T387
Test name
Test status
Simulation time 498062620178 ps
CPU time 1236.42 seconds
Started May 23 03:28:43 PM PDT 24
Finished May 23 03:49:22 PM PDT 24
Peak memory 201836 kb
Host smart-39d9085c-23cd-4348-be90-c76ae020b426
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=381976913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.381976913
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.457981690
Short name T194
Test name
Test status
Simulation time 167991642294 ps
CPU time 335.52 seconds
Started May 23 03:28:44 PM PDT 24
Finished May 23 03:34:21 PM PDT 24
Peak memory 201904 kb
Host smart-391f874a-b634-48cf-8ce8-5b72505c7331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457981690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.457981690
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2425140000
Short name T2
Test name
Test status
Simulation time 492296091498 ps
CPU time 288.72 seconds
Started May 23 03:28:42 PM PDT 24
Finished May 23 03:33:33 PM PDT 24
Peak memory 201888 kb
Host smart-eb0b9d4a-efe3-4c59-aaf5-6ab9743e9179
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425140000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2425140000
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2897388709
Short name T315
Test name
Test status
Simulation time 190707606114 ps
CPU time 218.03 seconds
Started May 23 03:28:43 PM PDT 24
Finished May 23 03:32:23 PM PDT 24
Peak memory 201920 kb
Host smart-cd5e9b7a-a3f5-4e6e-8cfb-7c5e379f84ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897388709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2897388709
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2827151702
Short name T509
Test name
Test status
Simulation time 204917196036 ps
CPU time 126.21 seconds
Started May 23 03:28:44 PM PDT 24
Finished May 23 03:30:52 PM PDT 24
Peak memory 201824 kb
Host smart-d2b5feb8-021d-422c-81ac-dde0dbc64f87
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827151702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2827151702
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3434132090
Short name T234
Test name
Test status
Simulation time 94234858956 ps
CPU time 474.74 seconds
Started May 23 03:28:48 PM PDT 24
Finished May 23 03:36:45 PM PDT 24
Peak memory 202236 kb
Host smart-1656c4c0-e8b5-453b-a31a-bf86280e48c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434132090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3434132090
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.4164449478
Short name T474
Test name
Test status
Simulation time 36327867469 ps
CPU time 19.1 seconds
Started May 23 03:28:43 PM PDT 24
Finished May 23 03:29:04 PM PDT 24
Peak memory 201688 kb
Host smart-e25d8d96-ec1b-4065-bbfa-456124d54e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164449478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.4164449478
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2295671597
Short name T618
Test name
Test status
Simulation time 2926035391 ps
CPU time 4.37 seconds
Started May 23 03:28:45 PM PDT 24
Finished May 23 03:28:51 PM PDT 24
Peak memory 201560 kb
Host smart-3a0292c1-2151-445b-9f93-500d815ea4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295671597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2295671597
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.125637614
Short name T412
Test name
Test status
Simulation time 5801251989 ps
CPU time 4.3 seconds
Started May 23 03:28:43 PM PDT 24
Finished May 23 03:28:49 PM PDT 24
Peak memory 201696 kb
Host smart-c8f98965-3b07-4104-ab33-fc655273fdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125637614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.125637614
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1690934570
Short name T104
Test name
Test status
Simulation time 29897341764 ps
CPU time 87.06 seconds
Started May 23 03:28:46 PM PDT 24
Finished May 23 03:30:14 PM PDT 24
Peak memory 210760 kb
Host smart-e3f03a3b-478c-48f2-a08c-1029fd7120bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690934570 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1690934570
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2527475333
Short name T784
Test name
Test status
Simulation time 387916780 ps
CPU time 1.07 seconds
Started May 23 03:29:04 PM PDT 24
Finished May 23 03:29:07 PM PDT 24
Peak memory 201540 kb
Host smart-94777d7a-f65d-41a9-b61f-53f45fdfebd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527475333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2527475333
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2870985631
Short name T222
Test name
Test status
Simulation time 547080542988 ps
CPU time 1187.22 seconds
Started May 23 03:28:44 PM PDT 24
Finished May 23 03:48:33 PM PDT 24
Peak memory 201816 kb
Host smart-f9a8e52a-50c2-4072-b125-323e47c2f8d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870985631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2870985631
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1149473789
Short name T307
Test name
Test status
Simulation time 331277993364 ps
CPU time 375.62 seconds
Started May 23 03:28:48 PM PDT 24
Finished May 23 03:35:05 PM PDT 24
Peak memory 201844 kb
Host smart-77b9950d-e8a9-4a44-85d7-d67d216fe024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149473789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1149473789
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1950100552
Short name T211
Test name
Test status
Simulation time 323615411740 ps
CPU time 203.38 seconds
Started May 23 03:28:48 PM PDT 24
Finished May 23 03:32:14 PM PDT 24
Peak memory 201856 kb
Host smart-7dca1da6-15cf-4a84-a919-16873d4aac14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950100552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1950100552
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.10066683
Short name T448
Test name
Test status
Simulation time 169561109424 ps
CPU time 119.64 seconds
Started May 23 03:28:44 PM PDT 24
Finished May 23 03:30:46 PM PDT 24
Peak memory 201808 kb
Host smart-f01f8bc9-4cf0-42dd-9b54-e18a7bd87e6c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=10066683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt
_fixed.10066683
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2203074003
Short name T238
Test name
Test status
Simulation time 327060878279 ps
CPU time 530.54 seconds
Started May 23 03:28:47 PM PDT 24
Finished May 23 03:37:39 PM PDT 24
Peak memory 201832 kb
Host smart-9a6a55f5-b22f-4994-acd6-0f6c0506509b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203074003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2203074003
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3322518813
Short name T378
Test name
Test status
Simulation time 166179431578 ps
CPU time 367.56 seconds
Started May 23 03:28:44 PM PDT 24
Finished May 23 03:34:53 PM PDT 24
Peak memory 201856 kb
Host smart-f08a9f41-6633-460b-bb26-a633d2b30733
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322518813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3322518813
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3300324224
Short name T607
Test name
Test status
Simulation time 183807349926 ps
CPU time 222.97 seconds
Started May 23 03:28:48 PM PDT 24
Finished May 23 03:32:33 PM PDT 24
Peak memory 201868 kb
Host smart-3d1fa375-b74d-4900-9066-0516d7f7cf6b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300324224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3300324224
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.73524518
Short name T578
Test name
Test status
Simulation time 203676052843 ps
CPU time 35.13 seconds
Started May 23 03:28:45 PM PDT 24
Finished May 23 03:29:21 PM PDT 24
Peak memory 201816 kb
Host smart-162e9f05-e8be-43a1-90fe-65e7c574bc75
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73524518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.a
dc_ctrl_filters_wakeup_fixed.73524518
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.516750940
Short name T226
Test name
Test status
Simulation time 123108983079 ps
CPU time 527.8 seconds
Started May 23 03:29:06 PM PDT 24
Finished May 23 03:37:55 PM PDT 24
Peak memory 202188 kb
Host smart-afd2e9d3-e541-4f28-a4bf-c5ea19fb7867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516750940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.516750940
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3999686646
Short name T440
Test name
Test status
Simulation time 31051653548 ps
CPU time 26.77 seconds
Started May 23 03:29:04 PM PDT 24
Finished May 23 03:29:33 PM PDT 24
Peak memory 201676 kb
Host smart-1d2ba16c-e9bf-4873-9eb0-c0725a522efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999686646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3999686646
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1082324623
Short name T397
Test name
Test status
Simulation time 4988513492 ps
CPU time 8.95 seconds
Started May 23 03:28:46 PM PDT 24
Finished May 23 03:28:57 PM PDT 24
Peak memory 201668 kb
Host smart-f6350c25-a91a-499c-94e0-1e30445c1fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082324623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1082324623
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1290467561
Short name T463
Test name
Test status
Simulation time 5693491479 ps
CPU time 4.09 seconds
Started May 23 03:28:45 PM PDT 24
Finished May 23 03:28:51 PM PDT 24
Peak memory 201632 kb
Host smart-b3ec3f3d-f6d7-4988-8d56-469936d0ae56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290467561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1290467561
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1193334910
Short name T277
Test name
Test status
Simulation time 333972819322 ps
CPU time 215.4 seconds
Started May 23 03:29:04 PM PDT 24
Finished May 23 03:32:41 PM PDT 24
Peak memory 201828 kb
Host smart-0970fc82-3fe4-4f60-afe6-b2f883202a33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193334910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1193334910
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3192823999
Short name T683
Test name
Test status
Simulation time 275382686290 ps
CPU time 410.62 seconds
Started May 23 03:29:04 PM PDT 24
Finished May 23 03:35:56 PM PDT 24
Peak memory 210452 kb
Host smart-9207dd5a-dc4f-48c9-94c6-f98e1658bc07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192823999 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3192823999
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3675405632
Short name T457
Test name
Test status
Simulation time 444672274 ps
CPU time 0.87 seconds
Started May 23 03:29:06 PM PDT 24
Finished May 23 03:29:08 PM PDT 24
Peak memory 201584 kb
Host smart-e860c681-40b1-4c19-a415-071cc1b831c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675405632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3675405632
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2446297311
Short name T335
Test name
Test status
Simulation time 168173467821 ps
CPU time 116.55 seconds
Started May 23 03:29:07 PM PDT 24
Finished May 23 03:31:05 PM PDT 24
Peak memory 201888 kb
Host smart-07b7b9e1-f08e-4235-b43a-597992b25ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446297311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2446297311
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1520649275
Short name T328
Test name
Test status
Simulation time 161133126637 ps
CPU time 74.23 seconds
Started May 23 03:29:04 PM PDT 24
Finished May 23 03:30:19 PM PDT 24
Peak memory 201856 kb
Host smart-5e44d99c-dc77-49b9-80d3-e96cd529a965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520649275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1520649275
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3413546578
Short name T729
Test name
Test status
Simulation time 324769336063 ps
CPU time 409.29 seconds
Started May 23 03:29:05 PM PDT 24
Finished May 23 03:35:56 PM PDT 24
Peak memory 201780 kb
Host smart-7ca55f39-d44c-44b1-b4dc-2c78b9a23a74
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413546578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3413546578
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1512756463
Short name T417
Test name
Test status
Simulation time 162611062756 ps
CPU time 101.95 seconds
Started May 23 03:29:04 PM PDT 24
Finished May 23 03:30:48 PM PDT 24
Peak memory 201820 kb
Host smart-e292e657-c38b-4fd3-9d41-e00cf41ff408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512756463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1512756463
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.696133379
Short name T441
Test name
Test status
Simulation time 336957176322 ps
CPU time 755.45 seconds
Started May 23 03:29:04 PM PDT 24
Finished May 23 03:41:41 PM PDT 24
Peak memory 201860 kb
Host smart-ff87a10e-214e-478a-99c3-667f95b21bbe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=696133379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.696133379
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3861123209
Short name T650
Test name
Test status
Simulation time 186693791345 ps
CPU time 406.39 seconds
Started May 23 03:29:06 PM PDT 24
Finished May 23 03:35:54 PM PDT 24
Peak memory 201856 kb
Host smart-9eb3b4b6-f4eb-4dfe-a54b-ec0f001d650c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861123209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3861123209
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3930947348
Short name T493
Test name
Test status
Simulation time 388171680740 ps
CPU time 458.8 seconds
Started May 23 03:29:05 PM PDT 24
Finished May 23 03:36:45 PM PDT 24
Peak memory 201824 kb
Host smart-be8dc9f5-3ce2-4f83-abe6-7f60e02d0167
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930947348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3930947348
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.4156682823
Short name T358
Test name
Test status
Simulation time 133410149901 ps
CPU time 668 seconds
Started May 23 03:29:05 PM PDT 24
Finished May 23 03:40:15 PM PDT 24
Peak memory 202220 kb
Host smart-64e62bc2-31cd-46ad-be73-7de65028d55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156682823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.4156682823
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3735444639
Short name T10
Test name
Test status
Simulation time 41633166720 ps
CPU time 52.67 seconds
Started May 23 03:29:05 PM PDT 24
Finished May 23 03:29:59 PM PDT 24
Peak memory 201640 kb
Host smart-afadadff-4717-4e30-b58d-14bedc94fea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735444639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3735444639
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2857470215
Short name T602
Test name
Test status
Simulation time 4027358047 ps
CPU time 2.99 seconds
Started May 23 03:29:07 PM PDT 24
Finished May 23 03:29:11 PM PDT 24
Peak memory 201620 kb
Host smart-b68013be-d680-42b6-816c-23b70ea31820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857470215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2857470215
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1476352651
Short name T519
Test name
Test status
Simulation time 5792853041 ps
CPU time 2.98 seconds
Started May 23 03:29:05 PM PDT 24
Finished May 23 03:29:09 PM PDT 24
Peak memory 201652 kb
Host smart-6ab76eca-d740-4448-9e34-78c77c8e4e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476352651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1476352651
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.791901717
Short name T501
Test name
Test status
Simulation time 309227979 ps
CPU time 1.38 seconds
Started May 23 03:21:57 PM PDT 24
Finished May 23 03:21:59 PM PDT 24
Peak memory 201516 kb
Host smart-91d64328-d42a-4abd-8545-1035612ffa4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791901717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.791901717
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1016208716
Short name T244
Test name
Test status
Simulation time 176738211137 ps
CPU time 370.25 seconds
Started May 23 03:21:49 PM PDT 24
Finished May 23 03:28:00 PM PDT 24
Peak memory 201896 kb
Host smart-3277db20-f124-46f7-abfe-e8529948b42e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016208716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1016208716
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.845146703
Short name T161
Test name
Test status
Simulation time 169002518942 ps
CPU time 387.81 seconds
Started May 23 03:21:42 PM PDT 24
Finished May 23 03:28:12 PM PDT 24
Peak memory 201900 kb
Host smart-b4812e4c-9601-4278-937d-bb06148cd0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845146703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.845146703
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2565429728
Short name T171
Test name
Test status
Simulation time 164682368614 ps
CPU time 398.72 seconds
Started May 23 03:21:41 PM PDT 24
Finished May 23 03:28:22 PM PDT 24
Peak memory 201804 kb
Host smart-b25b84a6-6c57-41cb-83be-080d9c108afb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565429728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2565429728
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3013838491
Short name T594
Test name
Test status
Simulation time 324221789321 ps
CPU time 221.53 seconds
Started May 23 03:21:45 PM PDT 24
Finished May 23 03:25:27 PM PDT 24
Peak memory 201816 kb
Host smart-45f66f38-5245-4da9-a377-d7885a2cc0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013838491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3013838491
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.245775528
Short name T586
Test name
Test status
Simulation time 499872869183 ps
CPU time 283.64 seconds
Started May 23 03:21:50 PM PDT 24
Finished May 23 03:26:35 PM PDT 24
Peak memory 201892 kb
Host smart-9778637b-3eba-4af4-b782-33d5729c45c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=245775528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.245775528
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1882808068
Short name T701
Test name
Test status
Simulation time 354893936391 ps
CPU time 789.94 seconds
Started May 23 03:21:50 PM PDT 24
Finished May 23 03:35:01 PM PDT 24
Peak memory 201864 kb
Host smart-18b45e70-736d-4f15-ae56-a8b5b4642fef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882808068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1882808068
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.361831932
Short name T722
Test name
Test status
Simulation time 603483914353 ps
CPU time 1381.73 seconds
Started May 23 03:21:43 PM PDT 24
Finished May 23 03:44:47 PM PDT 24
Peak memory 201760 kb
Host smart-29dcc996-d5b7-4687-95cc-47248fe45e0a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361831932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.361831932
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1174459132
Short name T57
Test name
Test status
Simulation time 118163394383 ps
CPU time 386.54 seconds
Started May 23 03:21:42 PM PDT 24
Finished May 23 03:28:11 PM PDT 24
Peak memory 202244 kb
Host smart-6a1b1cfd-ae1c-445c-8733-d9fffc418006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174459132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1174459132
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1997885221
Short name T385
Test name
Test status
Simulation time 27357707863 ps
CPU time 61.04 seconds
Started May 23 03:21:44 PM PDT 24
Finished May 23 03:22:46 PM PDT 24
Peak memory 201604 kb
Host smart-8f96dd0f-12d2-49a1-9843-f69191616c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997885221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1997885221
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.8674921
Short name T579
Test name
Test status
Simulation time 4985562590 ps
CPU time 12.66 seconds
Started May 23 03:21:50 PM PDT 24
Finished May 23 03:22:03 PM PDT 24
Peak memory 201608 kb
Host smart-ae9ffcc6-7dd1-4854-aff6-d6c1684b1a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8674921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.8674921
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3449454229
Short name T444
Test name
Test status
Simulation time 5646327227 ps
CPU time 4 seconds
Started May 23 03:21:45 PM PDT 24
Finished May 23 03:21:51 PM PDT 24
Peak memory 201676 kb
Host smart-1b21ddb5-bff2-4eff-9476-b92304197fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449454229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3449454229
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2313624514
Short name T322
Test name
Test status
Simulation time 354745517037 ps
CPU time 231.9 seconds
Started May 23 03:22:01 PM PDT 24
Finished May 23 03:25:54 PM PDT 24
Peak memory 210528 kb
Host smart-81f3f287-872e-4eb3-bc4f-b0c942678a99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313624514 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2313624514
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2618959919
Short name T122
Test name
Test status
Simulation time 443635361 ps
CPU time 1.31 seconds
Started May 23 03:22:00 PM PDT 24
Finished May 23 03:22:02 PM PDT 24
Peak memory 201524 kb
Host smart-f2f36c5c-2500-4081-9a29-733ac0549b1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618959919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2618959919
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3835163603
Short name T782
Test name
Test status
Simulation time 489763435511 ps
CPU time 491.36 seconds
Started May 23 03:21:58 PM PDT 24
Finished May 23 03:30:10 PM PDT 24
Peak memory 201840 kb
Host smart-7dbf8fbb-a7b6-48d5-a7d6-510443f51dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835163603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3835163603
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.679304893
Short name T203
Test name
Test status
Simulation time 489752005612 ps
CPU time 1222.97 seconds
Started May 23 03:22:03 PM PDT 24
Finished May 23 03:42:27 PM PDT 24
Peak memory 201836 kb
Host smart-70bbd8e6-126e-4952-91b2-38476fdd61d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=679304893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.679304893
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3661041431
Short name T790
Test name
Test status
Simulation time 166671714186 ps
CPU time 108.94 seconds
Started May 23 03:22:00 PM PDT 24
Finished May 23 03:23:51 PM PDT 24
Peak memory 201920 kb
Host smart-d7f76b5b-9c8e-48f9-8729-6b7792fed6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661041431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3661041431
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3054381607
Short name T559
Test name
Test status
Simulation time 492856197238 ps
CPU time 1091.51 seconds
Started May 23 03:22:00 PM PDT 24
Finished May 23 03:40:13 PM PDT 24
Peak memory 201836 kb
Host smart-6f79c0ea-71f7-46ac-8c90-ec27936a4185
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054381607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3054381607
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.731616017
Short name T791
Test name
Test status
Simulation time 408116672009 ps
CPU time 264.16 seconds
Started May 23 03:22:02 PM PDT 24
Finished May 23 03:26:27 PM PDT 24
Peak memory 201960 kb
Host smart-9a7b7f9e-1ffb-4203-83d1-b125674cc317
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731616017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.731616017
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1008623103
Short name T376
Test name
Test status
Simulation time 194640859465 ps
CPU time 116.68 seconds
Started May 23 03:21:59 PM PDT 24
Finished May 23 03:23:57 PM PDT 24
Peak memory 201848 kb
Host smart-4d6a7695-e262-4d8f-9ef5-c7ffbc9fb062
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008623103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1008623103
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.4197373622
Short name T359
Test name
Test status
Simulation time 88692820227 ps
CPU time 380.92 seconds
Started May 23 03:22:04 PM PDT 24
Finished May 23 03:28:26 PM PDT 24
Peak memory 202196 kb
Host smart-7a3c85b3-0238-4d31-bc5c-2cc3932369bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197373622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.4197373622
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2543279527
Short name T731
Test name
Test status
Simulation time 40434876466 ps
CPU time 25.77 seconds
Started May 23 03:22:00 PM PDT 24
Finished May 23 03:22:27 PM PDT 24
Peak memory 201664 kb
Host smart-a45c33ea-d61b-4b74-b60f-d3645f979973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543279527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2543279527
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3617055479
Short name T765
Test name
Test status
Simulation time 3823137577 ps
CPU time 2.84 seconds
Started May 23 03:21:57 PM PDT 24
Finished May 23 03:22:01 PM PDT 24
Peak memory 201612 kb
Host smart-28df61d1-9717-4094-9d9f-bfa614ce8093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617055479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3617055479
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.4139052825
Short name T634
Test name
Test status
Simulation time 5753260471 ps
CPU time 4.21 seconds
Started May 23 03:22:04 PM PDT 24
Finished May 23 03:22:10 PM PDT 24
Peak memory 201680 kb
Host smart-3ceeae73-13ad-48d2-9154-e4a644b65f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139052825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.4139052825
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.4214053037
Short name T711
Test name
Test status
Simulation time 400554987310 ps
CPU time 226.17 seconds
Started May 23 03:21:58 PM PDT 24
Finished May 23 03:25:45 PM PDT 24
Peak memory 201780 kb
Host smart-5a3d875d-81e1-4eb6-be6d-eb07d93373cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214053037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
4214053037
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.184205255
Short name T326
Test name
Test status
Simulation time 298020536999 ps
CPU time 152.66 seconds
Started May 23 03:22:00 PM PDT 24
Finished May 23 03:24:34 PM PDT 24
Peak memory 210548 kb
Host smart-d7459ef9-a0f4-4254-b533-362539cebe4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184205255 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.184205255
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.710743153
Short name T369
Test name
Test status
Simulation time 513137554 ps
CPU time 1.74 seconds
Started May 23 03:22:15 PM PDT 24
Finished May 23 03:22:18 PM PDT 24
Peak memory 201536 kb
Host smart-a4fc05a4-ee22-40d6-9561-23a69502b658
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710743153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.710743153
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1288915775
Short name T12
Test name
Test status
Simulation time 162866417651 ps
CPU time 133.7 seconds
Started May 23 03:22:04 PM PDT 24
Finished May 23 03:24:19 PM PDT 24
Peak memory 201844 kb
Host smart-efd2d642-2577-48b4-b217-0d1356ed7d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288915775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1288915775
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1885481620
Short name T87
Test name
Test status
Simulation time 329577204848 ps
CPU time 186.83 seconds
Started May 23 03:22:02 PM PDT 24
Finished May 23 03:25:09 PM PDT 24
Peak memory 201828 kb
Host smart-cb5c9c12-bcf9-4e6f-8afb-067d5c859933
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885481620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1885481620
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.393583597
Short name T250
Test name
Test status
Simulation time 489594765824 ps
CPU time 286.7 seconds
Started May 23 03:22:04 PM PDT 24
Finished May 23 03:26:52 PM PDT 24
Peak memory 201864 kb
Host smart-1f0f47b8-e38d-4555-a3a6-b1618c80b839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393583597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.393583597
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3994331118
Short name T570
Test name
Test status
Simulation time 161839574070 ps
CPU time 113.62 seconds
Started May 23 03:21:59 PM PDT 24
Finished May 23 03:23:54 PM PDT 24
Peak memory 201828 kb
Host smart-0710ae21-d326-4359-8f74-554166e97bc6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994331118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3994331118
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.533884905
Short name T118
Test name
Test status
Simulation time 411801937548 ps
CPU time 486.27 seconds
Started May 23 03:22:03 PM PDT 24
Finished May 23 03:30:10 PM PDT 24
Peak memory 201708 kb
Host smart-f29ff920-43ac-4713-860d-9017d4a12796
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533884905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.533884905
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3349256614
Short name T664
Test name
Test status
Simulation time 199039550189 ps
CPU time 236.59 seconds
Started May 23 03:21:59 PM PDT 24
Finished May 23 03:25:56 PM PDT 24
Peak memory 201856 kb
Host smart-0ef11e5d-f98e-4268-87e4-81b934d4c3a2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349256614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3349256614
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3376451645
Short name T231
Test name
Test status
Simulation time 73886245825 ps
CPU time 393.69 seconds
Started May 23 03:22:17 PM PDT 24
Finished May 23 03:28:53 PM PDT 24
Peak memory 202188 kb
Host smart-d7dcabf0-6a44-44fd-a6b4-04b550870a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376451645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3376451645
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2620405347
Short name T720
Test name
Test status
Simulation time 43910140897 ps
CPU time 53.93 seconds
Started May 23 03:21:59 PM PDT 24
Finished May 23 03:22:54 PM PDT 24
Peak memory 201632 kb
Host smart-9f9a4236-e7be-4078-b201-ca03e330cc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620405347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2620405347
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2398054932
Short name T544
Test name
Test status
Simulation time 4573117463 ps
CPU time 1.38 seconds
Started May 23 03:22:03 PM PDT 24
Finished May 23 03:22:05 PM PDT 24
Peak memory 201516 kb
Host smart-ea231fc4-4f8b-49bb-b737-017e633fa1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398054932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2398054932
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3651643073
Short name T514
Test name
Test status
Simulation time 5958718770 ps
CPU time 7.4 seconds
Started May 23 03:21:59 PM PDT 24
Finished May 23 03:22:08 PM PDT 24
Peak memory 201688 kb
Host smart-b1c66184-0b50-4fe2-91c5-2076d530233f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651643073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3651643073
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1818741759
Short name T736
Test name
Test status
Simulation time 694492254090 ps
CPU time 874.07 seconds
Started May 23 03:22:17 PM PDT 24
Finished May 23 03:36:54 PM PDT 24
Peak memory 201808 kb
Host smart-92c2e6fb-6a35-4955-8608-e063eb4a07de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818741759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1818741759
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.961972413
Short name T761
Test name
Test status
Simulation time 351288928906 ps
CPU time 716.72 seconds
Started May 23 03:22:17 PM PDT 24
Finished May 23 03:34:16 PM PDT 24
Peak memory 210472 kb
Host smart-2b3e668f-c12d-467c-bc69-5d92fda327d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961972413 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.961972413
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2067136485
Short name T377
Test name
Test status
Simulation time 490222885 ps
CPU time 1.17 seconds
Started May 23 03:22:17 PM PDT 24
Finished May 23 03:22:21 PM PDT 24
Peak memory 201504 kb
Host smart-d9793b4c-7d32-46bf-b3ba-7bcfe52a54fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067136485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2067136485
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2505589840
Short name T169
Test name
Test status
Simulation time 165972169793 ps
CPU time 3.9 seconds
Started May 23 03:22:17 PM PDT 24
Finished May 23 03:22:27 PM PDT 24
Peak memory 201796 kb
Host smart-ff537af3-380e-4aff-a9f9-be89f56ed4b3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505589840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2505589840
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.765103774
Short name T223
Test name
Test status
Simulation time 336733801180 ps
CPU time 808.21 seconds
Started May 23 03:22:18 PM PDT 24
Finished May 23 03:35:48 PM PDT 24
Peak memory 201840 kb
Host smart-7b336718-a9ce-4b29-a1b6-0a52661126bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765103774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.765103774
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3882887062
Short name T28
Test name
Test status
Simulation time 167279640445 ps
CPU time 113.78 seconds
Started May 23 03:22:14 PM PDT 24
Finished May 23 03:24:09 PM PDT 24
Peak memory 201920 kb
Host smart-4185bd81-edce-4466-9d90-25f76f6380f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882887062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3882887062
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2735787150
Short name T437
Test name
Test status
Simulation time 493026298479 ps
CPU time 306.89 seconds
Started May 23 03:22:15 PM PDT 24
Finished May 23 03:27:24 PM PDT 24
Peak memory 201828 kb
Host smart-e891ca0f-3cbe-48cd-ab8a-22b1ecd892d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735787150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2735787150
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.383649948
Short name T123
Test name
Test status
Simulation time 162049062446 ps
CPU time 371.95 seconds
Started May 23 03:22:16 PM PDT 24
Finished May 23 03:28:31 PM PDT 24
Peak memory 201804 kb
Host smart-ad5ad01e-972a-4ee7-a1b6-3409dbefdd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383649948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.383649948
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1037578940
Short name T702
Test name
Test status
Simulation time 169367571639 ps
CPU time 104.28 seconds
Started May 23 03:22:13 PM PDT 24
Finished May 23 03:23:59 PM PDT 24
Peak memory 201900 kb
Host smart-5640aead-e677-4cdd-93a5-07fabf794c3e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037578940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1037578940
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.275849440
Short name T352
Test name
Test status
Simulation time 565569032186 ps
CPU time 1405.26 seconds
Started May 23 03:22:17 PM PDT 24
Finished May 23 03:45:44 PM PDT 24
Peak memory 201880 kb
Host smart-c52d5a99-c651-4306-a71b-68af823cfcdc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275849440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.275849440
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3687877276
Short name T472
Test name
Test status
Simulation time 195090657640 ps
CPU time 214.66 seconds
Started May 23 03:22:16 PM PDT 24
Finished May 23 03:25:53 PM PDT 24
Peak memory 201832 kb
Host smart-6b03af0d-eaf2-42ea-bf08-6a7f8482ab24
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687877276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3687877276
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2288668284
Short name T390
Test name
Test status
Simulation time 75522846646 ps
CPU time 404.89 seconds
Started May 23 03:22:15 PM PDT 24
Finished May 23 03:29:02 PM PDT 24
Peak memory 202160 kb
Host smart-aba3865d-04df-4dfa-afec-c3b138ed6afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288668284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2288668284
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1738055865
Short name T652
Test name
Test status
Simulation time 40971556153 ps
CPU time 26.9 seconds
Started May 23 03:22:16 PM PDT 24
Finished May 23 03:22:45 PM PDT 24
Peak memory 201648 kb
Host smart-37d5a335-25b4-4514-936b-5733e687d983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738055865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1738055865
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2374517382
Short name T734
Test name
Test status
Simulation time 5469723048 ps
CPU time 3.96 seconds
Started May 23 03:22:16 PM PDT 24
Finished May 23 03:22:22 PM PDT 24
Peak memory 201684 kb
Host smart-498d9ed8-7fac-4706-9441-6ff98367998a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374517382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2374517382
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.4126440634
Short name T604
Test name
Test status
Simulation time 5936340885 ps
CPU time 14.67 seconds
Started May 23 03:22:15 PM PDT 24
Finished May 23 03:22:32 PM PDT 24
Peak memory 201668 kb
Host smart-b0ec7b69-88a4-4f50-998f-15cec227443e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126440634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.4126440634
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1153864311
Short name T249
Test name
Test status
Simulation time 433970311527 ps
CPU time 518.9 seconds
Started May 23 03:22:15 PM PDT 24
Finished May 23 03:30:56 PM PDT 24
Peak memory 202164 kb
Host smart-5f9df08e-f564-4139-8b5d-f56dcc6366df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153864311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1153864311
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2601318145
Short name T115
Test name
Test status
Simulation time 370058315429 ps
CPU time 270.22 seconds
Started May 23 03:22:16 PM PDT 24
Finished May 23 03:26:49 PM PDT 24
Peak memory 210460 kb
Host smart-dd9dd9c8-4308-4c72-8182-017dc5631843
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601318145 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2601318145
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.42265561
Short name T393
Test name
Test status
Simulation time 382630615 ps
CPU time 1.56 seconds
Started May 23 03:22:16 PM PDT 24
Finished May 23 03:22:20 PM PDT 24
Peak memory 201516 kb
Host smart-6e049728-8c29-4a77-a328-6408d5d99e12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42265561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.42265561
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.417529875
Short name T179
Test name
Test status
Simulation time 508132710449 ps
CPU time 291.73 seconds
Started May 23 03:22:15 PM PDT 24
Finished May 23 03:27:08 PM PDT 24
Peak memory 201844 kb
Host smart-17b67e2f-3837-4654-887a-f3592b27720b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417529875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.417529875
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2927992841
Short name T795
Test name
Test status
Simulation time 166997040471 ps
CPU time 205.96 seconds
Started May 23 03:22:14 PM PDT 24
Finished May 23 03:25:41 PM PDT 24
Peak memory 201836 kb
Host smart-fc4e500c-e28e-4494-b97b-14bd68fd8bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927992841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2927992841
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3024403893
Short name T477
Test name
Test status
Simulation time 165702897647 ps
CPU time 186.24 seconds
Started May 23 03:22:16 PM PDT 24
Finished May 23 03:25:25 PM PDT 24
Peak memory 201724 kb
Host smart-c6fba739-7507-446f-9175-fdec5efff031
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024403893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3024403893
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3495998752
Short name T197
Test name
Test status
Simulation time 493354675845 ps
CPU time 150.94 seconds
Started May 23 03:22:17 PM PDT 24
Finished May 23 03:24:50 PM PDT 24
Peak memory 201872 kb
Host smart-ea82522c-59c1-485c-a58f-2da84eef07bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495998752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3495998752
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1978989476
Short name T91
Test name
Test status
Simulation time 487851225595 ps
CPU time 557.37 seconds
Started May 23 03:22:15 PM PDT 24
Finished May 23 03:31:34 PM PDT 24
Peak memory 201852 kb
Host smart-60af89b4-d44c-44ff-af36-c46a30197ebd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978989476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1978989476
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.4083606946
Short name T155
Test name
Test status
Simulation time 682485290599 ps
CPU time 755.91 seconds
Started May 23 03:22:16 PM PDT 24
Finished May 23 03:34:53 PM PDT 24
Peak memory 201884 kb
Host smart-5717d74c-a5fc-4a5b-8d5f-992289531851
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083606946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.4083606946
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.79327641
Short name T51
Test name
Test status
Simulation time 208700688431 ps
CPU time 493.7 seconds
Started May 23 03:22:16 PM PDT 24
Finished May 23 03:30:31 PM PDT 24
Peak memory 201808 kb
Host smart-1d30b4a8-c139-47f2-bb59-a1c582920c31
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79327641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.ad
c_ctrl_filters_wakeup_fixed.79327641
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3376572195
Short name T361
Test name
Test status
Simulation time 93785220448 ps
CPU time 540.74 seconds
Started May 23 03:22:13 PM PDT 24
Finished May 23 03:31:15 PM PDT 24
Peak memory 202224 kb
Host smart-00cc6e5c-b39c-4146-a644-deb44680ffc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376572195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3376572195
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.427719787
Short name T366
Test name
Test status
Simulation time 26734110830 ps
CPU time 69.67 seconds
Started May 23 03:22:16 PM PDT 24
Finished May 23 03:23:27 PM PDT 24
Peak memory 201680 kb
Host smart-d11157bd-0680-4558-9b76-0e94e9cb144b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427719787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.427719787
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1790919057
Short name T367
Test name
Test status
Simulation time 5029878379 ps
CPU time 6.52 seconds
Started May 23 03:22:14 PM PDT 24
Finished May 23 03:22:22 PM PDT 24
Peak memory 201648 kb
Host smart-47e5720e-3890-4960-8a08-f6e53f34ff15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790919057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1790919057
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.2308399437
Short name T735
Test name
Test status
Simulation time 6000883404 ps
CPU time 1.73 seconds
Started May 23 03:22:21 PM PDT 24
Finished May 23 03:22:24 PM PDT 24
Peak memory 201664 kb
Host smart-01455816-6feb-4e60-a5e2-8f172677cb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308399437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2308399437
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1391612696
Short name T533
Test name
Test status
Simulation time 119393937118 ps
CPU time 66.22 seconds
Started May 23 03:22:17 PM PDT 24
Finished May 23 03:23:26 PM PDT 24
Peak memory 210244 kb
Host smart-a9bd5be3-a01b-4c64-b181-78610956f207
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391612696 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1391612696
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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