Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7077	1			T1	64		T3	40		T10	8
testmodes[AdcCtrlTestmodeNormal]	5466	1			T1	66		T2	2		T3	2
testmodes[AdcCtrlTestmodeLowpower]	5993	1			T1	70		T7	20		T8	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3913	1			T1	17		T3	39		T10	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1701	1			T1	27		T3	1		T10	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1354	1			T1	19		T35	2		T36	7
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1717	1			T1	25		T10	4		T111	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2028	1			T1	16		T2	1		T3	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1385	1			T1	25		T8	1		T11	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1337	1			T1	21		T35	4		T36	11
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1400	1			T1	23		T12	1		T13	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	3004	1			T1	26		T7	19		T9	19