Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26587

1

T1

200

T2

2

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22927

1

T1

200

T2

2

T3

40

auto[ADC_CTRL_FILTER_COND_OUT]

3660

1

T3

14

T6

1

T11

36

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20631

1

T1

200

T3

41

T5

1

auto[1]

5956

1

T2

2

T3

13

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22672

1

T1

200

T2

2

T3

42

auto[1]

3915

1

T3

12

T8

17

T11

16

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T213	3		T214	11		-	-
values[0]	56	1			T29	3		T215	31		T216	19
values[1]	813	1			T5	1		T47	36		T90	17
values[2]	568	1			T13	18		T37	1		T29	4
values[3]	769	1			T3	13		T6	1		T27	18
values[4]	441	1			T12	32		T13	4		T36	8
values[5]	2795	1			T2	2		T50	1		T110	12
values[6]	834	1			T6	1		T37	22		T27	5
values[7]	611	1			T5	1		T11	20		T47	24
values[8]	707	1			T4	1		T5	1		T8	27
values[9]	1391	1			T3	1		T8	9		T11	16
minimum	17588	1			T1	200		T3	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	828	1			T13	18		T47	36		T29	7
values[1]	798	1			T5	1		T37	1		T32	9
values[2]	596	1			T3	13		T6	1		T13	2
values[3]	2718	1			T2	2		T12	32		T13	2
values[4]	749	1			T33	15		T134	1		T38	6
values[5]	683	1			T6	1		T47	24		T44	4
values[6]	644	1			T4	1		T5	2		T11	20
values[7]	630	1			T8	36		T48	4		T15	5
values[8]	980	1			T3	1		T11	16		T35	2
values[9]	347	1			T36	11		T26	2		T134	6
minimum	17614	1			T1	200		T3	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

4136

1

T8

17

T11

18

T12

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T29	5		T90	10		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	9		T47	19		T174	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T5	1		T37	1		T194	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T32	9		T217	11		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T6	1		T13	1		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T3	1		T146	12		T219	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1533	1			T2	2		T12	7		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	9		T13	1		T36	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T33	8		T145	1		T136	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T134	1		T38	5		T198	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T47	13		T27	1		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	1		T44	4		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T4	1		T5	2		T48	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T11	11		T37	7		T32	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	19		T17	9		T220	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T48	4		T15	3		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T33	10		T138	18		T183	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T3	1		T11	9		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T36	6		T26	1		T39	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T134	1		T221	1		T188	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17448	1			T1	200		T3	40		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T29	2		T90	7		T218	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	9		T47	17		T40	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T194	11		T153	1		T139	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T218	1		T147	12		T93	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T13	1		T27	17		T31	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	12		T222	3		T223	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	878	1			T12	5		T110	11		T42	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	11		T13	1		T36	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T33	7		T145	1		T136	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T38	1		T198	14		T199	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	11		T27	4		T224	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T36	1		T26	14		T27	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T198	2		T225	4		T226	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	9		T37	15		T190	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	17		T17	7		T227	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T15	2		T138	11		T194	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T33	8		T138	15		T183	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T11	7		T35	1		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T36	5		T26	1		T39	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T134	5		T188	21		T148	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T15	1		T29	5		T38	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T213	1		T214	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T29	2		T215	16		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T216	19		T228	1		T178	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T5	1		T90	10		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T47	19		T174	14		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T37	1		T29	3		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	9		T32	9		T217	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T6	1		T27	1		T31	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	1		T218	1		T200	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T12	7		T13	1		T229	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	9		T13	1		T36	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1614	1			T2	2		T50	1		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T134	1		T198	1		T199	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T33	8		T145	1		T136	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T6	1		T37	7		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T5	1		T47	13		T48	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	11		T44	4		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T4	1		T5	1		T8	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T15	3		T32	16		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T8	3		T36	6		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	455	1			T3	1		T11	9		T48	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17441	1			T1	200		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T213	2		T214	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T29	1		T215	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T90	7		T218	1		T153	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T47	17		T40	6		T230	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T29	1		T153	1		T222	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	9		T147	12		T231	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T27	17		T31	4		T232	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T3	12		T218	1		T222	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T12	5		T13	1		T229	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T12	11		T13	1		T36	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	953	1			T110	11		T42	12		T134	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T198	14		T199	11		T230	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T33	7		T145	1		T136	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T37	15		T27	4		T38	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T47	11		T27	4		T225	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T11	9		T36	1		T26	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	11		T198	2		T17	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T15	2		T16	2		T80	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T8	6		T36	5		T26	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T11	7		T35	1		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T29	5		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T29	6		T90	8		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	10		T47	19		T174	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T5	1		T37	1		T194	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T32	1		T217	1		T218	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T6	1		T13	2		T27	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	13		T146	1		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1212	1			T2	2		T12	6		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	12		T13	2		T36	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T33	8		T145	2		T136	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T134	1		T38	5		T198	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T47	12		T27	5		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T6	1		T44	1		T36	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T4	1		T5	2		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T11	10		T37	16		T32	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	19		T17	11		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T48	1		T15	3		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T33	9		T138	16		T183	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T3	1		T11	8		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T36	8		T26	2		T39	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T134	6		T221	1		T188	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17613	1			T1	200		T3	40		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T29	1		T90	9		T153	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	8		T47	17		T174	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T139	13		T141	12		T233	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T32	8		T217	10		T147	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T31	6		T234	9		T235	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T146	11		T219	21		T97	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1199	1			T12	6		T236	30		T237	32
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	8		T36	2		T200	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T33	7		T136	13		T219	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T38	1		T199	11		T139	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T47	12		T46	4		T238	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T44	3		T232	9		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T48	2		T32	7		T225	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	10		T37	6		T32	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T8	17		T17	5		T220	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T48	3		T15	2		T138	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T33	9		T138	17		T239	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T11	8		T218	6		T137	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T36	3		T39	2		T141	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T188	18		T148	14		T18	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T240	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T213	3		T214	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T29	2		T215	16		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T216	1		T228	1		T178	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T5	1		T90	8		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T47	19		T174	1		T40	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T37	1		T29	4		T153	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	10		T32	1		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T6	1		T27	18		T31	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	13		T218	2		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T12	6		T13	2		T229	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T12	12		T13	2		T36	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T2	2		T50	1		T110	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T134	1		T198	15		T199	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T33	8		T145	2		T136	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T6	1		T37	16		T27	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T5	1		T47	12		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T11	10		T44	1		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	1		T5	1		T8	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T15	3		T32	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T8	7		T36	8		T26	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	419	1			T3	1		T11	8		T48	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17588	1			T1	200		T3	40		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T29	1		T215	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T216	18		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T90	9		T153	8		T219	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T47	17		T174	13		T230	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T241	5		T242	1		T157	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	8		T32	8		T217	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T31	6		T232	10		T139	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T200	2		T146	11		T219	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T12	6		T234	9		T147	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	8		T36	2		T146	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T236	30		T237	32		T173	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T199	11		T239	11		T230	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T33	7		T136	13		T46	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T37	6		T38	1		T232	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T47	12		T48	2		T225	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	10		T44	3		T40	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	15		T32	7		T17	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	2		T32	15		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T8	2		T36	3		T33	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T11	8		T48	3		T218	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

auto[0]

4136

1

T8

17

T11

18

T12

14

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26587

1

T1

200

T2

2

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21039

1

T1

200

T3

54

T5

1

auto[ADC_CTRL_FILTER_COND_OUT]

5548

1

T2

2

T4

1

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20886

1

T1

200

T3

40

T4

1

auto[1]

5701

1

T2

2

T3

14

T6

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22672

1

T1

200

T2

2

T3

42

auto[1]

3915

1

T3

12

T8

17

T11

16

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	78	1			T136	1		T147	15		T141	9
values[1]	516	1			T13	4		T44	4		T38	1
values[2]	694	1			T5	1		T37	22		T48	3
values[3]	717	1			T3	13		T5	1		T37	1
values[4]	580	1			T4	1		T6	1		T11	16
values[5]	730	1			T8	27		T15	5		T26	2
values[6]	723	1			T6	1		T12	20		T134	3
values[7]	623	1			T3	1		T36	2		T27	28
values[8]	776	1			T11	20		T12	12		T33	15
values[9]	3562	1			T2	2		T5	1		T8	9
minimum	17588	1			T1	200		T3	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	650	1			T13	4		T44	4		T38	1
values[1]	2826	1			T2	2		T5	1		T37	22
values[2]	703	1			T3	13		T5	1		T6	1
values[3]	615	1			T11	16		T36	11		T29	7
values[4]	682	1			T4	1		T8	27		T12	20
values[5]	716	1			T3	1		T6	1		T36	2
values[6]	840	1			T27	23		T201	1		T171	7
values[7]	669	1			T11	20		T12	12		T33	15
values[8]	1044	1			T5	1		T8	9		T13	18
values[9]	131	1			T47	16		T15	3		T32	9
minimum	17711	1			T1	200		T3	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

4136

1

T8

17

T11

18

T12

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	1		T141	22		T148	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	1		T44	4		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T48	3		T38	1		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1582	1			T2	2		T5	1		T37	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T3	1		T6	1		T47	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	1		T37	1		T32	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	9		T36	6		T29	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T31	7		T33	10		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T26	1		T40	7		T239	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T4	1		T8	16		T12	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T3	1		T134	1		T217	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	1		T36	1		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T27	1		T201	1		T171	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T27	1		T243	1		T244	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	11		T33	8		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	7		T221	1		T137	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T5	1		T13	9		T47	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T8	3		T26	1		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T47	9		T15	2		T90	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T32	9		T189	1		T190	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17480	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T20	2		T215	11		T213	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T13	1		T148	8		T243	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	1		T138	11		T194	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T16	2		T224	18		T245	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	975	1			T37	15		T110	11		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	12		T47	10		T36	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T229	2		T137	12		T194	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	7		T36	5		T29	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T31	4		T33	8		T38	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T26	1		T40	5		T142	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T8	11		T12	11		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T134	2		T218	1		T153	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T36	1		T27	4		T190	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T27	4		T171	2		T246	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T27	17		T244	10		T247	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T11	9		T33	7		T232	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	5		T137	11		T183	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T13	9		T47	11		T134	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T8	6		T26	14		T198	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T47	7		T15	1		T90	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T190	9		T248	11		T249	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T15	1		T29	5		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T215	15		T213	4		T250	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T147	11		T141	9		T96	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T136	1		T213	1		T251	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	1		T184	1		T141	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T13	1		T44	4		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T48	3		T38	1		T233	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	1		T37	7		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T3	1		T47	10		T36	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	1		T37	1		T48	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T6	1		T11	9		T36	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T4	1		T33	10		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T26	1		T29	3		T39	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T8	16		T15	3		T31	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T134	1		T217	11		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	1		T12	9		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T3	1		T27	1		T218	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T36	1		T27	2		T252	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	11		T33	8		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	7		T221	1		T183	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T5	1		T13	9		T47	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1796	1			T2	2		T8	3		T50	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17441	1			T1	200		T3	40		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T147	4		T253	9		T254	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T213	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T13	1		T148	8		T213	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T13	1		T194	11		T224	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T243	7		T224	18		T93	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T37	15		T35	1		T138	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	12		T47	10		T36	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T136	11		T229	2		T137	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T11	7		T36	5		T29	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T33	8		T38	1		T139	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T26	1		T29	1		T40	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T8	11		T15	2		T31	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T134	2		T153	1		T142	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	11		T190	6		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T27	4		T218	1		T210	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T36	1		T27	21		T252	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	9		T33	7		T199	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	5		T183	12		T139	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T13	9		T47	18		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1139	1			T8	6		T110	11		T42	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T29	5		T38	2