Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26587

1

T1

200

T2

2

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23059

1

T1

200

T2

2

T3

41

auto[ADC_CTRL_FILTER_COND_OUT]

3528

1

T3

13

T4

1

T6

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20592

1

T1

200

T3

54

T4

1

auto[1]

5995

1

T2

2

T5

1

T6

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22672

1

T1

200

T2

2

T3

42

auto[1]

3915

1

T3

12

T8

17

T11

16

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	223	1			T36	8		T27	10		T134	3
values[0]	16	1			T190	1		T311	15		-	-
values[1]	751	1			T4	1		T13	18		T35	2
values[2]	2765	1			T2	2		T13	2		T37	1
values[3]	843	1			T8	27		T135	1		T232	20
values[4]	758	1			T5	1		T48	3		T15	5
values[5]	645	1			T5	1		T6	1		T11	20
values[6]	730	1			T3	13		T13	2		T15	3
values[7]	867	1			T5	1		T6	1		T11	16
values[8]	450	1			T3	1		T31	11		T134	1
values[9]	951	1			T8	9		T12	20		T36	2
minimum	17588	1			T1	200		T3	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	655	1			T4	1		T37	1		T35	2
values[1]	2825	1			T2	2		T13	2		T50	1
values[2]	905	1			T8	27		T26	2		T135	1
values[3]	707	1			T5	2		T11	20		T48	3
values[4]	695	1			T3	13		T6	1		T37	22
values[5]	651	1			T6	1		T11	16		T13	2
values[6]	852	1			T5	1		T12	12		T47	20
values[7]	441	1			T3	1		T31	11		T134	1
values[8]	1028	1			T12	20		T36	8		T27	23
values[9]	66	1			T8	9		T36	2		T27	5
minimum	17762	1			T1	200		T3	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

4136

1

T8

17

T11

18

T12

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T37	1		T35	1		T32	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T4	1		T38	2		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1574	1			T2	2		T50	1		T47	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	1		T26	1		T232	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T26	1		T135	1		T136	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T8	16		T147	11		T140	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	2		T48	3		T36	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	11		T15	3		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T44	4		T38	5		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T3	1		T6	1		T37	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	1		T48	4		T137	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	1		T11	9		T90	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	1		T12	7		T218	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T47	10		T137	10		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	1		T31	7		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T137	1		T200	3		T147	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T27	1		T29	2		T217	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T12	9		T36	6		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T8	3		T27	1		T146	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T36	1		T312	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17496	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T32	9		T199	12		T259	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T35	1		T33	7		T218	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T230	9		T148	14		T243	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	924	1			T47	7		T110	11		T42	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	1		T26	14		T232	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T26	1		T136	11		T212	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T8	11		T147	4		T224	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T36	5		T29	1		T194	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	9		T15	2		T134	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T38	1		T145	1		T218	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	12		T37	15		T47	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	1		T137	11		T138	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	7		T90	7		T232	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	5		T40	5		T183	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T47	10		T222	4		T233	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T31	4		T230	13		T148	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T137	12		T147	12		T225	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T27	4		T29	1		T198	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	11		T36	2		T27	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T8	6		T27	4		T295	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T36	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	9		T15	1		T29	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T199	11		T191	5		T160	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T27	2		T146	3		T239	18
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T36	6		T134	1		T229	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T311	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T190	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T13	9		T35	1		T32	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T4	1		T32	9		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1577	1			T2	2		T37	1		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	1		T26	1		T153	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T135	1		T136	14		T212	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T8	16		T232	11		T147	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	1		T48	3		T26	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T15	3		T134	1		T234	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	1		T44	4		T36	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T6	1		T11	11		T37	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	1		T145	1		T137	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T15	2		T33	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	1		T12	7		T48	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T6	1		T11	9		T47	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	1		T31	7		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T200	3		T147	15		T220	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T8	3		T29	2		T217	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T12	9		T36	1		T27	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17441	1			T1	200		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T27	8		T254	15		T313	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T36	2		T134	2		T229	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T311	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T13	9		T35	1		T33	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T199	11		T148	14		T243	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	892	1			T47	7		T110	11		T42	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	1		T26	14		T153	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T136	11		T212	4		T153	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T8	11		T232	9		T147	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T26	1		T194	20		T142	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T15	2		T134	5		T198	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T36	5		T29	1		T38	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	9		T37	15		T47	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	1		T145	1		T137	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	12		T15	1		T33	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	5		T40	5		T183	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	7		T47	10		T222	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T31	4		T230	13		T148	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T147	12		T225	4		T310	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T8	6		T29	1		T198	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	11		T36	1		T27	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T29	5		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T37	1		T35	2		T32	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	1		T38	2		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T2	2		T50	1		T47	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	2		T26	15		T232	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T26	2		T135	1		T136	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T8	12		T147	5		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	2		T48	1		T36	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	10		T15	3		T134	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T44	1		T38	5		T145	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	13		T6	1		T37	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	2		T48	1		T137	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	1		T11	8		T90	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	1		T12	6		T218	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T47	11		T137	1		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	1		T31	5		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T137	13		T200	1		T147	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T27	5		T29	2		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T12	12		T36	6		T27	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T8	7		T27	5		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T36	2		T312	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17621	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T32	1		T199	12		T259	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T32	7		T33	7		T139	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T230	2		T148	11		T243	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1221	1			T47	8		T236	30		T237	32
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T232	10		T153	8		T235	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T136	13		T212	4		T239	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T8	15		T147	10		T140	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T48	2		T36	3		T219	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T11	10		T15	2		T234	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T44	3		T38	1		T139	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T37	6		T47	12		T32	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T48	3		T137	10		T138	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	8		T90	9		T232	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	6		T218	6		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T47	9		T137	9		T219	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T31	6		T230	11		T141	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T200	2		T147	14		T220	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T29	1		T217	10		T174	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T12	8		T36	2		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T8	2		T146	2		T314	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T13	8		T239	2		T210	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T32	8		T199	11		T259	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T27	10		T146	1		T239	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T36	6		T134	3		T229	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T311	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T190	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T13	10		T35	2		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	1		T32	1		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1238	1			T2	2		T37	1		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	2		T26	15		T153	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T135	1		T136	12		T212	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T8	12		T232	10		T147	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	1		T48	1		T26	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T15	3		T134	6		T234	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T5	1		T44	1		T36	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T6	1		T11	10		T37	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T13	2		T145	2		T137	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	13		T15	3		T33	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	1		T12	6		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T6	1		T11	8		T47	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T3	1		T31	5		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T200	1		T147	13		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T8	7		T29	2		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T12	12		T36	2		T27	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17588	1			T1	200		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T146	2		T239	17		T140	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T36	2		T39	1		T255	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T311	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	8		T32	7		T33	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T32	8		T199	11		T148	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1231	1			T47	8		T236	30		T237	32
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T153	8		T230	2		T235	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T136	13		T212	4		T141	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T8	15		T232	10		T147	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T48	2		T219	7		T142	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T15	2		T234	9		T188	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T44	3		T36	3		T38	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	10		T37	6		T47	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T137	10		T138	8		T248	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T33	9		T90	9		T232	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	6		T48	3		T218	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T11	8		T47	9		T137	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T31	6		T230	11		T141	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T200	2		T147	14		T220	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T8	2		T29	1		T217	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	8		T259	4		T142	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

auto[0]

4136

1

T8

17

T11

18

T12

14