Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26587

1

T1

200

T2

2

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23098

1

T1

200

T2

2

T3

40

auto[ADC_CTRL_FILTER_COND_OUT]

3489

1

T3

14

T5

2

T11

36

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20471

1

T1

194

T3

41

T5

2

auto[1]

6116

1

T1

6

T2

2

T3

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22672

1

T1

200

T2

2

T3

42

auto[1]

3915

1

T3

12

T8

17

T11

16

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	483	1			T1	6		T35	7		T36	5
values[0]	93	1			T218	7		T285	3		T302	3
values[1]	562	1			T6	1		T11	20		T12	12
values[2]	2752	1			T2	2		T4	1		T5	1
values[3]	720	1			T13	2		T47	20		T36	8
values[4]	639	1			T5	2		T8	27		T26	15
values[5]	856	1			T47	40		T29	4		T32	9
values[6]	593	1			T36	11		T26	2		T134	3
values[7]	810	1			T12	20		T37	22		T48	4
values[8]	892	1			T6	1		T8	9		T134	1
values[9]	1033	1			T3	14		T11	16		T37	1
minimum	17154	1			T1	194		T3	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	729	1			T6	1		T12	12		T13	20
values[1]	2777	1			T2	2		T4	1		T5	1
values[2]	703	1			T13	2		T36	8		T27	18
values[3]	744	1			T5	2		T8	27		T26	15
values[4]	747	1			T47	40		T36	11		T29	4
values[5]	646	1			T48	4		T26	2		T134	3
values[6]	833	1			T12	20		T37	22		T15	3
values[7]	737	1			T6	1		T8	9		T11	16
values[8]	748	1			T3	14		T44	4		T36	2
values[9]	273	1			T37	1		T48	3		T27	5
minimum	17650	1			T1	200		T3	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

4136

1

T8

17

T11

18

T12

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T6	1		T13	9		T15	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	7		T13	1		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1505	1			T2	2		T4	1		T50	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	1		T11	11		T47	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	1		T36	6		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T239	12		T147	15		T244	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	1		T8	16		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	1		T26	1		T201	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T29	3		T32	9		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T47	22		T36	6		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T48	4		T26	1		T137	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T134	1		T229	1		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T37	7		T38	1		T232	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T12	9		T15	2		T31	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T6	1		T8	3		T217	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	9		T134	1		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T36	1		T135	1		T38	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T3	2		T44	4		T29	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T48	3		T27	1		T199	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T37	1		T33	8		T276	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17455	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T161	19		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T13	9		T15	2		T33	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T12	5		T13	1		T27	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	900	1			T110	11		T35	1		T42	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	9		T47	10		T134	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	1		T36	2		T27	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T147	12		T149	13		T210	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T8	11		T136	11		T218	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T26	14		T230	9		T142	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T29	1		T145	1		T218	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T47	18		T36	5		T95	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T26	1		T39	2		T224	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T134	2		T229	2		T198	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T37	15		T232	9		T198	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	11		T15	1		T31	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T8	6		T137	11		T138	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T11	7		T149	9		T210	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T36	1		T38	1		T232	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	12		T29	1		T90	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T27	4		T199	11		T245	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T33	7		T315	14		T316	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T15	1		T29	5		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T161	15		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	459	1			T1	6		T35	7		T36	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T316	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T218	7		T302	1		T250	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T285	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T6	1		T13	9		T15	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T11	11		T12	7		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1520	1			T2	2		T4	1		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	1		T13	1		T32	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	1		T36	6		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T47	10		T189	1		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	1		T8	16		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	1		T26	1		T239	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T29	3		T32	9		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T47	22		T136	1		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T26	1		T137	10		T141	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T36	6		T134	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T37	7		T48	4		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T12	9		T15	2		T31	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T6	1		T8	3		T217	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T134	1		T38	1		T189	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T48	3		T36	1		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T3	2		T11	9		T37	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17007	1			T1	194		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T317	10		T318	11		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T316	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T302	2		T250	12		T181	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T285	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	9		T15	2		T188	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T11	9		T12	5		T27	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	898	1			T110	11		T35	1		T42	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	1		T134	5		T40	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	1		T36	2		T27	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T47	10		T147	12		T223	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	11		T136	11		T218	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T26	14		T142	14		T149	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T29	1		T145	1		T218	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T47	18		T230	9		T246	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T26	1		T215	15		T227	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T36	5		T134	2		T229	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T37	15		T232	9		T198	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	11		T15	1		T31	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T8	6		T137	11		T138	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T139	15		T149	9		T231	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T36	1		T27	4		T38	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T3	12		T11	7		T29	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T29	5		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T6	1		T13	10		T15	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	6		T13	2		T27	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T2	2		T4	1		T50	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	1		T11	10		T47	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	2		T36	6		T27	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T239	1		T147	13		T244	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	1		T8	12		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T5	1		T26	15		T201	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T29	4		T32	1		T145	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T47	20		T36	8		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T48	1		T26	2		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T134	3		T229	3		T198	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T37	16		T38	1		T232	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T12	12		T15	3		T31	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	1		T8	7		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	8		T134	1		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T36	2		T135	1		T38	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T3	14		T44	1		T29	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T48	1		T27	5		T199	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T37	1		T33	8		T276	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17603	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T161	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T13	8		T15	2		T32	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T12	6		T156	3		T319	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1171	1			T236	30		T237	32		T173	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	10		T47	9		T32	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T36	2		T138	8		T200	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T239	11		T147	14		T210	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T8	15		T136	13		T148	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T230	2		T142	12		T246	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T32	8		T234	9		T140	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T47	20		T36	3		T219	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T48	3		T137	9		T39	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T153	8		T139	18		T141	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T37	6		T232	10		T212	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	8		T31	6		T174	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T8	2		T217	10		T137	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	8		T146	2		T255	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T38	1		T232	9		T40	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T44	3		T29	1		T90	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T48	2		T199	11		T97	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T33	7		T276	9		T294	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T306	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T161	18		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	457	1			T1	6		T35	7		T36	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T316	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T218	1		T302	3		T250	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T285	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	1		T13	10		T15	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T11	10		T12	6		T27	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T2	2		T4	1		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	1		T13	2		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	2		T36	6		T27	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T47	11		T189	1		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	1		T8	12		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	1		T26	15		T239	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T29	4		T32	1		T145	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T47	20		T136	1		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T26	2		T137	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T36	8		T134	3		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T37	16		T48	1		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T12	12		T15	3		T31	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T6	1		T8	7		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T134	1		T38	1		T189	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T48	1		T36	2		T27	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T3	14		T11	8		T37	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17154	1			T1	194		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T317	9		T318	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T218	6		T250	11		T258	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	8		T15	2		T32	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T11	10		T12	6		T156	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1186	1			T33	9		T236	30		T237	32
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T32	7		T226	9		T319	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T36	2		T138	8		T200	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T47	9		T147	14		T289	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	15		T136	13		T141	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T239	11		T142	12		T210	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T32	8		T234	9		T140	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T47	20		T219	7		T230	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T137	9		T141	8		T215	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T36	3		T153	8		T139	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T37	6		T48	3		T232	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	8		T31	6		T174	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T8	2		T217	10		T137	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T146	2		T139	13		T255	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T48	2		T38	1		T232	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T11	8		T44	3		T29	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

auto[0]

4136

1

T8

17

T11

18

T12

14