Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26587

1

T1

200

T2

2

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23253

1

T1

200

T2

2

T3

40

auto[ADC_CTRL_FILTER_COND_OUT]

3334

1

T3

14

T4

1

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20497

1

T1

200

T3

41

T5

2

auto[1]

6090

1

T2

2

T3

13

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22672

1

T1

200

T2

2

T3

42

auto[1]

3915

1

T3

12

T8

17

T11

16

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	43	1			T300	1		T283	4		T320	29
values[0]	44	1			T12	20		T246	1		T216	12
values[1]	804	1			T3	13		T37	22		T35	2
values[2]	664	1			T13	2		T37	1		T47	20
values[3]	918	1			T36	11		T27	5		T38	6
values[4]	615	1			T8	9		T11	16		T136	1
values[5]	595	1			T4	1		T47	24		T48	4
values[6]	547	1			T3	1		T5	1		T32	16
values[7]	537	1			T5	1		T48	3		T26	2
values[8]	3000	1			T2	2		T5	1		T6	1
values[9]	1232	1			T6	1		T8	27		T11	20
minimum	17588	1			T1	200		T3	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	936	1			T3	13		T12	20		T13	2
values[1]	878	1			T37	1		T27	5		T32	9
values[2]	693	1			T36	11		T136	1		T218	2
values[3]	603	1			T8	9		T11	16		T47	24
values[4]	776	1			T3	1		T4	1		T5	1
values[5]	359	1			T48	3		T199	23		T212	9
values[6]	2818	1			T2	2		T5	1		T6	1
values[7]	787	1			T13	2		T29	4		T33	15
values[8]	1025	1			T5	1		T8	27		T11	20
values[9]	102	1			T6	1		T135	1		T38	1
minimum	17610	1			T1	200		T3	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

4136

1

T8

17

T11

18

T12

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T12	9		T37	7		T36	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T3	1		T13	1		T47	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T37	1		T33	10		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T27	1		T32	9		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T36	6		T137	1		T140	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T136	1		T218	1		T174	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	9		T47	13		T171	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T8	3		T38	5		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T234	10		T138	9		T40	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	1		T4	1		T5	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T212	5		T184	1		T220	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T48	3		T199	12		T39	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T2	2		T12	7		T50	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	1		T6	1		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T33	8		T135	1		T200	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T13	1		T29	3		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T5	1		T36	6		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T8	16		T11	11		T13	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T135	1		T136	14		T280	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T6	1		T38	1		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17441	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T288	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T12	11		T37	15		T36	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	12		T13	1		T47	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T33	8		T134	2		T153	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T27	4		T148	8		T142	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T36	5		T137	12		T252	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T218	1		T153	6		T139	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T11	7		T47	11		T244	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	6		T38	1		T153	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T138	11		T40	5		T16	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T188	21		T147	12		T149	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T212	4		T93	1		T240	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T199	11		T17	8		T222	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	958	1			T12	5		T110	11		T42	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T26	1		T27	17		T31	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T33	7		T39	2		T139	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	1		T29	1		T222	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T36	2		T15	1		T26	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T8	11		T11	9		T13	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T136	11		T256	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T149	9		T283	3		T284	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T29	5		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T288	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T320	10		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T300	1		T283	1		T321	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T12	9		T216	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T246	1		T287	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T37	7		T36	1		T15	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	1		T35	1		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T37	1		T134	1		T190	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	1		T47	10		T32	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T36	6		T137	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T27	1		T38	5		T218	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T11	9		T171	1		T219	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T8	3		T136	1		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T47	13		T40	7		T244	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T4	1		T48	4		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T32	16		T234	10		T138	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	1		T5	1		T199	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T32	8		T137	21		T212	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	1		T48	3		T26	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1629	1			T2	2		T5	1		T12	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	1		T29	3		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T15	2		T26	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	436	1			T6	1		T8	16		T11	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17441	1			T1	200		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T320	19		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T283	3		T321	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T12	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T287	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T37	15		T36	1		T15	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	12		T35	1		T229	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T134	2		T190	6		T142	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T13	1		T47	10		T194	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T36	5		T137	12		T153	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T27	4		T38	1		T218	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T11	7		T210	1		T81	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	6		T153	1		T139	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T47	11		T40	5		T244	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T188	21		T272	6		T241	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T138	11		T16	2		T93	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T199	11		T17	8		T147	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T137	11		T212	4		T245	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T26	1		T27	17		T31	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T12	5		T110	11		T42	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T29	1		T198	2		T40	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T15	1		T26	14		T136	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T8	11		T11	9		T13	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T29	5		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T12	12		T37	16		T36	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T3	13		T13	2		T47	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T37	1		T33	9		T134	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T27	5		T32	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T36	8		T137	13		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T136	1		T218	2		T174	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	8		T47	12		T171	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T8	7		T38	5		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T234	1		T138	12		T40	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	1		T4	1		T5	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T212	5		T184	1		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T48	1		T199	12		T39	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T2	2		T12	6		T50	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	1		T6	1		T26	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T33	8		T135	1		T200	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	2		T29	4		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T5	1		T36	6		T15	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T8	12		T11	10		T13	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T135	1		T136	12		T280	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T6	1		T38	1		T149	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17588	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T288	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T12	8		T37	6		T15	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T47	9		T217	10		T138	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T33	9		T243	8		T142	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T32	8		T148	14		T142	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T36	3		T140	13		T274	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T174	13		T153	8		T139	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	8		T47	12		T219	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T8	2		T38	1		T241	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T234	9		T138	8		T40	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T48	3		T188	18		T239	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T212	4		T220	13		T240	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T48	2		T199	11		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T12	6		T32	22		T236	30
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T31	6		T146	2		T139	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T33	7		T200	2		T39	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T146	11		T230	2		T276	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T36	2		T230	11		T246	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T8	15		T11	10		T13	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T136	13		T280	9		T256	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T284	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T288	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T320	20		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T300	1		T283	4		T321	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T12	12		T216	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T246	1		T287	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T37	16		T36	2		T15	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	13		T35	2		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T37	1		T134	3		T190	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	2		T47	11		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T36	8		T137	13		T153	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T27	5		T38	5		T218	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	8		T171	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	7		T136	1		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T47	12		T40	10		T244	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T4	1		T48	1		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T32	1		T234	1		T138	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T3	1		T5	1		T199	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T32	1		T137	13		T212	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	1		T48	1		T26	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T2	2		T5	1		T12	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	1		T29	4		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T15	3		T26	15		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T6	1		T8	12		T11	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17588	1			T1	200		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T320	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T12	8		T216	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T287	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T37	6		T15	2		T33	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T138	17		T244	13		T281	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T142	12		T46	4		T21	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T47	9		T32	8		T217	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T36	3		T140	13		T259	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T38	1		T174	13		T153	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	8		T219	21		T274	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T8	2		T139	10		T292	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T47	12		T40	2		T244	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T48	3		T188	18		T239	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T32	15		T234	9		T138	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T199	11		T39	1		T17	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T32	7		T137	19		T212	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T48	2		T31	6		T146	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T12	6		T36	2		T33	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T146	11		T230	2		T97	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T136	13		T147	10		T230	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T8	15		T11	10		T13	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

auto[0]

4136

1

T8

17

T11

18

T12

14