Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26587

1

T1

200

T2

2

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23086

1

T1

200

T2

2

T3

53

auto[ADC_CTRL_FILTER_COND_OUT]

3501

1

T3

1

T5

2

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20718

1

T1

200

T3

40

T4

1

auto[1]

5869

1

T2

2

T3

14

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22672

1

T1

200

T2

2

T3

42

auto[1]

3915

1

T3

12

T8

17

T11

16

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	188	1			T47	24		T15	3		T230	12
values[0]	69	1			T40	12		T270	13		T322	9
values[1]	666	1			T5	1		T11	20		T13	2
values[2]	856	1			T6	1		T12	20		T135	1
values[3]	599	1			T4	1		T5	1		T8	9
values[4]	801	1			T8	27		T11	16		T47	16
values[5]	655	1			T37	23		T35	2		T32	24
values[6]	690	1			T3	1		T48	4		T27	18
values[7]	651	1			T36	8		T27	5		T32	9
values[8]	786	1			T5	1		T31	11		T134	1
values[9]	3038	1			T2	2		T3	13		T6	1
minimum	17588	1			T1	200		T3	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	887	1			T11	20		T13	2		T27	5
values[1]	649	1			T6	1		T12	32		T135	1
values[2]	726	1			T4	1		T5	1		T8	9
values[3]	686	1			T8	27		T47	16		T36	13
values[4]	831	1			T37	23		T35	2		T26	2
values[5]	553	1			T3	1		T48	4		T134	3
values[6]	2845	1			T2	2		T50	1		T110	12
values[7]	790	1			T5	1		T15	5		T31	11
values[8]	821	1			T3	13		T6	1		T13	20
values[9]	65	1			T44	4		T141	11		T227	11
minimum	17734	1			T1	200		T3	40		T5	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

4136

1

T8

17

T11

18

T12

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T13	1		T27	1		T33	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T11	11		T184	1		T147	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T12	16		T135	1		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T6	1		T38	5		T137	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T4	1		T5	1		T48	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T8	3		T11	9		T29	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T47	9		T36	1		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T8	16		T36	6		T32	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T37	8		T26	1		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T35	1		T184	1		T262	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T135	1		T218	1		T194	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	1		T48	4		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1575	1			T2	2		T50	1		T110	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T36	6		T27	1		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T15	3		T218	7		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	1		T31	7		T134	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	1		T6	1		T13	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T13	1		T47	23		T15	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T44	4		T227	8		T275	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T141	11		T84	1		T269	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17496	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T5	1		T282	1		T245	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T13	1		T27	4		T33	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	9		T147	12		T222	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	16		T145	1		T218	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T38	1		T139	5		T148	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T33	7		T148	13		T246	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T8	6		T11	7		T29	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T47	7		T36	1		T26	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	11		T36	5		T198	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T37	15		T26	1		T27	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T35	1		T264	11		T265	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T218	1		T194	11		T231	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T134	2		T229	2		T198	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	971	1			T110	11		T42	12		T266	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T36	2		T27	4		T142	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T15	2		T137	12		T194	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T31	4		T134	5		T136	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	12		T13	9		T232	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	1		T47	21		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T227	3		T268	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T269	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	1		T29	5		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T245	13		T270	4		T323	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T210	3		T275	8		T324	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T47	13		T15	2		T230	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T40	7		T322	1		T271	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T270	9		T107	14		T325	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T13	1		T27	1		T33	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	1		T11	11		T184	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T12	9		T135	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T6	1		T38	5		T137	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	1		T5	1		T12	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T8	3		T29	2		T232	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T47	9		T36	1		T26	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T8	16		T11	9		T36	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T37	8		T32	16		T212	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T35	1		T32	8		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T27	1		T135	1		T218	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	1		T48	4		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T32	9		T219	13		T224	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T36	6		T27	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T218	7		T137	1		T194	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	1		T31	7		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1570	1			T2	2		T3	1		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T13	1		T47	10		T134	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17441	1			T1	200		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T210	1		T161	12		T268	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T47	11		T15	1		T230	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T40	5		T322	8		T271	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T270	4		T107	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	1		T27	4		T33	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	9		T222	10		T233	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	11		T145	1		T218	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T38	1		T139	5		T147	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	5		T33	7		T246	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T8	6		T29	1		T232	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T47	7		T36	1		T26	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	11		T11	7		T36	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T37	15		T212	4		T153	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T35	1		T265	14		T285	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T27	17		T218	1		T194	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T229	2		T198	2		T40	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T224	8		T231	10		T272	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T36	2		T27	4		T134	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T137	12		T194	9		T139	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T31	4		T138	15		T188	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	951	1			T3	12		T13	9		T110	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	1		T47	10		T134	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T29	5		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T13	2		T27	5		T33	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T11	10		T184	1		T147	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	18		T135	1		T145	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T6	1		T38	5		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T4	1		T5	1		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	7		T11	8		T29	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T47	8		T36	2		T26	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T8	12		T36	8		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T37	17		T26	2		T27	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T35	2		T184	1		T262	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T135	1		T218	2		T194	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	1		T48	1		T134	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T2	2		T50	1		T110	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T36	6		T27	5		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T15	3		T218	1		T137	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	1		T31	5		T134	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	13		T6	1		T13	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T13	2		T47	23		T15	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T44	1		T227	8		T275	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T141	1		T84	1		T269	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17621	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T5	1		T282	1		T245	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T33	9		T234	9		T138	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	10		T147	14		T97	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	14		T219	7		T147	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T38	1		T137	9		T139	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T48	2		T33	7		T239	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T8	2		T11	8		T29	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T47	8		T90	9		T212	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T8	15		T36	3		T32	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T37	6		T32	15		T153	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T264	20		T265	12		T34	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T157	7		T152	16		T273	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T48	3		T17	5		T147	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1222	1			T32	8		T236	30		T237	32
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T36	2		T274	13		T220	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T15	2		T218	6		T200	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T31	6		T217	10		T136	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	8		T232	10		T210	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T47	21		T174	13		T239	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T44	3		T227	3		T275	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T141	10		T269	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T40	2		T239	17		T326	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T270	4		T107	13		T327	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T210	2		T275	1		T324	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T47	12		T15	3		T230	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T40	10		T322	9		T271	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T270	9		T107	14		T325	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	2		T27	5		T33	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	1		T11	10		T184	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	12		T135	1		T145	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	1		T38	5		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	1		T5	1		T12	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T8	7		T29	2		T232	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T47	8		T36	2		T26	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T8	12		T11	8		T36	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T37	17		T32	1		T212	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T35	2		T32	1		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T27	18		T135	1		T218	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T3	1		T48	1		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T32	1		T219	1		T224	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T36	6		T27	5		T134	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T218	1		T137	13		T194	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	1		T31	5		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T2	2		T3	13		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T13	2		T47	11		T134	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17588	1			T1	200		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T210	2		T275	7		T161	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T47	12		T230	2		T141	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T40	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T270	4		T107	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T33	9		T234	9		T138	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T11	10		T276	9		T248	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	8		T139	10		T219	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T38	1		T137	9		T139	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	6		T48	2		T33	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T8	2		T29	1		T232	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	8		T90	9		T171	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T8	15		T11	8		T36	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T37	6		T32	15		T212	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T32	7		T265	12		T34	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T252	16		T157	7		T152	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T48	3		T17	5		T147	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T32	8		T219	12		T226	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T36	2		T274	13		T220	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T218	6		T39	1		T139	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T31	6		T217	10		T138	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T13	8		T44	3		T15	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T47	9		T136	13		T199	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

auto[0]

4136

1

T8

17

T11

18

T12

14