Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26587

1

T1

200

T2

2

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22974

1

T1

200

T2

2

T3

54

auto[ADC_CTRL_FILTER_COND_OUT]

3613

1

T5

1

T11

16

T12

32

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20683

1

T1

200

T3

53

T4

1

auto[1]

5904

1

T2

2

T3

1

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22672

1

T1

200

T2

2

T3

42

auto[1]

3915

1

T3

12

T8

17

T11

16

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	236	1			T11	16		T35	2		T27	5
values[0]	66	1			T39	5		T139	14		T142	27
values[1]	572	1			T47	20		T27	5		T39	5
values[2]	753	1			T4	1		T8	27		T12	12
values[3]	837	1			T47	24		T33	18		T134	1
values[4]	2719	1			T2	2		T3	1		T5	1
values[5]	721	1			T12	20		T44	4		T26	2
values[6]	638	1			T6	2		T13	2		T36	8
values[7]	641	1			T3	13		T5	1		T13	18
values[8]	901	1			T13	2		T37	22		T15	3
values[9]	915	1			T5	1		T8	9		T11	20
minimum	17588	1			T1	200		T3	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	627	1			T27	5		T137	13		T16	6
values[1]	704	1			T4	1		T8	27		T12	12
values[2]	775	1			T47	24		T134	1		T194	10
values[3]	2832	1			T2	2		T3	1		T5	1
values[4]	702	1			T12	20		T13	2		T26	2
values[5]	618	1			T6	2		T13	18		T36	8
values[6]	717	1			T3	13		T5	1		T37	1
values[7]	951	1			T5	1		T8	9		T13	2
values[8]	689	1			T11	36		T47	16		T48	4
values[9]	193	1			T29	4		T221	1		T189	1
minimum	17779	1			T1	200		T3	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

4136

1

T8

17

T11

18

T12

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T27	1		T16	4		T139	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T137	1		T140	9		T243	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T4	1		T8	16		T33	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	7		T47	10		T32	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T194	1		T189	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T47	13		T134	1		T40	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1593	1			T2	2		T3	1		T5	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T32	8		T138	18		T212	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T13	1		T135	1		T174	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T12	9		T26	1		T90	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T6	2		T218	1		T138	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T13	9		T36	6		T146	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	1		T37	1		T48	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	1		T36	6		T15	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T5	1		T8	3		T37	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T13	1		T31	7		T32	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T11	11		T47	9		T48	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	9		T35	1		T29	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T221	1		T226	14		T332	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T29	3		T189	1		T256	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17505	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T139	9		T142	13		T152	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T27	4		T16	2		T139	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T137	12		T243	7		T231	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	11		T33	8		T229	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	5		T47	10		T183	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T194	9		T153	1		T230	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T47	11		T40	5		T188	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	905	1			T110	11		T42	12		T266	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T138	15		T212	4		T17	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T13	1		T190	6		T285	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	11		T26	1		T90	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T218	1		T138	11		T246	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T13	9		T36	2		T147	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	12		T36	1		T26	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T36	5		T15	2		T38	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	6		T37	15		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T13	1		T31	4		T136	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	9		T47	7		T27	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	7		T35	1		T29	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T226	11		T332	4		T260	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T29	1		T256	9		T293	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T15	1		T29	5		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T139	5		T142	14		T295	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T27	1		T221	1		T262	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T11	9		T35	1		T29	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T39	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T139	9		T142	13		T295	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T27	1		T39	5		T153	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T47	10		T140	9		T243	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T4	1		T8	16		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	7		T32	16		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T33	10		T194	1		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T47	13		T134	1		T40	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1590	1			T2	2		T3	1		T5	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T32	8		T138	18		T212	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T44	4		T135	1		T199	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T12	9		T26	1		T234	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T13	1		T218	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T36	6		T90	10		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	1		T37	1		T48	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	1		T13	9		T36	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T37	7		T15	2		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T13	1		T31	7		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T5	1		T8	3		T11	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T29	2		T32	9		T134	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17441	1			T1	200		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T27	4		T226	11		T242	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T11	7		T35	1		T29	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T39	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T139	5		T142	14		T295	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T27	4		T153	6		T16	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T47	10		T243	7		T235	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T8	11		T229	2		T147	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	5		T137	12		T147	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T33	8		T194	9		T198	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T47	11		T40	5		T183	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	903	1			T110	11		T42	12		T266	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T138	15		T212	4		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T199	11		T190	6		T285	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	11		T26	1		T137	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	1		T218	1		T246	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T36	2		T90	7		T147	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	12		T36	1		T26	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	9		T36	5		T15	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T37	15		T15	1		T134	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	1		T31	4		T40	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T8	6		T11	9		T47	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T29	1		T134	5		T136	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T29	5		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T27	5		T16	6		T139	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T137	13		T140	1		T243	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T4	1		T8	12		T33	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	6		T47	11		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T194	10		T189	1		T153	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T47	12		T134	1		T40	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T2	2		T3	1		T5	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T32	1		T138	16		T212	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T135	1		T174	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T12	12		T26	2		T90	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T6	2		T218	2		T138	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	10		T36	6		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T3	13		T37	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	1		T36	8		T15	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T5	1		T8	7		T37	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T13	2		T31	5		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	10		T47	8		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	8		T35	2		T29	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T221	1		T226	12		T332	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T29	4		T189	1		T256	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17635	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T139	6		T142	15		T152	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T139	10		T230	2		T148	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T140	8		T243	8		T235	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	15		T33	9		T147	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	6		T47	9		T32	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T219	7		T230	11		T274	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T47	12		T40	2		T188	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T44	3		T236	30		T217	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T32	7		T138	17		T212	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T174	13		T296	8		T247	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	8		T90	9		T234	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T138	8		T246	14		T333	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	8		T36	2		T146	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T48	2		T137	9		T139	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T36	3		T15	2		T38	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T8	2		T37	6		T33	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T31	6		T32	8		T136	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	10		T47	8		T48	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T11	8		T29	1		T232	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T226	13		T332	4		T260	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T256	9		T293	9		T334	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T39	3		T153	8		T239	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T139	8		T142	12		T152	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T27	5		T221	1		T262	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T11	8		T35	2		T29	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T39	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T139	6		T142	15		T295	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T27	5		T39	4		T153	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T47	11		T140	1		T243	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T4	1		T8	12		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	6		T32	1		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T33	9		T194	10		T198	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T47	12		T134	1		T40	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T2	2		T3	1		T5	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T32	1		T138	16		T212	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T44	1		T135	1		T199	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T12	12		T26	2		T234	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	2		T13	2		T218	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T36	6		T90	8		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	13		T37	1		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	1		T13	10		T36	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T37	16		T15	3		T134	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T13	2		T31	5		T40	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T5	1		T8	7		T11	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T29	2		T32	1		T134	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17588	1			T1	200		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T226	13		T242	1		T332	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T11	8		T232	10		T239	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T39	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T139	8		T142	12		T295	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T39	1		T153	8		T139	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T47	9		T140	8		T243	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	15		T147	10		T230	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	6		T32	15		T147	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T33	9		T219	7		T274	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T47	12		T40	2		T188	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1238	1			T236	30		T217	10		T237	32
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T32	7		T138	17		T212	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T44	3		T199	11		T146	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	8		T234	9		T137	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T174	13		T246	14		T296	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T36	2		T90	9		T146	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T48	2		T138	8		T139	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T13	8		T36	3		T15	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T37	6		T137	9		T141	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T31	6		T276	13		T86	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T8	2		T11	10		T47	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T29	1		T32	8		T136	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

auto[0]

4136

1

T8

17

T11

18

T12

14