Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26587

1

T1

200

T2

2

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20998

1

T1

200

T3

54

T5

1

auto[ADC_CTRL_FILTER_COND_OUT]

5589

1

T2

2

T4

1

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20871

1

T1

200

T3

40

T4

1

auto[1]

5716

1

T2

2

T3

14

T6

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22672

1

T1

200

T2

2

T3

42

auto[1]

3915

1

T3

12

T8

17

T11

16

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	326	1			T5	1		T47	24		T32	9
values[0]	43	1			T136	1		T147	15		T96	1
values[1]	567	1			T13	4		T44	4		T38	1
values[2]	599	1			T5	1		T48	3		T35	2
values[3]	783	1			T3	13		T5	1		T37	23
values[4]	573	1			T4	1		T6	1		T11	16
values[5]	690	1			T8	27		T15	5		T26	2
values[6]	760	1			T6	1		T12	20		T134	3
values[7]	689	1			T3	1		T36	2		T27	28
values[8]	740	1			T11	20		T12	12		T33	15
values[9]	3229	1			T2	2		T8	9		T13	18
minimum	17588	1			T1	200		T3	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	525	1			T13	4		T44	4		T38	1
values[1]	2883	1			T2	2		T5	1		T37	22
values[2]	715	1			T3	13		T5	1		T6	1
values[3]	593	1			T4	1		T11	16		T36	11
values[4]	693	1			T8	27		T12	20		T15	5
values[5]	700	1			T3	1		T6	1		T36	2
values[6]	831	1			T27	23		T201	1		T171	7
values[7]	651	1			T11	20		T12	12		T33	15
values[8]	1061	1			T5	1		T8	9		T13	18
values[9]	140	1			T15	3		T32	9		T90	17
minimum	17795	1			T1	200		T3	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

4136

1

T8

17

T11

18

T12

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T13	1		T141	13		T148	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T13	1		T44	4		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T48	3		T38	1		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1594	1			T2	2		T5	1		T37	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T3	1		T6	1		T47	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	1		T37	1		T32	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	9		T36	6		T29	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	1		T29	2		T31	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T26	1		T39	5		T40	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T8	16		T12	9		T15	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T3	1		T134	1		T217	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	1		T36	1		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T27	1		T201	1		T171	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T27	1		T243	1		T244	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	11		T33	8		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	7		T221	1		T137	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T5	1		T13	9		T47	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T8	3		T26	1		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T15	2		T90	10		T95	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T32	9		T189	1		T190	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17512	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T136	1		T194	1		T215	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T13	1		T148	8		T243	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	1		T138	11		T224	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T16	2		T224	18		T245	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	984	1			T37	15		T110	11		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	12		T47	10		T36	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T229	2		T137	12		T194	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	7		T36	5		T29	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T29	1		T31	4		T33	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T26	1		T40	5		T142	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T8	11		T12	11		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T134	2		T218	1		T153	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T36	1		T27	4		T190	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T27	4		T171	2		T210	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T27	17		T244	10		T191	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	9		T33	7		T232	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	5		T137	11		T183	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T13	9		T47	18		T134	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T8	6		T26	14		T198	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T15	1		T90	7		T95	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T190	9		T248	11		T335	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	1		T29	5		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T194	11		T215	15		T292	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T5	1		T47	13		T90	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T32	9		T188	19		T246	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T147	11		T96	1		T213	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T136	1		T254	11		T318	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	1		T141	22		T148	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	1		T44	4		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T48	3		T38	1		T184	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	1		T35	1		T138	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T3	1		T47	10		T232	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	1		T37	8		T48	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T6	1		T11	9		T36	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	1		T29	2		T33	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T26	1		T29	3		T39	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T8	16		T15	3		T31	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T134	1		T217	11		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	1		T12	9		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T3	1		T27	1		T218	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T36	1		T27	2		T252	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	11		T33	8		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	7		T221	1		T183	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T13	9		T47	9		T15	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1710	1			T2	2		T8	3		T50	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17441	1			T1	200		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T47	11		T90	7		T148	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T188	21		T245	8		T336	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T147	4		T213	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T254	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T13	1		T148	8		T243	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T13	1		T194	11		T224	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T224	18		T93	1		T245	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T35	1		T138	11		T139	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	12		T47	10		T232	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T37	15		T136	11		T229	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	7		T36	7		T198	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T29	1		T33	8		T38	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T26	1		T29	1		T40	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T8	11		T15	2		T31	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T134	2		T153	1		T142	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	11		T190	6		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T27	4		T218	1		T171	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T36	1		T27	21		T252	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	9		T33	7		T232	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	5		T183	12		T139	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	9		T47	7		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1047	1			T8	6		T110	11		T42	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T29	5		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T13	2		T141	1		T148	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	2		T44	1		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T48	1		T38	1		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1325	1			T2	2		T5	1		T37	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T3	13		T6	1		T47	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	1		T37	1		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	8		T36	8		T29	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T4	1		T29	2		T31	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T26	2		T39	4		T40	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	12		T12	12		T15	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	1		T134	3		T217	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	1		T36	2		T27	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T27	5		T201	1		T171	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T27	18		T243	1		T244	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	10		T33	8		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	6		T221	1		T137	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T5	1		T13	10		T47	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T8	7		T26	15		T198	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T15	3		T90	8		T95	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T32	1		T189	1		T190	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17637	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T136	1		T194	12		T215	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T141	12		T148	14		T220	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T44	3		T137	9		T138	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	2		T146	11		T97	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1253	1			T37	6		T48	3		T32	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T47	9		T36	2		T232	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T32	7		T219	21		T46	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	8		T36	3		T259	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T29	1		T31	6		T33	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T39	1		T40	2		T239	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T8	15		T12	8		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T217	10		T140	7		T274	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T200	2		T230	2		T252	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T171	4		T140	13		T210	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T244	6		T216	11		T247	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	10		T33	7		T232	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	6		T137	10		T139	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T13	8		T47	20		T138	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T8	2		T188	18		T17	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T90	9		T157	7		T249	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T32	8		T248	10		T335	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T147	10		T141	8		T253	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T215	10		T292	16		T250	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T5	1		T47	12		T90	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T32	1		T188	22		T246	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T147	5		T96	1		T213	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T136	1		T254	12		T318	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	2		T141	2		T148	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	2		T44	1		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	1		T38	1		T184	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T5	1		T35	2		T138	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T3	13		T47	11		T232	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	1		T37	17		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	1		T11	8		T36	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	1		T29	2		T33	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T26	2		T29	4		T39	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T8	12		T15	3		T31	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T134	3		T217	1		T153	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	1		T12	12		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	1		T27	5		T218	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T36	2		T27	23		T252	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T11	10		T33	8		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	6		T221	1		T183	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T13	10		T47	8		T15	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1403	1			T2	2		T8	7		T50	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17588	1			T1	200		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T47	12		T90	9		T274	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T32	8		T188	18		T335	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T147	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T254	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T141	20		T148	14		T220	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T44	3		T137	9		T219	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T48	2		T175	14		T254	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T138	8		T139	13		T220	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T47	9		T232	9		T146	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T37	6		T48	3		T32	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T11	8		T36	5		T146	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T29	1		T33	9		T38	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T39	1		T40	2		T259	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T8	15		T15	2		T31	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T217	10		T239	2		T140	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	8		T200	2		T230	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T171	4		T140	13		T210	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T252	16		T216	11		T260	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	10		T33	7		T232	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	6		T139	10		T244	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	8		T47	8		T138	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1354	1			T8	2		T236	30		T237	32

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

auto[0]

4136

1

T8

17

T11

18

T12

14