wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
161 |
1 |
|
|
T13 |
2 |
|
T141 |
2 |
|
T148 |
9 |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
207 |
1 |
|
|
T13 |
2 |
|
T44 |
1 |
|
T38 |
1 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
166 |
1 |
|
|
T48 |
1 |
|
T38 |
1 |
|
T184 |
1 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
1317 |
1 |
|
|
T2 |
2 |
|
T5 |
1 |
|
T37 |
16 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
259 |
1 |
|
|
T3 |
13 |
|
T6 |
1 |
|
T47 |
11 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
151 |
1 |
|
|
T5 |
1 |
|
T37 |
1 |
|
T32 |
1 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
217 |
1 |
|
|
T11 |
8 |
|
T36 |
8 |
|
T29 |
6 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
135 |
1 |
|
|
T31 |
5 |
|
T33 |
9 |
|
T135 |
1 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
187 |
1 |
|
|
T26 |
2 |
|
T40 |
10 |
|
T239 |
1 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
170 |
1 |
|
|
T4 |
1 |
|
T8 |
12 |
|
T12 |
12 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
201 |
1 |
|
|
T3 |
1 |
|
T134 |
3 |
|
T217 |
1 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
173 |
1 |
|
|
T6 |
1 |
|
T36 |
2 |
|
T27 |
5 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
214 |
1 |
|
|
T27 |
5 |
|
T201 |
1 |
|
T171 |
3 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
210 |
1 |
|
|
T27 |
18 |
|
T243 |
1 |
|
T244 |
11 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
157 |
1 |
|
|
T11 |
10 |
|
T33 |
8 |
|
T135 |
1 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
213 |
1 |
|
|
T12 |
6 |
|
T221 |
1 |
|
T137 |
12 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
294 |
1 |
|
|
T5 |
1 |
|
T13 |
10 |
|
T47 |
12 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
295 |
1 |
|
|
T8 |
7 |
|
T26 |
15 |
|
T198 |
3 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
34 |
1 |
|
|
T47 |
8 |
|
T15 |
3 |
|
T90 |
8 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
36 |
1 |
|
|
T32 |
1 |
|
T189 |
1 |
|
T190 |
10 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
17618 |
1 |
|
|
T1 |
200 |
|
T3 |
40 |
|
T7 |
20 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_OUT] |
36 |
1 |
|
|
T20 |
2 |
|
T215 |
16 |
|
T213 |
5 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
134 |
1 |
|
|
T141 |
20 |
|
T148 |
14 |
|
T220 |
4 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
148 |
1 |
|
|
T44 |
3 |
|
T137 |
9 |
|
T138 |
8 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
103 |
1 |
|
|
T48 |
2 |
|
T146 |
11 |
|
T97 |
2 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
1240 |
1 |
|
|
T37 |
6 |
|
T48 |
3 |
|
T32 |
15 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
169 |
1 |
|
|
T47 |
9 |
|
T36 |
2 |
|
T232 |
9 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
124 |
1 |
|
|
T32 |
7 |
|
T139 |
8 |
|
T219 |
21 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
138 |
1 |
|
|
T11 |
8 |
|
T36 |
3 |
|
T29 |
1 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
125 |
1 |
|
|
T31 |
6 |
|
T33 |
9 |
|
T38 |
1 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
155 |
1 |
|
|
T40 |
2 |
|
T239 |
2 |
|
T255 |
13 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
170 |
1 |
|
|
T8 |
15 |
|
T12 |
8 |
|
T15 |
2 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
192 |
1 |
|
|
T217 |
10 |
|
T39 |
1 |
|
T140 |
7 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
150 |
1 |
|
|
T200 |
2 |
|
T230 |
2 |
|
T252 |
16 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
198 |
1 |
|
|
T171 |
4 |
|
T140 |
13 |
|
T246 |
14 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
218 |
1 |
|
|
T244 |
6 |
|
T216 |
11 |
|
T247 |
11 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
148 |
1 |
|
|
T11 |
10 |
|
T33 |
7 |
|
T232 |
10 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
151 |
1 |
|
|
T12 |
6 |
|
T137 |
10 |
|
T139 |
10 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
232 |
1 |
|
|
T13 |
8 |
|
T47 |
12 |
|
T138 |
17 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
223 |
1 |
|
|
T8 |
2 |
|
T188 |
18 |
|
T17 |
5 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
26 |
1 |
|
|
T47 |
8 |
|
T90 |
9 |
|
T256 |
9 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
35 |
1 |
|
|
T32 |
8 |
|
T248 |
10 |
|
T249 |
6 |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
36 |
1 |
|
|
T147 |
10 |
|
T257 |
17 |
|
T258 |
9 |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_OUT] |
21 |
1 |
|
|
T215 |
10 |
|
T250 |
11 |
|
- |
- |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
29 |
1 |
|
|
T147 |
5 |
|
T141 |
1 |
|
T96 |
1 |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
9 |
1 |
|
|
T136 |
1 |
|
T213 |
5 |
|
T251 |
1 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
125 |
1 |
|
|
T13 |
2 |
|
T184 |
1 |
|
T141 |
1 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
171 |
1 |
|
|
T13 |
2 |
|
T44 |
1 |
|
T38 |
1 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
172 |
1 |
|
|
T48 |
1 |
|
T38 |
1 |
|
T233 |
1 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
258 |
1 |
|
|
T5 |
1 |
|
T37 |
16 |
|
T35 |
2 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
264 |
1 |
|
|
T3 |
13 |
|
T47 |
11 |
|
T36 |
6 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
135 |
1 |
|
|
T5 |
1 |
|
T37 |
1 |
|
T48 |
1 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
151 |
1 |
|
|
T6 |
1 |
|
T11 |
8 |
|
T36 |
8 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
164 |
1 |
|
|
T4 |
1 |
|
T33 |
9 |
|
T135 |
1 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
275 |
1 |
|
|
T26 |
2 |
|
T29 |
4 |
|
T39 |
4 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
146 |
1 |
|
|
T8 |
12 |
|
T15 |
3 |
|
T31 |
5 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
157 |
1 |
|
|
T134 |
3 |
|
T217 |
1 |
|
T153 |
2 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
201 |
1 |
|
|
T6 |
1 |
|
T12 |
12 |
|
T135 |
1 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
201 |
1 |
|
|
T3 |
1 |
|
T27 |
5 |
|
T218 |
2 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
114 |
1 |
|
|
T36 |
2 |
|
T27 |
23 |
|
T252 |
14 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
198 |
1 |
|
|
T11 |
10 |
|
T33 |
8 |
|
T135 |
1 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
230 |
1 |
|
|
T12 |
6 |
|
T221 |
1 |
|
T183 |
13 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
348 |
1 |
|
|
T5 |
1 |
|
T13 |
10 |
|
T47 |
20 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
1515 |
1 |
|
|
T2 |
2 |
|
T8 |
7 |
|
T50 |
1 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
17588 |
1 |
|
|
T1 |
200 |
|
T3 |
40 |
|
T7 |
20 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
40 |
1 |
|
|
T147 |
10 |
|
T141 |
8 |
|
T253 |
12 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
102 |
1 |
|
|
T141 |
12 |
|
T148 |
14 |
|
T220 |
4 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
118 |
1 |
|
|
T44 |
3 |
|
T137 |
9 |
|
T219 |
7 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
91 |
1 |
|
|
T48 |
2 |
|
T243 |
8 |
|
T175 |
10 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
173 |
1 |
|
|
T37 |
6 |
|
T32 |
7 |
|
T138 |
8 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
198 |
1 |
|
|
T47 |
9 |
|
T36 |
2 |
|
T232 |
9 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
120 |
1 |
|
|
T48 |
3 |
|
T32 |
15 |
|
T136 |
13 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
100 |
1 |
|
|
T11 |
8 |
|
T36 |
3 |
|
T29 |
1 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
165 |
1 |
|
|
T33 |
9 |
|
T38 |
1 |
|
T174 |
13 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
162 |
1 |
|
|
T39 |
1 |
|
T40 |
2 |
|
T259 |
4 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
147 |
1 |
|
|
T8 |
15 |
|
T15 |
2 |
|
T31 |
6 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
199 |
1 |
|
|
T217 |
10 |
|
T239 |
2 |
|
T140 |
7 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
166 |
1 |
|
|
T12 |
8 |
|
T200 |
2 |
|
T230 |
2 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
194 |
1 |
|
|
T140 |
13 |
|
T210 |
2 |
|
T93 |
12 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
114 |
1 |
|
|
T252 |
16 |
|
T260 |
4 |
|
T261 |
11 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
166 |
1 |
|
|
T11 |
10 |
|
T33 |
7 |
|
T218 |
6 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
182 |
1 |
|
|
T12 |
6 |
|
T139 |
10 |
|
T17 |
5 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
279 |
1 |
|
|
T13 |
8 |
|
T47 |
20 |
|
T90 |
9 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
1420 |
1 |
|
|
T8 |
2 |
|
T32 |
8 |
|
T236 |
30 |