Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26587

1

T1

200

T2

2

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23117

1

T1

200

T2

2

T3

53

auto[ADC_CTRL_FILTER_COND_OUT]

3470

1

T3

1

T5

2

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20628

1

T1

200

T3

40

T4

1

auto[1]

5959

1

T2

2

T3

14

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22672

1

T1

200

T2

2

T3

42

auto[1]

3915

1

T3

12

T8

17

T11

16

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	3	1			T15	3		-	-		-	-
values[0]	74	1			T11	20		T13	2		T40	12
values[1]	692	1			T5	1		T27	5		T33	18
values[2]	852	1			T6	1		T12	20		T135	1
values[3]	572	1			T4	1		T5	1		T8	9
values[4]	778	1			T11	16		T37	1		T47	16
values[5]	679	1			T8	27		T37	22		T35	2
values[6]	684	1			T3	1		T48	4		T27	18
values[7]	621	1			T36	8		T27	5		T229	3
values[8]	770	1			T5	1		T31	11		T32	9
values[9]	3274	1			T2	2		T3	13		T6	1
minimum	17588	1			T1	200		T3	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	973	1			T5	1		T11	20		T13	2
values[1]	733	1			T6	1		T12	32		T135	1
values[2]	725	1			T4	1		T5	1		T8	9
values[3]	683	1			T8	27		T37	22		T47	16
values[4]	804	1			T37	1		T35	2		T26	17
values[5]	557	1			T3	1		T48	4		T134	3
values[6]	2864	1			T2	2		T50	1		T110	12
values[7]	768	1			T5	1		T15	5		T31	11
values[8]	765	1			T3	13		T13	18		T47	24
values[9]	126	1			T6	1		T13	2		T47	20
minimum	17589	1			T1	200		T3	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

4136

1

T8

17

T11

18

T12

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T13	1		T27	1		T33	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	1		T11	11		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T12	16		T135	1		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	1		T38	5		T137	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T4	1		T5	1		T33	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T8	3		T11	9		T48	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T37	7		T36	1		T90	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T8	16		T47	9		T36	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T37	1		T26	2		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T35	1		T184	1		T262	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T135	1		T218	1		T194	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	1		T48	4		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1588	1			T2	2		T50	1		T110	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T36	6		T27	1		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T15	3		T218	7		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	1		T31	7		T134	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T3	1		T13	9		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T47	13		T15	2		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T6	1		T44	4		T227	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T13	1		T47	10		T246	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17441	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T263	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T13	1		T27	4		T33	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T11	9		T222	10		T233	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	16		T145	1		T218	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T38	1		T139	5		T147	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T33	7		T148	13		T246	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T8	6		T11	7		T29	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T37	15		T36	1		T90	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T8	11		T47	7		T36	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T26	15		T27	17		T153	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T35	1		T264	11		T265	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T218	1		T194	11		T224	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T134	2		T229	2		T198	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	960	1			T110	11		T42	12		T266	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T36	2		T27	4		T224	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T15	2		T137	12		T194	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T31	4		T134	5		T136	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	12		T13	9		T232	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T47	11		T15	1		T230	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T227	3		T267	2		T268	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T13	1		T47	10		T269	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T29	5		T38	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T15	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T13	1		T40	7		T239	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T11	11		T270	9		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T27	1		T33	10		T234	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	1		T184	1		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T12	9		T135	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T6	1		T38	5		T232	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T4	1		T5	1		T12	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	3		T48	3		T29	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T37	1		T36	1		T26	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T11	9		T47	9		T36	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T37	7		T32	16		T212	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T8	16		T35	1		T32	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T27	1		T135	1		T218	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T3	1		T48	4		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T231	1		T18	2		T20	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T36	6		T27	1		T229	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T32	9		T218	7		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	1		T31	7		T134	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1658	1			T2	2		T3	1		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T13	1		T47	23		T217	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17441	1			T1	200		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T15	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T13	1		T40	5		T271	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T11	9		T270	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T27	4		T33	8		T138	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T222	10		T233	13		T149	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	11		T145	1		T218	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T38	1		T232	11		T139	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T12	5		T33	7		T246	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T8	6		T29	1		T137	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T36	1		T26	15		T90	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	7		T47	7		T36	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T37	15		T212	4		T153	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T8	11		T35	1		T265	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T27	17		T218	1		T194	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T134	2		T198	2		T40	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T231	10		T18	2		T272	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T36	2		T27	4		T229	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T137	12		T194	9		T190	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T31	4		T134	5		T138	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1013	1			T3	12		T13	9		T110	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T13	1		T47	21		T136	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T29	5		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T13	2		T27	5		T33	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T5	1		T11	10		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	18		T135	1		T145	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T6	1		T38	5		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	1		T5	1		T33	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T8	7		T11	8		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T37	16		T36	2		T90	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T8	12		T47	8		T36	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T37	1		T26	17		T27	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T35	2		T184	1		T262	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T135	1		T218	2		T194	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	1		T48	1		T134	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T2	2		T50	1		T110	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T36	6		T27	5		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T15	3		T218	1		T137	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	1		T31	5		T134	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	13		T13	10		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T47	12		T15	3		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T6	1		T44	1		T227	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T13	2		T47	11		T246	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17588	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T263	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T33	9		T234	9		T138	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	10		T97	10		T270	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	14		T219	7		T239	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T38	1		T137	9		T139	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T33	7		T148	14		T255	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T8	2		T11	8		T48	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T37	6		T90	9		T212	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	15		T47	8		T36	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T32	15		T153	8		T46	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T264	20		T265	12		T34	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T157	7		T152	16		T273	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T48	3		T17	5		T147	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T32	8		T236	30		T237	32
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T36	2		T219	12		T274	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	2		T218	6		T200	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T31	6		T217	10		T136	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	8		T232	10		T139	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T47	12		T174	13		T230	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T44	3		T227	3		T275	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T47	9		T216	11		T269	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T15	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T13	2		T40	10		T239	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T11	10		T270	9		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T27	5		T33	9		T234	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	1		T184	1		T222	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T12	12		T135	1		T145	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T6	1		T38	5		T232	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	1		T5	1		T12	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T8	7		T48	1		T29	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T37	1		T36	2		T26	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T11	8		T47	8		T36	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T37	16		T32	1		T212	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	12		T35	2		T32	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T27	18		T135	1		T218	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T3	1		T48	1		T134	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T231	11		T18	4		T20	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T36	6		T27	5		T229	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T32	1		T218	1		T137	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	1		T31	5		T134	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T2	2		T3	13		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T13	2		T47	23		T217	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17588	1			T1	200		T3	40		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T40	2		T239	17		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T11	10		T270	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T33	9		T234	9		T138	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T276	9		T248	11		T277	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	8		T139	10		T219	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T38	1		T232	9		T137	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T12	6		T33	7		T239	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T8	2		T48	2		T29	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T90	9		T171	4		T148	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T11	8		T47	8		T36	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T37	6		T32	15		T212	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T8	15		T32	7		T265	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T252	16		T157	7		T278	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T48	3		T17	5		T147	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T226	22		T21	3		T273	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T36	2		T219	12		T274	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T32	8		T218	6		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T31	6		T138	17		T188	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T13	8		T44	3		T15	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T47	21		T217	10		T136	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

auto[0]

4136

1

T8

17

T11

18

T12

14