Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26587

1

T1

200

T2

2

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23281

1

T1

200

T2

2

T3

41

auto[ADC_CTRL_FILTER_COND_OUT]

3306

1

T3

13

T4

1

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20530

1

T1

200

T3

40

T5

1

auto[1]

6057

1

T2

2

T3

14

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22672

1

T1

200

T2

2

T3

42

auto[1]

3915

1

T3

12

T8

17

T11

16

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	249	1			T6	1		T29	3		T232	20
values[0]	2	1			T246	1		T279	1		-	-
values[1]	874	1			T3	13		T12	20		T37	22
values[2]	651	1			T13	2		T37	1		T47	20
values[3]	897	1			T36	11		T27	5		T32	9
values[4]	541	1			T8	9		T11	16		T38	6
values[5]	678	1			T4	1		T47	24		T48	4
values[6]	532	1			T3	1		T5	1		T27	18
values[7]	592	1			T5	1		T48	3		T26	2
values[8]	2952	1			T2	2		T5	1		T6	1
values[9]	1031	1			T8	27		T11	20		T13	20
minimum	17588	1			T1	200		T3	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	740	1			T3	13		T37	22		T47	20
values[1]	880	1			T13	2		T37	1		T27	5
values[2]	691	1			T36	11		T218	2		T137	13
values[3]	630	1			T8	9		T11	16		T47	24
values[4]	701	1			T3	1		T4	1		T5	1
values[5]	399	1			T48	3		T27	18		T32	16
values[6]	2789	1			T2	2		T5	1		T6	1
values[7]	869	1			T5	1		T36	8		T29	4
values[8]	978	1			T8	27		T11	20		T13	20
values[9]	98	1			T6	1		T38	1		T136	25
minimum	17812	1			T1	200		T3	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

4136

1

T8

17

T11

18

T12

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T37	7		T36	1		T15	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	1		T47	10		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T37	1		T134	1		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	1		T27	1		T32	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T36	6		T137	1		T219	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T218	1		T174	14		T189	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	9		T47	13		T244	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T8	3		T38	5		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T3	1		T234	10		T138	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	1		T5	1		T48	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T32	16		T212	5		T184	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T48	3		T27	1		T199	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1499	1			T2	2		T12	7		T50	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	1		T6	1		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T5	1		T36	6		T33	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T29	3		T38	1		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T15	2		T26	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T8	16		T11	11		T13	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T136	14		T280	10		T281	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T6	1		T38	1		T282	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17506	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T229	1		T244	14		T246	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T37	15		T36	1		T15	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T3	12		T47	10		T35	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T134	2		T153	1		T190	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T13	1		T27	4		T194	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T36	5		T137	12		T252	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T218	1		T139	2		T148	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	7		T47	11		T244	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T8	6		T38	1		T153	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T138	11		T40	5		T16	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T188	21		T147	12		T149	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T212	4		T222	10		T93	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T27	17		T199	11		T17	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T12	5		T110	11		T42	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T26	1		T31	4		T145	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T36	2		T33	7		T39	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T29	1		T40	6		T222	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T15	1		T26	14		T232	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T8	11		T11	9		T13	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T136	11		T256	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T283	3		T284	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	11		T15	1		T29	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T229	2		T244	9		T285	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T232	11		T19	8		T280	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T6	1		T29	2		T218	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T246	1		T279	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T12	9		T37	7		T15	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	1		T35	1		T229	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T37	1		T36	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	1		T47	10		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T36	6		T137	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T27	1		T32	9		T218	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	9		T219	22		T274	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T8	3		T38	5		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T47	13		T40	7		T16	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T4	1		T48	4		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	1		T32	16		T234	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	1		T27	1		T199	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T32	8		T137	21		T212	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	1		T48	3		T26	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1639	1			T2	2		T5	1		T12	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	1		T29	3		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T15	2		T26	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T8	16		T11	11		T13	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17441	1			T1	200		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T232	9		T19	3		T276	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T29	1		T218	1		T171	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	11		T37	15		T15	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	12		T35	1		T229	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T36	1		T134	2		T190	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T13	1		T47	10		T194	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T36	5		T137	12		T153	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T27	4		T218	1		T153	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T11	7		T210	1		T81	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T8	6		T38	1		T153	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T47	11		T40	5		T16	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T188	21		T149	6		T223	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T138	11		T93	1		T264	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T27	17		T199	11		T17	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T137	11		T212	4		T222	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T26	1		T31	4		T145	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T12	5		T110	11		T42	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T29	1		T198	2		T40	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T15	1		T26	14		T232	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T8	11		T11	9		T13	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T29	5		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T37	16		T36	2		T15	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	13		T47	11		T35	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T37	1		T134	3		T153	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	2		T27	5		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T36	8		T137	13		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T218	2		T174	1		T189	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	8		T47	12		T244	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	7		T38	5		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	1		T234	1		T138	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	1		T5	1		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T32	1		T212	5		T184	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T48	1		T27	18		T199	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T2	2		T12	6		T50	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	1		T6	1		T26	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T5	1		T36	6		T33	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T29	4		T38	1		T40	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T15	3		T26	15		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T8	12		T11	10		T13	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T136	12		T280	1		T281	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T6	1		T38	1		T282	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17649	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T229	3		T244	10		T246	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T37	6		T15	2		T33	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T47	9		T217	10		T138	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T243	8		T142	12		T215	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T32	8		T148	14		T142	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T36	3		T219	21		T140	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T174	13		T139	10		T148	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	8		T47	12		T244	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T8	2		T38	1		T153	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T234	9		T138	8		T40	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T48	3		T188	18		T239	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T32	15		T212	4		T220	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T48	2		T199	11		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1165	1			T12	6		T32	7		T236	30
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T31	6		T146	13		T139	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T36	2		T33	7		T200	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T230	2		T97	3		T276	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T232	19		T230	11		T246	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T8	15		T11	10		T13	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T136	13		T280	9		T256	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T284	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T12	8		T286	6		T269	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T244	13		T287	3		T288	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T232	10		T19	8		T280	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T6	1		T29	2		T218	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T246	1		T279	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T12	12		T37	16		T15	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	13		T35	2		T229	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T37	1		T36	2		T134	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	2		T47	11		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T36	8		T137	13		T153	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T27	5		T32	1		T218	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T11	8		T219	1		T274	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	7		T38	5		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T47	12		T40	10		T16	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T4	1		T48	1		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	1		T32	1		T234	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T5	1		T27	18		T199	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T32	1		T137	13		T212	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	1		T48	1		T26	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T2	2		T5	1		T12	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T6	1		T29	4		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T15	3		T26	15		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T8	12		T11	10		T13	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17588	1			T1	200		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T232	10		T19	3		T280	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T29	1		T171	4		T239	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T12	8		T37	6		T15	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T138	17		T259	4		T244	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T142	12		T227	3		T289	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T47	9		T217	10		T148	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T36	3		T140	13		T259	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T32	8		T174	13		T153	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	8		T219	21		T274	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T8	2		T38	1		T139	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T47	12		T40	2		T220	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T48	3		T188	18		T239	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T32	15		T234	9		T138	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T199	11		T39	1		T17	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T32	7		T137	19		T212	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T48	2		T31	6		T146	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T12	6		T36	2		T33	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T146	11		T230	2		T97	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T232	9		T136	13		T147	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T8	15		T11	10		T13	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

auto[0]

4136

1

T8

17

T11

18

T12

14