Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26587

1

T1

200

T2

2

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23071

1

T1

200

T2

2

T3

40

auto[ADC_CTRL_FILTER_COND_OUT]

3516

1

T3

14

T4

1

T8

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20774

1

T1

200

T3

54

T4

1

auto[1]

5813

1

T2

2

T5

3

T6

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22672

1

T1

200

T2

2

T3

42

auto[1]

3915

1

T3

12

T8

17

T11

16

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	30	1			T243	16		T231	3		T290	11
values[0]	52	1			T33	18		T38	1		T16	6
values[1]	560	1			T3	13		T5	1		T13	2
values[2]	677	1			T11	20		T47	24		T35	2
values[3]	755	1			T5	1		T12	12		T26	2
values[4]	722	1			T8	27		T11	16		T13	20
values[5]	2859	1			T2	2		T3	1		T8	9
values[6]	702	1			T4	1		T27	5		T31	11
values[7]	587	1			T6	1		T12	20		T38	6
values[8]	718	1			T48	7		T29	4		T145	2
values[9]	1337	1			T5	1		T6	1		T47	36
minimum	17588	1			T1	200		T3	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	822	1			T5	1		T13	2		T47	24
values[1]	671	1			T3	13		T5	1		T11	20
values[2]	768	1			T36	11		T26	2		T29	3
values[3]	2870	1			T2	2		T8	27		T11	16
values[4]	570	1			T3	1		T4	1		T8	9
values[5]	746	1			T31	11		T38	7		T200	3
values[6]	603	1			T6	1		T12	20		T27	5
values[7]	682	1			T47	20		T48	7		T145	2
values[8]	1096	1			T5	1		T6	1		T47	16
values[9]	171	1			T26	15		T148	28		T220	5
minimum	17588	1			T1	200		T3	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

4136

1

T8

17

T11

18

T12

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T5	1		T13	1		T33	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T47	13		T15	3		T33	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T5	1		T11	11		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	1		T27	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T36	6		T136	1		T229	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T26	1		T29	2		T217	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1581	1			T2	2		T11	9		T37	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T8	16		T12	7		T13	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T8	3		T15	2		T32	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T3	1		T4	1		T32	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T31	7		T38	6		T174	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T200	3		T139	14		T46	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	1		T27	1		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	9		T29	3		T137	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T48	7		T221	1		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T47	10		T145	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T5	1		T6	1		T47	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T90	10		T135	1		T138	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T245	1		T192	19		T291	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T26	1		T148	15		T220	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17441	1			T1	200		T3	40		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	1		T33	8		T134	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T47	11		T15	2		T33	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	9		T35	1		T36	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T3	12		T27	17		T134	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T36	5		T229	2		T215	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T26	1		T29	1		T194	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	883	1			T11	7		T37	15		T110	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	11		T12	5		T13	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T8	6		T15	1		T224	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T138	11		T149	9		T264	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T31	4		T38	1		T190	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T139	15		T46	1		T281	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T27	4		T137	12		T139	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	11		T29	1		T210	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T40	6		T190	6		T222	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T47	10		T145	1		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T47	7		T36	2		T27	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T90	7		T138	15		T199	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T245	13		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T26	14		T148	13		T243	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T29	5		T38	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T231	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T243	9		T290	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T33	10		T38	1		T16	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T285	1		T254	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	1		T13	1		T36	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	1		T33	8		T232	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	11		T35	1		T137	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T47	13		T15	3		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	1		T136	1		T229	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	7		T26	1		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T11	9		T37	8		T44	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T8	16		T13	10		T29	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1609	1			T2	2		T8	3		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	1		T218	1		T234	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T27	1		T31	7		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T4	1		T32	16		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	1		T38	5		T219	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	9		T137	10		T200	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T48	7		T221	2		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T29	3		T145	1		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T5	1		T6	1		T47	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	406	1			T47	10		T26	1		T90	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17441	1			T1	200		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T231	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T243	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T33	8		T16	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T285	2		T254	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T13	1		T36	1		T134	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T3	12		T33	7		T232	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	9		T35	1		T137	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T47	11		T15	2		T134	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T229	2		T153	6		T210	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	5		T26	1		T27	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T11	7		T37	15		T36	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T8	11		T13	10		T29	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	912	1			T8	6		T110	11		T42	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T218	1		T153	1		T244	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T27	4		T31	4		T190	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T138	11		T139	15		T46	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T38	1		T147	9		T222	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T12	11		T142	14		T18	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T137	12		T40	6		T139	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T29	1		T145	1		T17	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T47	7		T36	2		T27	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T47	10		T26	14		T90	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T29	5		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T5	1		T13	2		T33	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T47	12		T15	3		T33	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	1		T11	10		T35	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	13		T27	18		T134	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T36	8		T136	1		T229	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T26	2		T29	2		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T2	2		T11	8		T37	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	12		T12	6		T13	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	7		T15	3		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	1		T4	1		T32	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T31	5		T38	6		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T200	1		T139	16		T46	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	1		T27	5		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	12		T29	4		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T48	2		T221	1		T40	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T47	11		T145	2		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T5	1		T6	1		T47	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T90	8		T135	1		T138	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T245	14		T192	1		T291	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T26	15		T148	14		T220	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17588	1			T1	200		T3	40		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T33	9		T39	1		T139	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T47	12		T15	2		T33	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	10		T137	10		T39	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T141	10		T80	12		T292	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T36	3		T141	8		T215	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T29	1		T217	10		T147	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T11	8		T37	6		T44	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T8	15		T12	6		T13	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T8	2		T32	8		T142	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T32	15		T234	9		T138	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T31	6		T38	1		T174	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T200	2		T139	13		T46	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T139	8		T171	4		T219	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T12	8		T137	9		T140	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T48	5		T141	12		T215	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T47	9		T140	13		T142	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T47	8		T36	2		T146	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T90	9		T138	17		T199	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T192	18		T291	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T148	14		T220	4		T243	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T231	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T243	8		T290	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T33	9		T38	1		T16	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T285	3		T254	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T13	2		T36	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	13		T33	8		T232	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T11	10		T35	2		T137	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T47	12		T15	3		T134	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	1		T136	1		T229	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	6		T26	2		T27	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	8		T37	17		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T8	12		T13	12		T29	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T2	2		T8	7		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	1		T218	2		T234	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T27	5		T31	5		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T4	1		T32	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	1		T38	5		T219	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	12		T137	1		T200	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T48	2		T221	2		T137	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T29	4		T145	2		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T5	1		T6	1		T47	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	426	1			T47	11		T26	15		T90	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17588	1			T1	200		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T243	8		T290	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T33	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T254	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T39	3		T139	10		T259	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T33	7		T232	9		T212	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	10		T137	10		T259	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T47	12		T15	2		T136	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T153	8		T210	2		T215	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	6		T217	10		T141	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	8		T37	6		T44	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	15		T13	8		T29	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T8	2		T32	8		T236	30
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T234	9		T219	12		T239	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T31	6		T244	6		T235	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T32	15		T138	8		T139	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T38	1		T219	7		T239	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T12	8		T137	9		T200	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T48	5		T139	8		T171	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T17	5		T140	13		T210	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T47	8		T36	2		T146	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T47	9		T90	9		T138	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

auto[0]

4136

1

T8

17

T11

18

T12

14