Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26587

1

T1

200

T2

2

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22810

1

T1

200

T2

2

T3

40

auto[ADC_CTRL_FILTER_COND_OUT]

3777

1

T3

14

T6

1

T11

36

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20622

1

T1

200

T3

41

T5

1

auto[1]

5965

1

T2

2

T3

13

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22672

1

T1

200

T2

2

T3

42

auto[1]

3915

1

T3

12

T8

17

T11

16

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	303	1			T3	1		T218	7		T137	10
values[0]	20	1			T216	19		T297	1		-	-
values[1]	786	1			T5	1		T47	36		T29	3
values[2]	643	1			T13	18		T37	1		T29	4
values[3]	759	1			T3	13		T6	1		T27	18
values[4]	519	1			T12	32		T13	4		T36	8
values[5]	2744	1			T2	2		T50	1		T110	12
values[6]	780	1			T6	1		T47	24		T44	4
values[7]	611	1			T5	1		T11	20		T37	22
values[8]	661	1			T4	1		T5	1		T8	27
values[9]	1173	1			T8	9		T11	16		T48	4
minimum	17588	1			T1	200		T3	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	632	1			T13	18		T47	16		T29	7
values[1]	753	1			T5	1		T37	1		T32	9
values[2]	645	1			T3	13		T6	1		T13	2
values[3]	2703	1			T2	2		T12	32		T13	2
values[4]	757	1			T33	15		T134	1		T38	6
values[5]	631	1			T6	1		T44	4		T36	2
values[6]	677	1			T4	1		T5	2		T11	20
values[7]	638	1			T8	36		T48	4		T15	5
values[8]	1103	1			T3	1		T11	16		T35	2
values[9]	215	1			T26	2		T134	6		T221	1
minimum	17833	1			T1	200		T3	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

4136

1

T8

17

T11

18

T12

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T29	5		T90	10		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	9		T47	9		T218	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T5	1		T37	1		T194	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T32	9		T217	11		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	1		T13	1		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	1		T146	12		T219	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1508	1			T2	2		T12	7		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	9		T13	1		T200	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T145	1		T136	14		T219	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T33	8		T134	1		T38	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T44	4		T27	2		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T6	1		T36	1		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T4	1		T5	2		T47	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	11		T37	7		T32	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	19		T135	1		T17	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T48	4		T15	3		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T36	6		T33	10		T137	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	388	1			T3	1		T11	9		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T26	1		T39	3		T152	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T134	1		T221	1		T218	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17540	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T47	10		T40	1		T142	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T29	2		T90	7		T153	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T13	9		T47	7		T218	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T194	11		T153	1		T139	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T218	1		T231	17		T93	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T13	1		T27	17		T31	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T3	12		T223	4		T285	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	870	1			T12	5		T110	11		T42	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T12	11		T13	1		T139	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T145	1		T136	11		T230	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T33	7		T38	1		T198	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T27	8		T224	8		T149	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T36	1		T26	14		T232	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T47	11		T198	2		T225	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	9		T37	15		T190	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	17		T17	7		T227	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T15	2		T138	11		T194	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T36	5		T33	8		T137	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T11	7		T35	1		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T26	1		T39	2		T298	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T134	5		T148	13		T18	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	1		T29	5		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T47	10		T40	6		T142	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T17	3		T252	17		T150	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T3	1		T218	7		T137	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T216	19		T297	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T5	1		T29	2		T90	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T47	19		T218	1		T174	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T37	1		T29	3		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	9		T32	9		T217	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	1		T27	1		T31	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	1		T218	1		T146	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	7		T13	1		T36	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	9		T13	1		T200	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1553	1			T2	2		T50	1		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T33	8		T134	1		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T47	13		T44	4		T27	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T6	1		T38	5		T232	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T5	1		T48	3		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	11		T37	7		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T4	1		T5	1		T8	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T15	3		T32	16		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T8	3		T36	6		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	418	1			T11	9		T48	4		T35	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17441	1			T1	200		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T17	1		T252	13		T299	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T148	14		T276	13		T226	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T29	1		T90	7		T153	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T47	17		T218	1		T40	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T29	1		T153	1		T147	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T13	9		T231	27		T93	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T27	17		T31	4		T232	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T3	12		T218	1		T223	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T12	5		T13	1		T36	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T12	11		T13	1		T190	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	924	1			T110	11		T42	12		T134	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T33	7		T198	14		T199	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T47	11		T27	8		T145	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T38	1		T232	11		T139	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T225	4		T223	9		T215	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	9		T37	15		T36	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T8	11		T198	2		T17	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T15	2		T16	2		T80	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	6		T36	5		T26	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T11	7		T35	1		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T29	5		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T29	6		T90	8		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	10		T47	8		T218	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T5	1		T37	1		T194	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T32	1		T217	1		T218	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	1		T13	2		T27	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T3	13		T146	1		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T2	2		T12	6		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	12		T13	2		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T145	2		T136	12		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T33	8		T134	1		T38	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T44	1		T27	10		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T6	1		T36	2		T26	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T4	1		T5	2		T47	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T11	10		T37	16		T32	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T8	19		T135	1		T17	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T48	1		T15	3		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T36	8		T33	9		T137	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T3	1		T11	8		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T26	2		T39	3		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T134	6		T221	1		T218	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17657	1			T1	200		T3	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T47	11		T40	7		T142	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T29	1		T90	9		T153	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T13	8		T47	8		T174	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T139	13		T147	14		T233	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T32	8		T217	10		T255	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T31	6		T232	10		T234	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T146	11		T219	21		T97	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1174	1			T12	6		T36	2		T236	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	8		T200	2		T146	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T136	13		T219	12		T239	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T33	7		T38	1		T199	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T44	3		T46	4		T300	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T232	9		T40	2		T171	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T47	12		T48	2		T32	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	10		T37	6		T32	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T8	17		T17	5		T220	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T48	3		T15	2		T138	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T36	3		T33	9		T137	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T11	8		T137	9		T138	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T39	2		T152	5		T301	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T218	6		T148	14		T18	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T243	8		T244	6		T152	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T47	9		T142	7		T216	18

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T17	4		T252	14		T150	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T3	1		T218	1		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T216	1		T297	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T5	1		T29	2		T90	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T47	19		T218	2		T174	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T37	1		T29	4		T153	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	10		T32	1		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T6	1		T27	18		T31	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	13		T218	2		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T12	6		T13	2		T36	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	12		T13	2		T200	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T2	2		T50	1		T110	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T33	8		T134	1		T198	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T47	12		T44	1		T27	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T6	1		T38	5		T232	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	1		T48	1		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T11	10		T37	16		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T4	1		T5	1		T8	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T15	3		T32	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T8	7		T36	8		T26	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T11	8		T48	1		T35	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17588	1			T1	200		T3	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T252	16		T152	5		T301	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T218	6		T137	9		T141	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T216	18		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T29	1		T90	9		T153	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T47	17		T174	13		T219	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T147	14		T233	12		T244	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	8		T32	8		T217	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T31	6		T232	10		T234	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T146	11		T219	21		T276	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T12	6		T36	2		T147	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	8		T200	2		T146	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T236	30		T237	32		T173	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T33	7		T199	11		T139	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T47	12		T44	3		T136	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T38	1		T232	9		T139	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T48	2		T225	3		T215	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	10		T37	6		T40	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T8	15		T32	7		T17	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T15	2		T32	15		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T8	2		T36	3		T33	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T11	8		T48	3		T138	25

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22451

1

T1

200

T2

2

T3

54

auto[1]

auto[0]

4136

1

T8

17

T11

18

T12

14